coreboot-gerrit November 2023

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[S] Change in coreboot[main]: drivers/pc80/rtc/option.c: Reset only checked CMOS range during resume
by Bill XIE (Code Review) 03 Nov '23

03 Nov '23

Attention is currently required from: Jonathon Hall, Jérémy Compostella, Nico Huber. Hello Jonathon Hall, Jérémy Compostella, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78906?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/pc80/rtc/option.c: Reset only checked CMOS range during resume ...................................................................... drivers/pc80/rtc/option.c: Reset only checked CMOS range during resume Proposed in the comment of commit 29030d0f3dad ("drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume"), during sanitize_cmos(), only reset CMOS range covered by checksum and the checksum itself from the file cmos.default in CBFS during s3 resume, in order to prevent other runtime data in CMOS (e.g. the DRAM training data on GM45 platforms for s3 resume) being erased, while the whole CMOS after 14 could be reset during normal boot. Tested: cherry-pick this commit before commit 44a48ce7a46c ("Kconfig: Bring HEAP_SIZE to a common, large value"), which is already before my commit 29030d0f3dad , Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from s3 again, indicating that DRAM training data are no longer erased. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Co-authored-by: Jonathon Hall <jonathon.hall(a)puri.sm> Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a --- M src/drivers/pc80/rtc/option.c 1 file changed, 16 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/78906/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/78906?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a Gerrit-Change-Number: 78906 Gerrit-PatchSet: 7 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/amd/genoa: Configure HEAP_SIZE
by Felix Held (Code Review) 03 Nov '23

03 Nov '23

Attention is currently required from: Varshit Pandya. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78894?usp=email ) Change subject: soc/amd/genoa: Configure HEAP_SIZE ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: do we need the larger heap size? -- To view, visit https://review.coreboot.org/c/coreboot/+/78894?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idd707200fe72730849267cd3cafc40e44f1f8c5d Gerrit-Change-Number: 78894 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Nov 2023 15:03:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/amd/genoa: Add mmio.asl
by Felix Held (Code Review) 03 Nov '23

03 Nov '23

Attention is currently required from: Arthur Heymans, Varshit Pandya. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78895?usp=email ) Change subject: soc/amd/genoa: Add mmio.asl ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: unrelated to this patch, but it seems that the genoa patches are missing the i2c support enablement on the coreboot side File src/soc/amd/genoa/acpi/mmio.asl: https://review.coreboot.org/c/coreboot/+/78895/comment/c2ec8903_9f29ca35 : PS1, Line 282: #if CONFIG(SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP) this doesn't apply for genoa, since genoa won't have verstage on psp. same below -- To view, visit https://review.coreboot.org/c/coreboot/+/78895?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5bc2cc0141e9da7e2c6ed7691188d7c94b6b1e3 Gerrit-Change-Number: 78895 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 03 Nov 2023 15:00:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd/genoa: Hook SMP and SMM init
by Felix Held (Code Review) 03 Nov '23

03 Nov '23

Attention is currently required from: Arthur Heymans, Varshit Pandya. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76523?usp=email ) Change subject: soc/amd/genoa: Hook SMP and SMM init ...................................................................... Patch Set 5: (7 comments) File src/soc/amd/genoa/Makefile.inc: https://review.coreboot.org/c/coreboot/+/76523/comment/d2c7ac0c_9492ceb6 : PS5, Line 19: ramstage-y += cpu.c would be good to have this sorted alphabetically File src/soc/amd/genoa/cpu.c: https://review.coreboot.org/c/coreboot/+/76523/comment/58316913_fcf943bb : PS2, Line 42: { X86_VENDOR_AMD, GENOA_A0_CPUID}, : { X86_VENDOR_AMD, GENOA_A1_CPUID}, : { X86_VENDOR_AMD, GENOA_B0_CPUID}, > i'd use CPUID_ALL_STEPPINGS_MASK and only have two entries which then will cover all steppings of th […] Done File src/soc/amd/genoa/cpu.c: https://review.coreboot.org/c/coreboot/+/76523/comment/741220ca_02170602 : PS4, Line 14: /* MP and SMM loading initialization. */ : void mp_init_cpus(struct bus *cpu_bus) : { : extern const struct mp_ops amd_mp_ops_with_smm; : if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS) : die_with_post_code(POSTCODE_HW_INIT_FAILURE, : "mp_init_with_smm failed. Halting.\n"); : : /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ : mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE, : FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT); : : /* SMMINFO only needs to be set up when booting from S5 */ : if (!acpi_is_wakeup_s3()) : apm_control(APM_CNT_SMMINFO); : : } > this is common code since CB:78013 and can be removed Done https://review.coreboot.org/c/coreboot/+/76523/comment/e22ab6b7_8e0ed95b : PS4, Line 45: { 0, 0 }, > replace with CPU_TABLE_END Done File src/soc/amd/genoa/include/soc/cpu.h: https://review.coreboot.org/c/coreboot/+/76523/comment/0523aa05_a99318bf : PS5, Line 7: #define GENOA_A1_CPUID 0x00a10f01 not sure if we need to keep this one, since it's now unused File src/soc/amd/genoa/smihandler.c: PS4: > if possible, i'd like this to also be factored out into a patch between the smu patch and the rest o […] Done File src/soc/amd/genoa/smihandler.c: https://review.coreboot.org/c/coreboot/+/76523/comment/1c894654_9d8f4f8f : PS5, Line 3: /* TODO: Update for Phoenix */ was this verified to still be correct for genoa? -- To view, visit https://review.coreboot.org/c/coreboot/+/76523?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c2d976addacd5a2ba70eb629510128853b9f847 Gerrit-Change-Number: 76523 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 03 Nov 2023 14:58:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/amd/genoa: Add mmio.asl
by Varshit Pandya (Code Review) 03 Nov '23

03 Nov '23

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/78895?usp=email to review the following change. Change subject: soc/amd/genoa: Add mmio.asl ...................................................................... soc/amd/genoa: Add mmio.asl Change-Id: Ic5bc2cc0141e9da7e2c6ed7691188d7c94b6b1e3 Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>t show --- A src/soc/amd/genoa/acpi/mmio.asl M src/soc/amd/genoa/acpi/soc.asl 2 files changed, 344 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/78895/1 diff --git a/src/soc/amd/genoa/acpi/mmio.asl b/src/soc/amd/genoa/acpi/mmio.asl new file mode 100644 index 0000000..40b373c --- /dev/null +++ b/src/soc/amd/genoa/acpi/mmio.asl @@ -0,0 +1,342 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include <soc/amd/common/acpi/aoac.asl> +#include <soc/aoac_defs.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <amdblocks/acpimmio_map.h> + +Device (AAHB) +{ + Name (_HID, "AAHB0000") + Name (_UID, 0x0) + Name (_CRS, ResourceTemplate() + { + Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000) + }) + Name (_STA, 0xb) +} + +Device (GPIO) +{ + Name (_HID, GPIO_DEVICE_NAME) + Name (_CID, GPIO_DEVICE_NAME) + Name (_UID, 0) + Name (_DDN, GPIO_DEVICE_DESC) + + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Level, + ActiveLow, + Shared, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IGPI + } Else { + IRQN = PGPI + } + If (IRQN == 0x1f || IRQN == 0) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400) + }) + } Else { + Return (Local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (FUR0) +{ + Name (_HID, "AMDI0020") + Name (_UID, 0x0) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IUA0 + } Else { + IRQN = PUA0 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_UART0, 0) +} + +Device (FUR1) { + Name (_HID, "AMDI0020") + Name (_UID, 0x1) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IUA1 + } Else { + IRQN = PUA1 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_UART1, 0) +} + +Device (FUR2) { + Name (_HID, "AMDI0020") + Name (_UID, 0x2) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IUA2 + } Else { + IRQN = PUA2 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_UART2, 0) +} + +Device (I2C0) { + Name (_HID, "AMDI0010") + Name (_UID, 0x0) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II20 + } Else { + IRQN = PI20 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I2C0, 0) +} + +Device (I2C1) { + Name (_HID, "AMDI0010") + Name (_UID, 0x1) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II21 + } Else { + IRQN = PI21 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I2C1, 0) +} + +Device (I2C2) { + Name (_HID, "AMDI0010") + Name (_UID, 0x2) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II22 + } Else { + IRQN = PI22 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I2C2, 0) +} + +Device (I2C3) +{ +#if CONFIG(SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP) + Name (_HID, "AMDI0019") +#else + Name (_HID, "AMDI0010") +#endif + Name (_UID, 0x3) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II23 + } Else { + IRQN = PI23 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + +/* If this device is shared with PSP, then PSP takes care of power management */ +#if !CONFIG(SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP) + AOAC_DEVICE(FCH_AOAC_DEV_I2C3, 0) +#endif +} + +Device (MISC) +{ + Name (_HID, "AMD0040") + Name (_UID, 0x3) + Name (_CRS, ResourceTemplate() { + Memory32Fixed (ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + }) + Name (_DSD, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () { "is-rv", 1 }, + }, + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} diff --git a/src/soc/amd/genoa/acpi/soc.asl b/src/soc/amd/genoa/acpi/soc.asl index 88b0df8..d7684cf 100644 --- a/src/soc/amd/genoa/acpi/soc.asl +++ b/src/soc/amd/genoa/acpi/soc.asl @@ -3,4 +3,6 @@ Scope(\_SB) { /* global utility methods expected within the \_SB scope */ #include "pci_int_defs.asl" + + #include "mmio.asl" } /* End \_SB scope */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78895?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5bc2cc0141e9da7e2c6ed7691188d7c94b6b1e3 Gerrit-Change-Number: 78895 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/amd/genoa: Configure HEAP_SIZE
by Varshit Pandya (Code Review) 03 Nov '23

03 Nov '23

Varshit Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78894?usp=email ) Change subject: soc/amd/genoa: Configure HEAP_SIZE ...................................................................... soc/amd/genoa: Configure HEAP_SIZE Default value of HEAP_SIZE is 100000, since genoa has a lot of CPU increase the HEAP_SIZE to 200000 Change-Id: Idd707200fe72730849267cd3cafc40e44f1f8c5d Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/soc/amd/genoa/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/78894/1 diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index 2e80af4..8ad7b2f 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -152,4 +152,8 @@ endmenu +config HEAP_SIZE + hex + default 0x200000 + endif # SOC_AMD_GENOA -- To view, visit https://review.coreboot.org/c/coreboot/+/78894?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idd707200fe72730849267cd3cafc40e44f1f8c5d Gerrit-Change-Number: 78894 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/amd/genoa: Hook SMP and SMM init
by Varshit Pandya (Code Review) 03 Nov '23

03 Nov '23

Attention is currently required from: Arthur Heymans, Varshit Pandya. Varshit Pandya has uploaded a new patch set (#5) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/76523?usp=email ) The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/amd/genoa: Hook SMP and SMM init ...................................................................... soc/amd/genoa: Hook SMP and SMM init All CPUs properly come out of reset and relocate SMM. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I8c2d976addacd5a2ba70eb629510128853b9f847 --- M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/Makefile.inc M src/soc/amd/genoa/chipset.cb A src/soc/amd/genoa/cpu.c A src/soc/amd/genoa/include/soc/cpu.h A src/soc/amd/genoa/smihandler.c 6 files changed, 152 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/76523/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/76523?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c2d976addacd5a2ba70eb629510128853b9f847 Gerrit-Change-Number: 76523 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: drivers/pc80/rtc/option.c: Reset only checked CMOS range during resume
by Bill XIE (Code Review) 03 Nov '23

03 Nov '23

Attention is currently required from: Jonathon Hall, Jérémy Compostella, Nico Huber. Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78906?usp=email ) Change subject: drivers/pc80/rtc/option.c: Reset only checked CMOS range during resume ...................................................................... Patch Set 6: (2 comments) Patchset: PS4: > I agree to the patch, just want to mention that this will most […] Then we could restore the checked range only during s3 resume, while restore the whole CMOS after 14 during normal boot, as did in the Patchset 6. File src/drivers/pc80/rtc/option.c: https://review.coreboot.org/c/coreboot/+/78906/comment/b6cb2f20_3e77fecf : PS4, Line 217: for (i = LB_CKS_RANGE_START; i < MIN(LB_CKS_RANGE_END, length); i++) > @Bill It looks like the range end is inclusive, so `LB_CKS_RANGE_END+1` here. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78906?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a Gerrit-Change-Number: 78906 Gerrit-PatchSet: 6 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Comment-Date: Fri, 03 Nov 2023 14:34:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/pc80/rtc/option.c: Reset only checked CMOS range during resume
by Bill XIE (Code Review) 03 Nov '23

03 Nov '23

Attention is currently required from: Bill XIE, Jérémy Compostella, Nico Huber. Hello Jonathon Hall, Jérémy Compostella, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78906?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/pc80/rtc/option.c: Reset only checked CMOS range during resume ...................................................................... drivers/pc80/rtc/option.c: Reset only checked CMOS range during resume Proposed in the comment of commit 29030d0f3dad ("drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume"), during sanitize_cmos(), only reset CMOS range covered by checksum and the checksum itself from the file cmos.default in CBFS during s3 resume, in order to prevent other runtime data in CMOS (e.g. the DRAM training data on GM45 platforms for s3 resume) being erased, while the whole CMOS after 14 could be reset during normal boot. Tested: cherry-pick this commit before commit 44a48ce7a46c ("Kconfig: Bring HEAP_SIZE to a common, large value"), which is already before my commit 29030d0f3dad , Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from s3 again, indicating that DRAM training data are no longer erased. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Co-authored-by: Jonathon Hall <jonathon.hall(a)puri.sm> Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a --- M src/drivers/pc80/rtc/option.c 1 file changed, 12 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/78906/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/78906?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a Gerrit-Change-Number: 78906 Gerrit-PatchSet: 6 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum
by Bill XIE (Code Review) 03 Nov '23

03 Nov '23

Attention is currently required from: Bill XIE, Jérémy Compostella, Nico Huber. Hello Jonathon Hall, Jérémy Compostella, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78906?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins) Change subject: drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum ...................................................................... drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum Proposed in the comment of commit 29030d0f3dad ("drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume"), during sanitize_cmos(), only reset CMOS range covered by checksum and the checksum itself from the file cmos.default in CBFS, in order to prevent other runtime data in CMOS (e.g. the DRAM training data on GM45 platforms for s3 resume) being erased. Tested: cherry-pick this commit before commit 44a48ce7a46c ("Kconfig: Bring HEAP_SIZE to a common, large value"), which is already before my commit 29030d0f3dad , Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from s3 again, indicating that DRAM training data are no longer erased. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Co-authored-by: Jonathon Hall <jonathon.hall(a)puri.sm> Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a --- M src/drivers/pc80/rtc/option.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/78906/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/78906?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a Gerrit-Change-Number: 78906 Gerrit-PatchSet: 5 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newpatchset

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