coreboot-gerrit November 2023

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[M] Change in coreboot[main]: [WIP] soc/amd/genoa: add I2C support
by Felix Held (Code Review) 04 Nov '23

04 Nov '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78900?usp=email ) Change subject: [WIP] soc/amd/genoa: add I2C support ...................................................................... [WIP] soc/amd/genoa: add I2C support Still need to find out which type of pad control register is used for I2C4 and I2C5. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iebc10de6ea5c6d441cff04e016dcec62405078c3 --- M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/Makefile.inc M src/soc/amd/genoa/chip.h A src/soc/amd/genoa/i2c.c A src/soc/amd/genoa/include/soc/i2c.h M src/soc/amd/genoa/include/soc/iomap.h 6 files changed, 122 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/78900/1 diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index 2e80af4..887bed9 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -18,6 +18,9 @@ select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO select SOC_AMD_COMMON_BLOCK_HAS_ESPI + select SOC_AMD_COMMON_BLOCK_I2C + select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL + select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_NONCAR @@ -39,6 +42,10 @@ string default "soc/amd/genoa/chipset.cb" +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 150 + config EARLY_RESERVED_DRAM_BASE hex default 0x7000000 diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc index 506f6cf..e185714 100644 --- a/src/soc/amd/genoa/Makefile.inc +++ b/src/soc/amd/genoa/Makefile.inc @@ -5,6 +5,7 @@ all-y += reset.c all-y += config.c all-y += gpio.c +all-y += i2c.c all-y += uart.c bootblock-y += early_fch.c diff --git a/src/soc/amd/genoa/chip.h b/src/soc/amd/genoa/chip.h index 9168586..5713a72 100644 --- a/src/soc/amd/genoa/chip.h +++ b/src/soc/amd/genoa/chip.h @@ -4,9 +4,17 @@ #define __GENOA_CHIP_H__ #include <amdblocks/chip.h> +#include <amdblocks/i2c.h> +#include <drivers/i2c/designware/dw_i2c.h> +#include <soc/iomap.h> +#include <types.h> struct soc_amd_genoa_config { struct soc_amd_common_config common_config; + + u8 i2c_scl_reset; + struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT]; + struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT]; }; #endif diff --git a/src/soc/amd/genoa/i2c.c b/src/soc/amd/genoa/i2c.c new file mode 100644 index 0000000..8052cfc --- /dev/null +++ b/src/soc/amd/genoa/i2c.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/i2c.h> +#include <console/console.h> +#include <soc/i2c.h> +#include <soc/southbridge.h> +#include "chip.h" + +/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */ +static const struct soc_i2c_scl_pin i2c_scl_pins[] = { + I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL), + I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL), + I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL), + I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL), + I2C_RESET_SCL_PIN(I2C4_SCL_PIN, GPIO_I2C4_SCL), + I2C_RESET_SCL_PIN(I2C5_SCL_PIN, GPIO_I2C5_SCL), +}; + +static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = { + { I2C_MASTER_MODE, APU_I2C0_BASE, "I2C0" }, + { I2C_MASTER_MODE, APU_I2C1_BASE, "I2C1" }, + { I2C_MASTER_MODE, APU_I2C2_BASE, "I2C2" }, + { I2C_MASTER_MODE, APU_I2C3_BASE, "I2C3" }, + { I2C_MASTER_MODE, APU_I2C4_BASE, "I2C4" }, + { I2C_MASTER_MODE, APU_I2C5_BASE, "I2C5" } +}; + +void reset_i2c_peripherals(void) +{ + const struct soc_amd_genoa_config *cfg = config_of_soc(); + struct soc_i2c_peripheral_reset_info reset_info; + + reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK; + reset_info.i2c_scl = i2c_scl_pins; + reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins); + sb_reset_i2c_peripherals(&reset_info); +} + +void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) +{ + const struct soc_amd_genoa_config *config = config_of_soc(); + + if (bus >= ARRAY_SIZE(config->i2c_pad)) + return; + + /* The I/O pads of I2C0..3 are the new I23C pads and the I/O pads of I2C3 still are the + same I2C pads as in Picasso and Cezanne. TODO: verify if this is true */ + if (bus <= 3) + fch_i23c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]); + else + fch_i2c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]); +} + +const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) +{ + *num_ctrlrs = ARRAY_SIZE(i2c_ctrlr); + return i2c_ctrlr; +} + +const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses) +{ + const struct soc_amd_genoa_config *config = config_of_soc(); + + *num_buses = ARRAY_SIZE(config->i2c); + return config->i2c; +} diff --git a/src/soc/amd/genoa/include/soc/i2c.h b/src/soc/amd/genoa/include/soc/i2c.h new file mode 100644 index 0000000..ffff754 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/i2c.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_I2C_H +#define AMD_GENOA_I2C_H + +#include <gpio.h> +#include <types.h> + +#define GPIO_I2C0_SCL BIT(0) +#define GPIO_I2C1_SCL BIT(1) +#define GPIO_I2C2_SCL BIT(2) +#define GPIO_I2C3_SCL BIT(3) +#define GPIO_I2C4_SCL BIT(4) +#define GPIO_I2C5_SCL BIT(5) +#define GPIO_I2C_MASK (GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ + GPIO_I2C2_SCL | GPIO_I2C3_SCL | \ + GPIO_I2C4_SCL | GPIO_I2C5_SCL) + + +#define I2C0_SCL_PIN GPIO_145 +#define I2C1_SCL_PIN GPIO_147 +#define I2C2_SCL_PIN GPIO_149 +#define I2C3_SCL_PIN GPIO_151 +#define I2C4_SCL_PIN GPIO_13 +#define I2C5_SCL_PIN GPIO_19 + +#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx +#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx +#define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_149_IOMUX_GPIOxx +#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_151_IOMUX_GPIOxx +#define I2C4_SCL_PIN_IOMUX_GPIOxx GPIO_13_IOMUX_GPIOxx +#define I2C5_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx + +void reset_i2c_peripherals(void); + +#endif /* AMD_GENOA_I2C_H */ diff --git a/src/soc/amd/genoa/include/soc/iomap.h b/src/soc/amd/genoa/include/soc/iomap.h index 5b767e3..0e24780 100644 --- a/src/soc/amd/genoa/include/soc/iomap.h +++ b/src/soc/amd/genoa/include/soc/iomap.h @@ -3,6 +3,10 @@ #ifndef AMD_GENOA_IOMAP_H #define AMD_GENOA_IOMAP_H +#define I2C_MASTER_DEV_COUNT 6 +#define I2C_PERIPHERAL_DEV_COUNT 0 +#define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) + #define SPI_BASE_ADDRESS 0xfec10000 /* @Todo : Check these values for Genoa */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78900?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebc10de6ea5c6d441cff04e016dcec62405078c3 Gerrit-Change-Number: 78900 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/amd/*/iomap: drop unused I2C_MASTER_START_INDEX definitions
by Felix Held (Code Review) 04 Nov '23

04 Nov '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78899?usp=email ) Change subject: soc/amd/*/iomap: drop unused I2C_MASTER_START_INDEX definitions ...................................................................... soc/amd/*/iomap: drop unused I2C_MASTER_START_INDEX definitions Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0eae9e4d246bd07f43b1d77e5ad7649c010d0efe --- M src/soc/amd/cezanne/include/soc/iomap.h M src/soc/amd/glinda/include/soc/iomap.h M src/soc/amd/mendocino/include/soc/iomap.h M src/soc/amd/phoenix/include/soc/iomap.h M src/soc/amd/picasso/include/soc/iomap.h 5 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/78899/1 diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index e4fe00f..9c900e7 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -4,7 +4,6 @@ #define AMD_CEZANNE_IOMAP_H #define I2C_MASTER_DEV_COUNT 4 -#define I2C_MASTER_START_INDEX 0 #define I2C_PERIPHERAL_DEV_COUNT 0 /* TODO: Only master for now. */ #define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) diff --git a/src/soc/amd/glinda/include/soc/iomap.h b/src/soc/amd/glinda/include/soc/iomap.h index 30fff9f..029dd1c 100644 --- a/src/soc/amd/glinda/include/soc/iomap.h +++ b/src/soc/amd/glinda/include/soc/iomap.h @@ -6,7 +6,6 @@ #define AMD_GLINDA_IOMAP_H #define I2C_MASTER_DEV_COUNT 4 -#define I2C_MASTER_START_INDEX 0 #define I2C_PERIPHERAL_DEV_COUNT 0 /* TODO: Only master for now. */ #define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) diff --git a/src/soc/amd/mendocino/include/soc/iomap.h b/src/soc/amd/mendocino/include/soc/iomap.h index 859dfd5..d70773d 100644 --- a/src/soc/amd/mendocino/include/soc/iomap.h +++ b/src/soc/amd/mendocino/include/soc/iomap.h @@ -4,7 +4,6 @@ #define AMD_MENDOCINO_IOMAP_H #define I2C_MASTER_DEV_COUNT 4 -#define I2C_MASTER_START_INDEX 0 #define I2C_PERIPHERAL_DEV_COUNT 0 /* TODO: Only master for now. */ #define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) diff --git a/src/soc/amd/phoenix/include/soc/iomap.h b/src/soc/amd/phoenix/include/soc/iomap.h index 5e2c7c3..0b93057 100644 --- a/src/soc/amd/phoenix/include/soc/iomap.h +++ b/src/soc/amd/phoenix/include/soc/iomap.h @@ -4,7 +4,6 @@ #define AMD_PHOENIX_IOMAP_H #define I2C_MASTER_DEV_COUNT 4 -#define I2C_MASTER_START_INDEX 0 #define I2C_PERIPHERAL_DEV_COUNT 0 /* TODO: Only master for now. */ #define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 26022ef..be1cd4e 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -33,7 +33,6 @@ * I2C0 and I2C1 even though they are not functional. */ #define I2C_MASTER_DEV_COUNT 4 -#define I2C_MASTER_START_INDEX 2 #define I2C_PERIPHERAL_DEV_COUNT 1 #define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) -- To view, visit https://review.coreboot.org/c/coreboot/+/78899?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0eae9e4d246bd07f43b1d77e5ad7649c010d0efe Gerrit-Change-Number: 78899 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/amd/common/block/i2c: add pre-processor guards for ACPI
by Felix Held (Code Review) 04 Nov '23

04 Nov '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78898?usp=email ) Change subject: soc/amd/common/block/i2c: add pre-processor guards for ACPI ...................................................................... soc/amd/common/block/i2c: add pre-processor guards for ACPI Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8dc93b12b81abee41f6f225f41d1f9953d1d93e1 --- M src/soc/amd/common/block/i2c/i2c.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/78898/1 diff --git a/src/soc/amd/common/block/i2c/i2c.c b/src/soc/amd/common/block/i2c/i2c.c index 57819fb..3c3e9d3 100644 --- a/src/soc/amd/common/block/i2c/i2c.c +++ b/src/soc/amd/common/block/i2c/i2c.c @@ -44,6 +44,7 @@ return &cfg[bus]; } +#if CONFIG(HAVE_ACPI_TABLES) static const char *i2c_acpi_name(const struct device *dev) { size_t i; @@ -71,6 +72,7 @@ acpigen_write_store_int_to_namestr(acpi_device_status(dev), "STAT"); acpigen_pop_len(); /* Scope */ } +#endif int dw_i2c_soc_dev_to_bus(const struct device *dev) { @@ -138,8 +140,10 @@ .read_resources = i2c_read_resources, .set_resources = noop_set_resources, .scan_bus = scan_smbus, +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = i2c_acpi_name, .acpi_fill_ssdt = i2c_acpi_fill_ssdt, +#endif .ops_i2c_bus = &dw_i2c_bus_ops, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/78898?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8dc93b12b81abee41f6f225f41d1f9953d1d93e1 Gerrit-Change-Number: 78898 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/amd/genoa/include/iomap: add missing I2C and I3C MMIO bases
by Felix Held (Code Review) 04 Nov '23

04 Nov '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78897?usp=email ) Change subject: soc/amd/genoa/include/iomap: add missing I2C and I3C MMIO bases ...................................................................... soc/amd/genoa/include/iomap: add missing I2C and I3C MMIO bases All base addresses of MMIO devices in the devicetree should also have corresponding defines in iomap.h. PPR #55901 Rev 0.26 was used as a reference. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0444e6cc0587b484a4a1ff49fa4b1540a24c8e80 --- M src/soc/amd/genoa/include/soc/iomap.h 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/78897/1 diff --git a/src/soc/amd/genoa/include/soc/iomap.h b/src/soc/amd/genoa/include/soc/iomap.h index 076938e..5b767e3 100644 --- a/src/soc/amd/genoa/include/soc/iomap.h +++ b/src/soc/amd/genoa/include/soc/iomap.h @@ -18,9 +18,16 @@ #define APU_I2C1_BASE 0xfedc3000 #define APU_I2C2_BASE 0xfedc4000 #define APU_I2C3_BASE 0xfedc5000 +#define APU_I2C4_BASE 0xfedc6000 +#define APU_I2C5_BASE 0xfedcb000 #define APU_UART0_BASE 0xfedc9000 #define APU_UART1_BASE 0xfedca000 #define APU_UART2_BASE 0xfedce000 +#define APU_I3C0_BASE 0xfedd2000 +#define APU_I3C1_BASE 0xfedd3000 +#define APU_I3C2_BASE 0xfedd4000 +#define APU_I3C3_BASE 0xfedd6000 + #endif /* AMD_GENOA_IOMAP_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78897?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0444e6cc0587b484a4a1ff49fa4b1540a24c8e80 Gerrit-Change-Number: 78897 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/amd/genoa/devicetree: fix MMIO base addresses
by Felix Held (Code Review) 04 Nov '23

04 Nov '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78896?usp=email ) Change subject: soc/amd/genoa/devicetree: fix MMIO base addresses ...................................................................... soc/amd/genoa/devicetree: fix MMIO base addresses The base addresses of I2C 5 and I3C 3 were wrong and all I3C controllers should use the base address of the 4kiB block where all registers of that I3C controller are located in. PPR #55901 Rev 0.26 was used as a reference. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I1c983d4a709000ef7963b96228322603b98728aa --- M src/soc/amd/genoa/chipset.cb 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/78896/1 diff --git a/src/soc/amd/genoa/chipset.cb b/src/soc/amd/genoa/chipset.cb index 45eeec7..8b7d39e 100644 --- a/src/soc/amd/genoa/chipset.cb +++ b/src/soc/amd/genoa/chipset.cb @@ -213,13 +213,13 @@ device mmio 0xfedc4000 alias i2c_2 off end device mmio 0xfedc5000 alias i2c_3 off end device mmio 0xfedc6000 alias i2c_4 off end - device mmio 0xfedc7000 alias i2c_5 off end + device mmio 0xfedcb000 alias i2c_5 off end device mmio 0xfedc9000 alias uart_0 off end device mmio 0xfedca000 alias uart_1 off end device mmio 0xfedce000 alias uart_2 off end - device mmio 0xfedd2600 alias i3c_0 off end - device mmio 0xfedd3600 alias i3c_1 off end - device mmio 0xfedd4600 alias i3c_2 off end - device mmio 0xfedd5600 alias i3c_3 off end + device mmio 0xfedd2000 alias i3c_0 off end + device mmio 0xfedd3000 alias i3c_1 off end + device mmio 0xfedd4000 alias i3c_2 off end + device mmio 0xfedd6000 alias i3c_3 off end end -- To view, visit https://review.coreboot.org/c/coreboot/+/78896?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c983d4a709000ef7963b96228322603b98728aa Gerrit-Change-Number: 78896 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/alderlake: Add missing min sleep state for DPTF device
by Felix Held (Code Review) 04 Nov '23

04 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78877?usp=email ) Change subject: soc/intel/alderlake: Add missing min sleep state for DPTF device ...................................................................... soc/intel/alderlake: Add missing min sleep state for DPTF device Add an entry in the min_pci_sleep_states array for SA_DEVFN_DPTF, to correct warning in cbmem log: [WARN] unknown min d_state for PCI device 00:04.0 TEST=build/boot google/brya (banshee), verify warning not present in cbmem log, verify entry for DPTF device in ACPI LPI constraint list. Change-Id: I2a9976b065f08e4acd31c3deca13c5278f031a90 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78877 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/soc/intel/alderlake/acpi.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 1dc14be7..7687f02 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -166,6 +166,7 @@ { SA_DEVFN_ROOT, ACPI_DEVICE_SLEEP_D3 }, { SA_DEVFN_CPU_PCIE1_0, ACPI_DEVICE_SLEEP_D3 }, { SA_DEVFN_IGD, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_DPTF, ACPI_DEVICE_SLEEP_D3 }, { SA_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 }, { SA_DEVFN_CPU_PCIE6_0, ACPI_DEVICE_SLEEP_D3 }, { SA_DEVFN_CPU_PCIE6_2, ACPI_DEVICE_SLEEP_D3 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/78877?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2a9976b065f08e4acd31c3deca13c5278f031a90 Gerrit-Change-Number: 78877 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum
by Bill XIE (Code Review) 04 Nov '23

04 Nov '23

Attention is currently required from: Jonathon Hall, Jérémy Compostella, Nico Huber. Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78906?usp=email ) Change subject: drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum ...................................................................... Patch Set 8: (1 comment) Patchset: PS4: > Thanks for the context Nico, good to be aware of that. […] Okay, restored to patchset #5. -- To view, visit https://review.coreboot.org/c/coreboot/+/78906?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a Gerrit-Change-Number: 78906 Gerrit-PatchSet: 8 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Comment-Date: Sat, 04 Nov 2023 03:06:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum
by Bill XIE (Code Review) 04 Nov '23

04 Nov '23

Attention is currently required from: Bill XIE, Jérémy Compostella, Nico Huber. Hello Jonathon Hall, Jérémy Compostella, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78906?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum ...................................................................... drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum Proposed in the comment of commit 29030d0f3dad ("drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume"), during sanitize_cmos(), only reset CMOS range covered by checksum and the checksum itself from the file cmos.default in CBFS, in order to prevent other runtime data in CMOS (e.g. the DRAM training data on GM45 platforms for s3 resume) being erased. Tested: cherry-pick this commit before commit 44a48ce7a46c ("Kconfig: Bring HEAP_SIZE to a common, large value"), which is already before my commit 29030d0f3dad , Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from s3 again, indicating that DRAM training data are no longer erased. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Co-authored-by: Jonathon Hall <jonathon.hall(a)puri.sm> Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a --- M src/drivers/pc80/rtc/option.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/78906/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/78906?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a Gerrit-Change-Number: 78906 Gerrit-PatchSet: 8 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: arch/arm64/arch_timer: Fix possible overflow in multiplication
by Yu-Ping Wu (Code Review) 04 Nov '23

04 Nov '23

Attention is currently required from: Arthur Heymans, Julius Werner, Paul Menzel, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78800?usp=email ) Change subject: arch/arm64/arch_timer: Fix possible overflow in multiplication ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78800?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I366667de05392913150414f0fa9058725be71c52 Gerrit-Change-Number: 78800 Gerrit-PatchSet: 8 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sat, 04 Nov 2023 02:05:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/qualcomm/sc7280: Enlarge BOOTBLOCK to 44K
by Yu-Ping Wu (Code Review) 04 Nov '23

04 Nov '23

Attention is currently required from: Julius Werner, Shelley Chen, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78893?usp=email ) Change subject: soc/qualcomm/sc7280: Enlarge BOOTBLOCK to 44K ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78893?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae9d44939b29098e823508dd3965a1bae7a69041 Gerrit-Change-Number: 78893 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sat, 04 Nov 2023 02:05:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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