coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

1 participants
3037 discussions

[M] Change in coreboot[main]: Use common GCD function
by Martin L Roth (Code Review) 04 Nov '23

04 Nov '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78799?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: Use common GCD function ...................................................................... Use common GCD function Change-Id: I30e4b02a9ca6a15c9bc4edcf4143ffa13a21a732 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78799 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/drivers/analogix/anx7625/anx7625.c M src/northbridge/intel/ironlake/quickpath.c M src/soc/rockchip/rk3288/clock.c M src/soc/rockchip/rk3399/clock.c 4 files changed, 18 insertions(+), 69 deletions(-) Approvals: Julius Werner: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index e3a5111..8726ac0 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <commonlib/bsd/gcd.h> #include <delay.h> #include <device/i2c_simple.h> #include <edid.h> @@ -152,30 +153,14 @@ return 0; } -static unsigned long gcd(unsigned long a, unsigned long b) -{ - if (a == 0) - return b; - - while (b != 0) { - if (a > b) - a = a - b; - else - b = b - a; - } - - return a; -} - /* Reduce fraction a/b */ -static void anx7625_reduction_of_a_fraction(unsigned long *_a, - unsigned long *_b) +static void anx7625_reduction_of_a_fraction(u32 *_a, u32 *_b) { - unsigned long gcd_num; - unsigned long a = *_a, b = *_b, old_a, old_b; + u32 gcd_num; + u32 a = *_a, b = *_b, old_a, old_b; u32 denom = 1; - gcd_num = gcd(a, b); + gcd_num = gcd32(a, b); a /= gcd_num; b /= gcd_num; @@ -198,9 +183,7 @@ *_b = b; } -static int anx7625_calculate_m_n(u32 pixelclock, - unsigned long *m, unsigned long *n, - uint8_t *pd) +static int anx7625_calculate_m_n(u32 pixelclock, u32 *m, u32 *n, uint8_t *pd) { uint8_t post_divider = *pd; if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { @@ -300,7 +283,7 @@ static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt) { - unsigned long m, n; + u32 m, n; u16 htotal; int ret; uint8_t post_divider = 0; @@ -311,7 +294,7 @@ return -1; } - ANXINFO("compute M(%lu), N(%lu), divider(%d).\n", m, n, post_divider); + ANXINFO("compute M(%u), N(%u), divider(%d).\n", m, n, post_divider); /* configure pixel clock */ ret = anx7625_reg_write(bus, RX_P0_ADDR, PIXEL_CLOCK_L, diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c index 8a0e01c..eb79347 100644 --- a/src/northbridge/intel/ironlake/quickpath.c +++ b/src/northbridge/intel/ironlake/quickpath.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <commonlib/bsd/gcd.h> #include <console/console.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <cpu/x86/msr.h> @@ -11,31 +12,14 @@ #define NORTHBRIDGE PCI_DEV(0, 0, 0) -static unsigned int gcd(unsigned int a, unsigned int b) -{ - unsigned int t; - if (a > b) { - t = a; - a = b; - b = t; - } - /* invariant a < b. */ - while (a) { - t = b % a; - b = a; - a = t; - } - return b; -} - static inline int div_roundup(int a, int b) { return DIV_ROUND_UP(a, b); } -static unsigned int lcm(unsigned int a, unsigned int b) +static u32 lcm(u32 a, u32 b) { - return (a * b) / gcd(a, b); + return (a * b) / gcd32(a, b); } struct stru1 { @@ -65,7 +49,7 @@ int freq_max_reduced; int freq3, freq4; - g = gcd(freq1, freq2); + g = gcd32(freq1, freq2); freq1_reduced = freq1 / g; freq2_reduced = freq2 / g; freq_min_reduced = MIN(freq1_reduced, freq2_reduced); diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index c2f93f5..d52fa2a 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <device/mmio.h> #include <assert.h> +#include <commonlib/bsd/gcd.h> #include <console/console.h> #include <delay.h> +#include <device/mmio.h> #include <lib.h> #include <soc/addressmap.h> #include <soc/clock.h> @@ -438,16 +439,6 @@ } } -static u32 clk_gcd(u32 a, u32 b) -{ - while (b != 0) { - int r = b; - b = a % b; - a = r; - } - return a; -} - void rkclk_configure_i2s(unsigned int hz) { int n, d; @@ -462,7 +453,7 @@ 1 << 15 | 0 << 12 | 1 << 8 | 0 << 0)); /* set frac divider */ - v = clk_gcd(GPLL_HZ, hz); + v = gcd32(GPLL_HZ, hz); n = (GPLL_HZ / v) & (0xffff); d = (hz / v) & (0xffff); assert(hz == GPLL_HZ / n * d); diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 75af695b..fbff5a7 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> +#include <commonlib/bsd/gcd.h> #include <console/console.h> -#include <device/mmio.h> #include <delay.h> +#include <device/mmio.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/grf.h> @@ -776,16 +777,6 @@ return freq; } -static u32 clk_gcd(u32 a, u32 b) -{ - while (b != 0) { - int r = b; - b = a % b; - a = r; - } - return a; -} - void rkclk_configure_i2s(unsigned int hz) { int n, d; @@ -805,7 +796,7 @@ RK_CLRBITS(1 << 12 | 1 << 5 | 1 << 4 | 1 << 3)); /* set frac divider */ - v = clk_gcd(CPLL_HZ, hz); + v = gcd32(CPLL_HZ, hz); n = (CPLL_HZ / v) & (0xffff); d = (hz / v) & (0xffff); assert(hz == (u64)CPLL_HZ * d / n); -- To view, visit https://review.coreboot.org/c/coreboot/+/78799?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30e4b02a9ca6a15c9bc4edcf4143ffa13a21a732 Gerrit-Change-Number: 78799 Gerrit-PatchSet: 8 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[main]: commonlib: Add GCD function
by Martin L Roth (Code Review) 04 Nov '23

04 Nov '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78798?usp=email ) Change subject: commonlib: Add GCD function ...................................................................... commonlib: Add GCD function Implement a simple GCD function. BUG=b:307790895 TEST=emerge-geralt coreboot TEST=make tests/commonlib/bsd/gcd-test Change-Id: I21819cda4299b3809b8ca7a95cbdc6a87e4b3481 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78798 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/Makefile.inc A src/commonlib/bsd/gcd.c A src/commonlib/bsd/include/commonlib/bsd/gcd.h M tests/commonlib/bsd/Makefile.inc A tests/commonlib/bsd/gcd-test.c 5 files changed, 67 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Martin L Roth: Looks good to me, approved diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 86e8c56..70e731d 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -58,3 +58,6 @@ romstage-y += bsd/elog.c ramstage-y += bsd/elog.c smm-y += bsd/elog.c + +decompressor-y += bsd/gcd.c +all-y += bsd/gcd.c diff --git a/src/commonlib/bsd/gcd.c b/src/commonlib/bsd/gcd.c new file mode 100644 index 0000000..92b601e --- /dev/null +++ b/src/commonlib/bsd/gcd.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#include <commonlib/bsd/gcd.h> +#include <commonlib/bsd/helpers.h> +#include <stdint.h> + +uint32_t gcd32(uint32_t a, uint32_t b) +{ + uint32_t c; + + if (a == 0 || b == 0) + return MAX(a, b); + + c = a % b; + + while (c > 0) { + a = b; + b = c; + c = a % b; + } + + return b; +} diff --git a/src/commonlib/bsd/include/commonlib/bsd/gcd.h b/src/commonlib/bsd/include/commonlib/bsd/gcd.h new file mode 100644 index 0000000..20949de --- /dev/null +++ b/src/commonlib/bsd/include/commonlib/bsd/gcd.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _COMMONLIB_BSD_GCD_H_ +#define _COMMONLIB_BSD_GCD_H_ + +#include <stdint.h> + +uint32_t gcd32(uint32_t a, uint32_t b); + +#endif /* _COMMONLIB_BSD_GCD_H_ */ diff --git a/tests/commonlib/bsd/Makefile.inc b/tests/commonlib/bsd/Makefile.inc index 56664d0..bf17b6d 100644 --- a/tests/commonlib/bsd/Makefile.inc +++ b/tests/commonlib/bsd/Makefile.inc @@ -1,5 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only tests-y += helpers-test +tests-y += gcd-test helpers-test-srcs += tests/commonlib/bsd/helpers-test.c + +gcd-test-srcs += tests/commonlib/bsd/gcd-test.c +gcd-test-srcs += src/commonlib/bsd/gcd.c diff --git a/tests/commonlib/bsd/gcd-test.c b/tests/commonlib/bsd/gcd-test.c new file mode 100644 index 0000000..13fad86 --- /dev/null +++ b/tests/commonlib/bsd/gcd-test.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <commonlib/bsd/gcd.h> +#include <tests/test.h> + +static void test_gcd32(void **state) +{ + assert_int_equal(gcd32(17, 11), 1); + assert_int_equal(gcd32(64, 36), 4); + assert_int_equal(gcd32(90, 123), 3); + assert_int_equal(gcd32(65536, 339584), 128); + assert_int_equal(gcd32(1, 1), 1); + assert_int_equal(gcd32(1, 123), 1); + assert_int_equal(gcd32(123, 1), 1); + assert_int_equal(gcd32(1, UINT32_MAX), 1); + assert_int_equal(gcd32(UINT32_MAX, 1), 1); + assert_int_equal(gcd32(UINT32_MAX, UINT32_MAX), UINT32_MAX); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_gcd32), + }; + + return cb_run_group_tests(tests, NULL, NULL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/78798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I21819cda4299b3809b8ca7a95cbdc6a87e4b3481 Gerrit-Change-Number: 78798 Gerrit-PatchSet: 7 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[main]: commonlib: Add GCD function
by Martin L Roth (Code Review) 04 Nov '23

04 Nov '23

Attention is currently required from: Arthur Heymans, Paul Menzel, Yidi Lin. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78798?usp=email ) Change subject: commonlib: Add GCD function ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I21819cda4299b3809b8ca7a95cbdc6a87e4b3481 Gerrit-Change-Number: 78798 Gerrit-PatchSet: 6 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sat, 04 Nov 2023 17:05:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/brya/var/marasov: Enable Wi-Fi sar table for Intel module
by Martin L Roth (Code Review) 04 Nov '23

04 Nov '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77789?usp=email ) Change subject: mb/google/brya/var/marasov: Enable Wi-Fi sar table for Intel module ...................................................................... mb/google/brya/var/marasov: Enable Wi-Fi sar table for Intel module 1.In contrast to the MediaTek Wi-Fi module, the Intel Wi-Fi module needs to load a SAR table. 2.Describe the FW_CONFIG probe for the settings on marasov. - WIFI_SAR_ID_0 for MTK Wi-Fi module MT7921L - WIFI_SAR_ID_1 for Intel Wi-Fi module AX211NGW BUG=b:300045956 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Change-Id: I5b5c6bea6c2c916fb682044218ec7b3a5d2659f6 Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77789 Reviewed-by: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/marasov/overridetree.cb M src/mainboard/google/brya/variants/marasov/variant.c 3 files changed, 19 insertions(+), 0 deletions(-) Approvals: Daniel Peng: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 683f917..b06d772 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -269,6 +269,7 @@ config BOARD_GOOGLE_MARASOV select BOARD_GOOGLE_BASEBOARD_BRYA + select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_INTEL_ISH select SOC_INTEL_RAPTORLAKE select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index 311971f..a8c1c06 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -16,6 +16,10 @@ option TOUCH_NONE 0 option TOUCH_ELAN0001 1 end + field WIFI_SAR_ID 6 7 + option WIFI_SAR_ID_0 0 + option WIFI_SAR_ID_1 1 + end field STORAGE 30 31 option STORAGE_UNKNOWN 0 option STORAGE_NVME 1 diff --git a/src/mainboard/google/brya/variants/marasov/variant.c b/src/mainboard/google/brya/variants/marasov/variant.c index dad8a3c..5f3894d 100644 --- a/src/mainboard/google/brya/variants/marasov/variant.c +++ b/src/mainboard/google/brya/variants/marasov/variant.c @@ -2,8 +2,22 @@ #include <acpi/acpigen.h> #include <baseboard/variants.h> +#include <console/console.h> +#include <fw_config.h> +#include <sar.h> #include <variant/gpio.h> +const char *get_wifi_sar_cbfs_filename(void) +{ + if (fw_config_probe(FW_CONFIG(WIFI_SAR_ID, WIFI_SAR_ID_1))) { + printk(BIOS_INFO, "Use wifi_sar_1.hex for Intel Wi-Fi module AX211NGW.\n"); + return "wifi_sar_1.hex"; + } + + printk(BIOS_INFO, "Intel Wi-Fi SAR not used, return NULL!\n"); + return NULL; +} + void variant_generate_s0ix_hook(enum s0ix_entry entry) { /* Add board-specific MS0X entries */ -- To view, visit https://review.coreboot.org/c/coreboot/+/77789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5b5c6bea6c2c916fb682044218ec7b3a5d2659f6 Gerrit-Change-Number: 77789 Gerrit-PatchSet: 8 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: soc/intel/meteorlake: Consolidate settings for enabling tracehub
by Martin L Roth (Code Review) 04 Nov '23

04 Nov '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78648?usp=email ) Change subject: soc/intel/meteorlake: Consolidate settings for enabling tracehub ...................................................................... soc/intel/meteorlake: Consolidate settings for enabling tracehub To get tracehub working, it requires few settings such as SOC_INTEL_METEORLAKE_DEBUG_CONSENT=2 and enable tracehub device in dev tree. This commit binds all tracehub related settings to Kconfig, so that users only need to enable SOC_INTEL_COMMON_BLOCK_TRACEHUB TEST=boot on screebo and test tracehub device exists and working Change-Id: Ie830fe2fd38e3456497bea37fe42ca60d26ca305 Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78648 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/chip.c 2 files changed, 16 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 05d7f70..a2f2706 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -353,6 +353,7 @@ # USB DBC is more common for developers so make this default to 6 if # SOC_INTEL_DEBUG_CONSENT=y default 6 if SOC_INTEL_DEBUG_CONSENT + default 2 if SOC_INTEL_COMMON_BLOCK_TRACEHUB default 0 help This is to control debug interface on SOC. diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index a1b1968..be957cc 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -151,6 +151,18 @@ gpio_pm_configure(value, TOTAL_GPIO_COMM); } +/* Enable tracehub in device tree */ +static void soc_enable_tracehub(void) +{ + struct device *dev; + + dev = pcidev_path_on_root(PCI_DEVFN_NPK); + if (dev) { + dev->enabled = 1; + printk(BIOS_DEBUG, "Tracehub is enabled.\n"); + } +} + void soc_init_pre_device(void *chip_info) { config_t *config = config_of_soc(); @@ -159,6 +171,9 @@ config->tbt_authentication = ioe_p2sb_sbi_read(PID_IOM, IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION; + if (CONFIG(SOC_INTEL_COMMON_BLOCK_TRACEHUB)) + soc_enable_tracehub(); + /* Perform silicon specific init. */ fsp_silicon_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/78648?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie830fe2fd38e3456497bea37fe42ca60d26ca305 Gerrit-Change-Number: 78648 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: soc/amd/genoa/devicetree: fix MMIO base addresses
by Matt DeVillier (Code Review) 04 Nov '23

04 Nov '23

Attention is currently required from: Felix Held, Martin L Roth, Varshit Pandya. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78896?usp=email ) Change subject: soc/amd/genoa/devicetree: fix MMIO base addresses ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/soc/amd/genoa/chipset.cb: https://review.coreboot.org/c/coreboot/+/78896/comment/e2610812_6962d860 : PS1, Line 216: device mmio 0xfedcb000 alias i2c_5 off end reorder based on new address? -- To view, visit https://review.coreboot.org/c/coreboot/+/78896?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c983d4a709000ef7963b96228322603b98728aa Gerrit-Change-Number: 78896 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 04 Nov 2023 14:10:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum
by Nico Huber (Code Review) 04 Nov '23

04 Nov '23

Attention is currently required from: Bill XIE, Jonathon Hall, Jérémy Compostella. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78906?usp=email ) Change subject: drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78906?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a Gerrit-Change-Number: 78906 Gerrit-PatchSet: 8 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Comment-Date: Sat, 04 Nov 2023 12:17:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: soc/amd/genoa: Add mmio.asl
by Felix Held (Code Review) 04 Nov '23

04 Nov '23

Attention is currently required from: Arthur Heymans, Varshit Pandya. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78895?usp=email ) Change subject: soc/amd/genoa: Add mmio.asl ...................................................................... Patch Set 1: (3 comments) File src/soc/amd/genoa/acpi/mmio.asl: https://review.coreboot.org/c/coreboot/+/78895/comment/09c52404_3adcf9c6 : PS1, Line 199: would be good to have the i2c status reporting code added here too. CB:78900 adds the devicetree ops for that to work; since the acpi table generation isn't enabled yet, the order in this gets added shouldn't really matter though https://review.coreboot.org/c/coreboot/+/78895/comment/abc1fb94_857dae6f : PS1, Line 322: there are two more i2c devices. CB:78897 adds the missing base address definitions. since we don't have i3c support, i;d say that we shouldn't report the i3c devices in here for now https://review.coreboot.org/c/coreboot/+/78895/comment/2867e600_351763b2 : PS1, Line 340: 0x0F this should return 0x0b to hide the device in the windows device manager. see CB:68962 -- To view, visit https://review.coreboot.org/c/coreboot/+/78895?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5bc2cc0141e9da7e2c6ed7691188d7c94b6b1e3 Gerrit-Change-Number: 78895 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 04 Nov 2023 05:22:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: soc/amd/genoa/chipset.dt: add UART device ops
by Felix Held (Code Review) 04 Nov '23

04 Nov '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78901?usp=email ) Change subject: soc/amd/genoa/chipset.dt: add UART device ops ...................................................................... soc/amd/genoa/chipset.dt: add UART device ops Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9fc155fe76c05fefd4ce31ae6b96dcc4527b6abc --- M src/soc/amd/genoa/chipset.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/78901/1 diff --git a/src/soc/amd/genoa/chipset.cb b/src/soc/amd/genoa/chipset.cb index 8b7d39e..e2d0e2e 100644 --- a/src/soc/amd/genoa/chipset.cb +++ b/src/soc/amd/genoa/chipset.cb @@ -214,9 +214,9 @@ device mmio 0xfedc5000 alias i2c_3 off end device mmio 0xfedc6000 alias i2c_4 off end device mmio 0xfedcb000 alias i2c_5 off end - device mmio 0xfedc9000 alias uart_0 off end - device mmio 0xfedca000 alias uart_1 off end - device mmio 0xfedce000 alias uart_2 off end + device mmio 0xfedc9000 alias uart_0 off ops amd_uart_mmio_ops end + device mmio 0xfedca000 alias uart_1 off ops amd_uart_mmio_ops end + device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedd2000 alias i3c_0 off end device mmio 0xfedd3000 alias i3c_1 off end device mmio 0xfedd4000 alias i3c_2 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/78901?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9fc155fe76c05fefd4ce31ae6b96dcc4527b6abc Gerrit-Change-Number: 78901 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: mb/google/corsola: Enable FW_CONFIG and FW_CONFIG_SOURCE_CHROMEEC_CBI
by Felix Held (Code Review) 04 Nov '23

04 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78905?usp=email ) Change subject: mb/google/corsola: Enable FW_CONFIG and FW_CONFIG_SOURCE_CHROMEEC_CBI ...................................................................... mb/google/corsola: Enable FW_CONFIG and FW_CONFIG_SOURCE_CHROMEEC_CBI Enable FW_CONFIG for corsola so that the information can be passed to payloads via coreboot tables. BUG=b:157692450 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I6c12041d3666907c884f5a50a12c1433c2085961 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78905 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/corsola/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index c082e6f..805a83a 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -22,6 +22,8 @@ select MAINBOARD_HAS_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER select RTC + select FW_CONFIG + select FW_CONFIG_SOURCE_CHROMEEC_CBI config BOARD_GOOGLE_KINGLER_COMMON def_bool n -- To view, visit https://review.coreboot.org/c/coreboot/+/78905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c12041d3666907c884f5a50a12c1433c2085961 Gerrit-Change-Number: 78905 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2023