coreboot-gerrit November 2023

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[M] Change in coreboot[main]: vendorcode/amd: Hook up opensil
by Varshit Pandya (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Arthur Heymans, Martin L Roth, Martin Roth. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76511?usp=email ) Change subject: vendorcode/amd: Hook up opensil ...................................................................... Patch Set 13: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/76511?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide2d181914116119dfd37b1511d89ea965729141 Gerrit-Change-Number: 76511 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 03:44:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/emulation/qemu-sbsa: Generate PPTT ACPI table
by David Milosevic (Code Review) 17 Nov '23

17 Nov '23

David Milosevic has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79108?usp=email ) Change subject: mb/emulation/qemu-sbsa: Generate PPTT ACPI table ...................................................................... mb/emulation/qemu-sbsa: Generate PPTT ACPI table In order to be compliant to the LBBR spec, we need to generate and export a Processor Properties Topology Table. Change-Id: Iabeb138c1257488bcb364fe7b522f02c041745e2 Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> --- M src/mainboard/emulation/qemu-sbsa/Kconfig M src/mainboard/emulation/qemu-sbsa/Makefile.inc A src/mainboard/emulation/qemu-sbsa/pptt.c 3 files changed, 149 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/79108/1 diff --git a/src/mainboard/emulation/qemu-sbsa/Kconfig b/src/mainboard/emulation/qemu-sbsa/Kconfig index 8719d00..53d44f0 100644 --- a/src/mainboard/emulation/qemu-sbsa/Kconfig +++ b/src/mainboard/emulation/qemu-sbsa/Kconfig @@ -22,6 +22,7 @@ select HAVE_ACPI_TABLES select ACPI_GTDT select ACPI_COMMON_MADT_GICC_V3 + select ACPI_PPTT select GENERATE_SMBIOS_TABLES config ARM64_CURRENT_EL diff --git a/src/mainboard/emulation/qemu-sbsa/Makefile.inc b/src/mainboard/emulation/qemu-sbsa/Makefile.inc index e3855ba..515f497 100644 --- a/src/mainboard/emulation/qemu-sbsa/Makefile.inc +++ b/src/mainboard/emulation/qemu-sbsa/Makefile.inc @@ -13,6 +13,7 @@ ramstage-y += mmio.c ramstage-y += acpi.c +ramstage-y += pptt.c bootblock-y += bootblock_custom.S diff --git a/src/mainboard/emulation/qemu-sbsa/pptt.c b/src/mainboard/emulation/qemu-sbsa/pptt.c new file mode 100644 index 0000000..ac0172f --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/pptt.c @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdlib.h> +#include <cpu/cpu.h> +#include <arch/cache.h> +#include <acpi/acpi.h> +#include <console/console.h> + +#define CACHE_NODE_FLAGS 0xd7 // everything valid except, write-policy and allocation type +#define CLUSTER_FLAGS 0x11 // physical package, ID invalid, no thread, no leaf, identical impl. +#define CORE_FLAGS 0x1a // no physical package, ID valid, no thread, leaf, identical impl. + +/* + * L2 cache (LLC) + */ +struct pptt_cache l2 = { + + .next_level = NULL +}; + +/* + * L1I cache + */ +struct pptt_cache l1i = { + + .next_level = &l2 +}; + +/* + * L1D cache + */ +struct pptt_cache l1d = { + + .next_level = &l2 +}; + +/* + * private resources of a cpu core. Same for + * each core, thus we can reuse this struture + * instead of creating it dynamically. + */ +struct pptt_cpu_resources core_resources = { + + .cache = &l1i, + + .next = &(struct pptt_cpu_resources) { + + .cache = &l1d, + .next = NULL + } +}; + +struct pptt_topology root_topology = { + + .flags.raw = CLUSTER_FLAGS, + .resources = NULL, + .sibling = NULL, + .child = NULL // updated in runtime +}; + +/* --- Helpers --- */ + +static u8 cache_attributes(const enum cache_type type) +{ + /* + * 'write-policy' and 'allocation type' currently + * unsupported. cache flags set accordingly. + * + * maybe a todo for the future. + */ + + u8 attr = 0x0; + + if (type == CACHE_INSTRUCTION) + attr |= (0x1 << 2); + else if(type == CACHE_UNIFIED) + attr |= (0x1 << 3); + + return attr; +} + +/* --- ACPI hook --- */ + +struct pptt_topology* acpi_get_pptt_topology(void) +{ + struct cache_info info; + + /* update cache information (L1I) */ + + cpu_get_cache_info(CACHE_L1, CACHE_INSTRUCTION, &info); + + l1i.size = info.size; + l1i.associativity = info.associativity; + l1i.numsets = info.numsets; + l1i.line_size = info.line_bytes; + l1i.attributes = cache_attributes(CACHE_INSTRUCTION); + l1i.flags.raw = CACHE_NODE_FLAGS; + + /* update cache information (L1D) */ + + cpu_get_cache_info(CACHE_L1, CACHE_DATA, &info); + + l1d.size = info.size; + l1d.associativity = info.associativity; + l1d.numsets = info.numsets; + l1d.line_size = info.line_bytes; + l1d.attributes = cache_attributes(CACHE_DATA); + l1d.flags.raw = CACHE_NODE_FLAGS; + + /* update cache information (L2) */ + + cpu_get_cache_info(CACHE_L2, CACHE_UNIFIED, &info); + + l2.size = info.size; + l2.associativity = info.associativity; + l2.numsets = info.numsets; + l2.line_size = info.line_bytes; + l2.attributes = cache_attributes(CACHE_UNIFIED); + l2.flags.raw = CACHE_NODE_FLAGS; + + /* add secondary CPUs */ + + u32 cpu_id = 0; + + struct device *dev = NULL; + struct pptt_topology **it = &root_topology.child; + + while ((dev = dev_find_path(dev, DEVICE_PATH_GICC_V3))) { + + if ((*it = malloc(sizeof(struct pptt_topology))) == NULL) { + + printk(BIOS_ERR, "Could not allocate pptt structure!\n"); + break; + } + + memset(*it, 0, sizeof(struct pptt_topology)); + + (*it)->processor_id = cpu_id; + (*it)->flags.raw = CORE_FLAGS; + (*it)->resources = &core_resources; + + it = &(*it)->sibling; + cpu_id += 1; + } + + return &root_topology; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79108?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabeb138c1257488bcb364fe7b522f02c041745e2 Gerrit-Change-Number: 79108 Gerrit-PatchSet: 1 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: arch/arm64: Implement initial set of SMBIOS tables
by Benjamin Doron (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: David Milosevic, Julius Werner, Lean Sheng Tan, Martin L Roth, Maximilian Brune. Hello David Milosevic, Julius Werner, Lean Sheng Tan, Maximilian Brune, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78285?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/arm64: Implement initial set of SMBIOS tables ...................................................................... arch/arm64: Implement initial set of SMBIOS tables Implement the two architectural tables: processor and cache. Note that SoC/board code should override core-thread count and, for spec-compliance, create CBMEM_ID_MEMINFO. Need to confirm tables are in fact compliant. Change-Id: Iedae0f26f168bd6d3af866e35d9d39ddb01abc15 Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M src/Kconfig A src/arch/arm64/smbios.c M src/arch/arm64/tables.c M src/include/smbios.h 4 files changed, 233 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/78285/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/78285?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iedae0f26f168bd6d3af866e35d9d39ddb01abc15 Gerrit-Change-Number: 78285 Gerrit-PatchSet: 7 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: google/*: Clean up Kconfg board selection for Google MTK boards
by Yu-Ping Wu (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Felix Singer, Hung-Te Lin, Julius Werner, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79063?usp=email ) Change subject: google/*: Clean up Kconfg board selection for Google MTK boards ...................................................................... Patch Set 1: (5 comments) File src/mainboard/google/corsola/Kconfig: https://review.coreboot.org/c/coreboot/+/79063/comment/3e408669_a096bd24 : PS1, Line 22: select DRIVER_ANALOGIX_ANX7625 if BOARD_GOOGLE_CHINCHOU In the past we've changed the file multiple times in order to better organize these display driver Kconfigs. Note that only one driver should be selected, except on Steelix where old revisions use a different eDP bridge. The best option we have so far is to let each board select the right config, so that it's clear that only one of them is selected. Now if the preferred model is to hide `BOARD_GOOGLE_*` from the Kconfig file, I think we'll want to change how these drivers are selected. In particular, we'll need to make sure both options are mutually exclusive (except for Steelix). My suggestion would be: ``` config CORSOLA_HAS_MIPI_PANEL def_bool BOARD_GOOGLE_STARYU_COMMON config DRIVER_ANALOGIX_ANX7625 def_bool BOARD_GOOGLE_KINGLER_COMMON || BOARD_GOOGLE_CHINCHOU || ... depends on !CORSOLA_HAS_MIPI_PANEL config DRIVER_PARADE_PS8640 def_bool !DRIVER_ANALOGIX_ANX7625 || BOARD_GOOGLE_STEELIX depends on !CORSOLA_HAS_MIPI_PANEL ``` Do you think that's cleaner than the current patch? File src/mainboard/google/geralt/Kconfig: https://review.coreboot.org/c/coreboot/+/79063/comment/106057be_7b8ed6b8 : PS1, Line 5: def_bool BOARD_GOOGLE_GERALT And `BOARD_GOOGLE_CIRI` (added by a recent patch CB:78954). https://review.coreboot.org/c/coreboot/+/79063/comment/f7ca0d8f_08f54390 : PS1, Line 62: SDCARD_INIT Also modify this for consistency (need to rebase). File src/mainboard/google/kukui/Kconfig: https://review.coreboot.org/c/coreboot/+/79063/comment/213d8053_35485f20 : PS1, Line 27: BOARD_GOOGLE_WILLOW This needs to select `BOARD_GOOGLE_KUKUI_COMMON`. Here kukui is considered as the parent of jacuzzi. https://review.coreboot.org/c/coreboot/+/79063/comment/8228d956_63e9ae5f : PS1, Line 36: select VBOOT_VBNV_FLASH Not related to the patch, but I've always been wondering how repeated definitions of a Kconfig option work. Is this line equivalent to `select VBOOT_VBNV_FLASH if VBOOT` in `BOARD_SPECIFIC_OPTIONS`? -- To view, visit https://review.coreboot.org/c/coreboot/+/79063?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40880e7609ba703d0053ad01da742871e54d4e7a Gerrit-Change-Number: 79063 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 01:54:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: mb/emulation/qemu-sbsa: Add qemu-sbsa board
by David Milosevic (Code Review) 17 Nov '23

17 Nov '23

David Milosevic has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79107?usp=email ) Change subject: mb/emulation/qemu-sbsa: Add qemu-sbsa board ...................................................................... mb/emulation/qemu-sbsa: Add qemu-sbsa board Add coreboot support for qemu's sbsa-ref machine (-m sbsa-ref) Change-Id: I19fbaeed991fc6dbc6c001765a9b9571bf9297a4 Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> --- A Documentation/mainboard/emulation/qemu-sbsa.md M src/arch/arm64/monitor_services.c A src/mainboard/emulation/qemu-sbsa/Kconfig A src/mainboard/emulation/qemu-sbsa/Kconfig.name A src/mainboard/emulation/qemu-sbsa/Makefile.inc A src/mainboard/emulation/qemu-sbsa/acpi.c A src/mainboard/emulation/qemu-sbsa/board_info.txt A src/mainboard/emulation/qemu-sbsa/bootblock.c A src/mainboard/emulation/qemu-sbsa/bootblock_custom.S A src/mainboard/emulation/qemu-sbsa/cbmem.c A src/mainboard/emulation/qemu-sbsa/chip.h A src/mainboard/emulation/qemu-sbsa/devicetree.cb A src/mainboard/emulation/qemu-sbsa/dsdt.asl A src/mainboard/emulation/qemu-sbsa/flash.fmd A src/mainboard/emulation/qemu-sbsa/include/mainboard/addressmap.h A src/mainboard/emulation/qemu-sbsa/mainboard.c A src/mainboard/emulation/qemu-sbsa/media.c A src/mainboard/emulation/qemu-sbsa/memlayout.ld A src/mainboard/emulation/qemu-sbsa/mmio.c 19 files changed, 1,039 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/79107/1 diff --git a/Documentation/mainboard/emulation/qemu-sbsa.md b/Documentation/mainboard/emulation/qemu-sbsa.md new file mode 100644 index 0000000..ccaf58d --- /dev/null +++ b/Documentation/mainboard/emulation/qemu-sbsa.md @@ -0,0 +1,8 @@ +# QEMU SBSA emulator +This page describes how to build and run coreboot for QEMU's sbsa-ref machine. + +## Running coreboot in QEMU +```bash +qemu-system-aarch64 -nographic -m 1024 -M sbsa-ref -pflash <TF-A> \ + -pflash ./build/coreboot.rom \ +``` diff --git a/src/arch/arm64/monitor_services.c b/src/arch/arm64/monitor_services.c index 38b9db0..b3ebb32 100644 --- a/src/arch/arm64/monitor_services.c +++ b/src/arch/arm64/monitor_services.c @@ -15,7 +15,7 @@ memset(&ret_args, 0, sizeof(ret_args)); - if (current_el() == EL3) { + if (CONFIG(ARM64_CURRENT_EL) == EL3) { printk(BIOS_DEBUG, "coreboot executes in EL3, assuming no monitor present...\n"); return ret_args; } diff --git a/src/mainboard/emulation/qemu-sbsa/Kconfig b/src/mainboard/emulation/qemu-sbsa/Kconfig new file mode 100644 index 0000000..8719d00 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/Kconfig @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_EMULATION_QEMU_SBSA + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARM64_USE_ARCH_TIMER + select BOARD_ROMSIZE_KB_32768 + select BOOTBLOCK_CUSTOM + select BOOT_DEVICE_NOT_SPI_FLASH + select DRIVERS_UART_PL011 + select FLATTENED_DEVICE_TREE + select HAVE_LINEAR_FRAMEBUFFER + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MISSING_BOARD_RESET + select PCI + select HAVE_ACPI_TABLES + select ACPI_GTDT + select ACPI_COMMON_MADT_GICC_V3 + select GENERATE_SMBIOS_TABLES + +config ARM64_CURRENT_EL + default 2 + +config ECAM_MMCONF_BASE_ADDRESS + default 0xf0000000 + +config ECAM_MMCONF_BUS_NUMBER + default 256 + +config MEMLAYOUT_LD_FILE + string + default "src/mainboard/emulation/qemu-sbsa/memlayout.ld" + +config FATAL_ASSERTS + default y + +config FMDFILE + default "src/mainboard/emulation/qemu-sbsa/flash.fmd" + +config MAINBOARD_DIR + default "emulation/qemu-sbsa" + +config MAINBOARD_PART_NUMBER + default "QEMU sbsa" + +config MAX_CPUS + int + default 128 + +config MAINBOARD_VENDOR + string + default "QEMU" + +config DRAM_SIZE_MB + int + default 8388608 # The maximum dram size is 8192GiB. + +endif # BOARD_EMULATION_QEMU_SBSA diff --git a/src/mainboard/emulation/qemu-sbsa/Kconfig.name b/src/mainboard/emulation/qemu-sbsa/Kconfig.name new file mode 100644 index 0000000..d289d40 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/Kconfig.name @@ -0,0 +1,5 @@ +config BOARD_EMULATION_QEMU_SBSA + bool "QEMU sbsa" + help + To execute, do: + qemu-system-aarch64 -nographic -m 1024 -M sbsa-ref -pflash <TF-A> -pflash ./build/coreboot.rom diff --git a/src/mainboard/emulation/qemu-sbsa/Makefile.inc b/src/mainboard/emulation/qemu-sbsa/Makefile.inc new file mode 100644 index 0000000..e3855ba --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/Makefile.inc @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c + +romstage-y += cbmem.c + +bootblock-y += media.c +romstage-y += media.c +ramstage-y += media.c + +bootblock-y += mmio.c +romstage-y += mmio.c +ramstage-y += mmio.c + +ramstage-y += acpi.c + +bootblock-y += bootblock_custom.S + +CPPFLAGS_common += -mcmodel=large -I$(src)/mainboard/$(MAINBOARDDIR)/include + +build_complete:: + @printf "Truncating coreboot.rom to 256M\n" + truncate -s 256M $(obj)/coreboot.rom diff --git a/src/mainboard/emulation/qemu-sbsa/acpi.c b/src/mainboard/emulation/qemu-sbsa/acpi.c new file mode 100644 index 0000000..4cfb22a --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/acpi.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <mainboard/addressmap.h> + + +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->ARM_boot_arch |= ACPI_FADT_ARM_PSCI_COMPLIANT; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + return current; +} + +uintptr_t platform_get_gicd_base(void) +{ + return SBSA_GIC_DIST; +} + +uintptr_t platform_get_gicr_base(void) +{ + return SBSA_GIC_REDIST; +} + +#define SEC_EL1_TIMER_GISV 0x1d +#define NONSEC_EL1_TIMER_GSIV 0x1e +#define VIRTUAL_TIMER_GSIV 0x1b +#define NONSEC_EL2_TIMER_GSIV 0x1a + +#define SBSA_TIMER_FLAGS (ACPI_GTDT_INTERRUPT_POLARITY | ACPI_GTDT_ALWAYS_ON) + +void acpi_soc_fill_gtdt(acpi_gtdt_t *gtdt) +{ + /* his value is optional if the system implements EL3 (Security + Extensions). If not provided, this field must be 0xFFFFFFFFFFFFFFFF. */ + gtdt->counter_block_address = UINT64_MAX; + gtdt->secure_el1_interrupt = SEC_EL1_TIMER_GISV; + gtdt->secure_el1_flags = SBSA_TIMER_FLAGS; + gtdt->non_secure_el1_interrupt = NONSEC_EL1_TIMER_GSIV; + gtdt->non_secure_el1_flags = SBSA_TIMER_FLAGS; + gtdt->virtual_timer_interrupt = VIRTUAL_TIMER_GSIV; + gtdt->virtual_timer_flags = SBSA_TIMER_FLAGS; + gtdt->non_secure_el2_interrupt = NONSEC_EL2_TIMER_GSIV; + gtdt->non_secure_el2_flags = SBSA_TIMER_FLAGS; + /* his value is optional if the system implements EL3 + (Security Extensions). If not provided, this field must be + 0xFFFFFFFFFFFFFFF. */ + gtdt->counter_read_block_address = UINT64_MAX; +} + +#define WD_TIMER_GSIV 0x30 + +unsigned long acpi_soc_gtdt_add_timers(uint32_t *count, unsigned long current) +{ + (*count)++; + return acpi_gtdt_add_watchdog(current, SBSA_GWDT_REFRESH, SBSA_GWDT_CONTROL, + WD_TIMER_GSIV, 0); +} diff --git a/src/mainboard/emulation/qemu-sbsa/board_info.txt b/src/mainboard/emulation/qemu-sbsa/board_info.txt new file mode 100644 index 0000000..e4cd579 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/board_info.txt @@ -0,0 +1,3 @@ +Board name: QEMU sbsa +Category: emulation +Board URL: http://wiki.qemu.org/Main_Page diff --git a/src/mainboard/emulation/qemu-sbsa/bootblock.c b/src/mainboard/emulation/qemu-sbsa/bootblock.c new file mode 100644 index 0000000..473189e --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/bootblock.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/mmu.h> +#include <bootblock_common.h> +#include <symbols.h> + +void bootblock_mainboard_init(void) +{ + mmu_init(); + + /* Everything below DRAM is device memory */ + mmu_config_range((void *)0, (uintptr_t)_dram, MA_DEV | MA_RW); + /* Set a dummy value for DRAM. ramstage should update the mapping. */ + mmu_config_range(_dram, ((size_t) CONFIG_DRAM_SIZE_MB) * MiB, MA_MEM | MA_RW); + + mmu_config_range(_ttb, REGION_SIZE(ttb), MA_MEM | MA_S | MA_RW); + mmu_config_range(_bootblock, REGION_SIZE(bootblock), MA_MEM | MA_S | MA_RW); + mmu_config_range(_romstage, REGION_SIZE(romstage), MA_MEM | MA_S | MA_RW); + mmu_config_range(_ramstage, REGION_SIZE(ramstage), MA_MEM | MA_S | MA_RW); + mmu_config_range((void *)CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, + MA_DEV | MA_RW); + mmu_enable(); +} diff --git a/src/mainboard/emulation/qemu-sbsa/bootblock_custom.S b/src/mainboard/emulation/qemu-sbsa/bootblock_custom.S new file mode 100644 index 0000000..c05afed --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/bootblock_custom.S @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Early initialization code for sbsa-ref machine + */ + +#include <arch/asm.h> + +ENTRY(_start) + + /* TF-A arg which contains a pointer to fdt */ + ldr x1, =_fdt_pointer + str x0, [x1] + + /* Setup CPU. */ + /* bl arm64_init_cpu */ + + /* ==== stack init from arm64_init_cpu ==== */ + + msr SPSel, #0 /* use SP_EL0 */ + + ldr x2, =0xdeadbeefdeadbeef + ldr x0, =_stack + ldr x1, =_estack +1: + stp x2, x2, [x0], #16 + cmp x0, x1 + bne 1b + + sub sp, x0, #16 + + /* ==== END ==== */ + + /* Get code positions. */ + ldr x1, =_flash + ldr x0, =_bootblock + + /* Calculate bootblock size. */ + ldr x2, =_ebootblock + sub x2, x2, x0 + + /* Call memcpy in arch/arm64/memcpy.S */ + bl memcpy + dmb sy + + /* Calculate relocation offset between bootblock in flash and in DRAM. */ + ldr x0, =_flash + ldr x1, =_bootblock + sub x1, x1, x0 + + /* Jump to main() in DRAM. */ + adr x0, main + add x0, x0, x1 + blr x0 +ENDPROC(_start) diff --git a/src/mainboard/emulation/qemu-sbsa/cbmem.c b/src/mainboard/emulation/qemu-sbsa/cbmem.c new file mode 100644 index 0000000..389ff4e --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/cbmem.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cbmem.h> +#include <ramdetect.h> +#include <symbols.h> + +uintptr_t cbmem_top_chipset(void) +{ + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); +} diff --git a/src/mainboard/emulation/qemu-sbsa/chip.h b/src/mainboard/emulation/qemu-sbsa/chip.h new file mode 100644 index 0000000..98c6c71 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/chip.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EMULATION_QEMU_SBSA_CHIP_H +#define MAINBOARD_EMULATION_QEMU_SBSA_CHIP_H + +#include <types.h> + +struct mainboard_emulation_qemu_sbsa_config { + uint32_t vgic_maintenance_interrupt; + uint32_t performance_interrupt_gsiv; +}; + +#endif diff --git a/src/mainboard/emulation/qemu-sbsa/devicetree.cb b/src/mainboard/emulation/qemu-sbsa/devicetree.cb new file mode 100644 index 0000000..2e2cf3d --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/devicetree.cb @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip mainboard/emulation/qemu-sbsa + register "vgic_maintenance_interrupt" = "0x19" + register "performance_interrupt_gsiv" = "0x17" + + device cpu_cluster 0 on ops qemu_aarch64_cpu_ops end + + device domain 0 on ops qemu_aarch64_pci_domain_ops + device pci 00.0 on end + end +end diff --git a/src/mainboard/emulation/qemu-sbsa/dsdt.asl b/src/mainboard/emulation/qemu-sbsa/dsdt.asl new file mode 100644 index 0000000..e7d4251 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/dsdt.asl @@ -0,0 +1,487 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define LINK_DEVICE(Uid, LinkName, Irq) \ + Device (LinkName) { \ + Name (_HID, EISAID("PNP0C0F")) \ + Name (_UID, Uid) \ + Name (_PRS, ResourceTemplate() { \ + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { Irq } \ + }) \ + Method (_STA) { \ + Return (0xF) \ + } \ + Method (_CRS, 0) { Return (_PRS) } \ + Method (_SRS, 1) { } \ + Method (_DIS) { } \ + } + +#define PRT_ENTRY(Address, Pin, Link) \ + Package (4) { \ + Address, Pin, Link, Zero \ + } + +#include <acpi/acpi.h> +#include <mainboard/addressmap.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20230621 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + + Scope (_SB) { + // UART PL011 + Device (COM0) { + Name (_HID, "ARMH0011") + Name (_UID, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, SBSA_UART_BASE, 0x00001000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 33 } + }) + Method (_STA) { + Return (0xF) + } + } + + // AHCI Host Controller + Device (AHC0) { + Name (_HID, "LNRO001E") + Name (_CLS, Package (3) { + 0x01, + 0x06, + 0x01, + }) + Name (_CCA, 1) + Name (_CRS, ResourceTemplate() { + Memory32Fixed (ReadWrite, SBSA_AHCI_BASE, 0x00010000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 42 } + }) + Method (_STA) { + Return (0xF) + } + } + + // USB EHCI Host Controller + Device (USB0) { + Name (_HID, "LNRO0D20") + Name (_CID, "PNP0D20") + Method (_STA) { + Return (0xF) + } + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, SBSA_EHCI_BASE, 0x00010000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 43 } + }) + Return (RBUF) + } + + // Root Hub + Device (RHUB) { + Name (_ADR, 0x00000000) // Address of Root Hub should be 0 as per ACPI 5.0 spec + Method (_STA) { + Return (0xF) + } + + // Ports connected to Root Hub + Device (HUB1) { + Name (_ADR, 0x00000001) + Name (_UPC, Package() { + 0x00, // Port is NOT connectable + 0xFF, // Don't care + 0x00000000, // Reserved 0 must be zero + 0x00000000 // Reserved 1 must be zero + }) + Method (_STA) { + Return (0xF) + } + + Device (PRT1) { + Name (_ADR, 0x00000001) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name (_PLD, Package() { + Buffer(0x10) { + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + Method (_STA) { + Return (0xF) + } + } // USB0_RHUB_HUB1_PRT1 + Device (PRT2) { + Name (_ADR, 0x00000002) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name (_PLD, Package() { + Buffer(0x10) { + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + Method (_STA) { + Return (0xF) + } + } // USB0_RHUB_HUB1_PRT2 + + Device (PRT3) { + Name (_ADR, 0x00000003) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name (_PLD, Package() { + Buffer (0x10) { + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + Method (_STA) { + Return (0xF) + } + } // USB0_RHUB_HUB1_PRT3 + + Device (PRT4) { + Name (_ADR, 0x00000004) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name (_PLD, Package() { + Buffer (0x10){ + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + Method (_STA) { + Return (0xF) + } + } // USB0_RHUB_HUB1_PRT4 + } // USB0_RHUB_HUB1 + } // USB0_RHUB + } // USB0 + + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge + Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge + Name (_SEG, Zero) // PCI Segment Group number + Name (_BBN, Zero) // PCI Base Bus Number + Name (_UID, "PCI0") + Name (_CCA, One) // Initially mark the PCI coherent (for JunoR1) + + Method (_STA) { + Return (0xF) + } + + Method (_CBA, 0, NotSerialized) { + return (SBSA_PCIE_ECAM_BASE) + } + + LINK_DEVICE(0, GSI0, 0x23) + LINK_DEVICE(1, GSI1, 0x24) + LINK_DEVICE(2, GSI2, 0x25) + LINK_DEVICE(3, GSI3, 0x26) + + Name (_PRT, Package () // _PRT: PCI Routing Table + { + PRT_ENTRY(0x0000FFFF, 0, GSI0), + PRT_ENTRY(0x0000FFFF, 0, GSI1), + PRT_ENTRY(0x0000FFFF, 0, GSI2), + PRT_ENTRY(0x0000FFFF, 0, GSI3), + + PRT_ENTRY(0x0001FFFF, 0, GSI1), + PRT_ENTRY(0x0001FFFF, 1, GSI2), + PRT_ENTRY(0x0001FFFF, 2, GSI3), + PRT_ENTRY(0x0001FFFF, 3, GSI0), + + PRT_ENTRY(0x0002FFFF, 0, GSI2), + PRT_ENTRY(0x0002FFFF, 1, GSI3), + PRT_ENTRY(0x0002FFFF, 2, GSI0), + PRT_ENTRY(0x0002FFFF, 3, GSI1), + + PRT_ENTRY(0x0003FFFF, 0, GSI3), + PRT_ENTRY(0x0003FFFF, 1, GSI0), + PRT_ENTRY(0x0003FFFF, 2, GSI1), + PRT_ENTRY(0x0003FFFF, 3, GSI2), + + PRT_ENTRY(0x0004FFFF, 0, GSI0), + PRT_ENTRY(0x0004FFFF, 1, GSI1), + PRT_ENTRY(0x0004FFFF, 2, GSI2), + PRT_ENTRY(0x0004FFFF, 3, GSI3), + + PRT_ENTRY(0x0005FFFF, 0, GSI1), + PRT_ENTRY(0x0005FFFF, 1, GSI2), + PRT_ENTRY(0x0005FFFF, 2, GSI3), + PRT_ENTRY(0x0005FFFF, 3, GSI0), + + PRT_ENTRY(0x0006FFFF, 0, GSI2), + PRT_ENTRY(0x0006FFFF, 1, GSI3), + PRT_ENTRY(0x0006FFFF, 2, GSI0), + PRT_ENTRY(0x0006FFFF, 3, GSI1), + + PRT_ENTRY(0x0007FFFF, 0, GSI3), + PRT_ENTRY(0x0007FFFF, 1, GSI0), + PRT_ENTRY(0x0007FFFF, 2, GSI1), + PRT_ENTRY(0x0007FFFF, 3, GSI2), + + PRT_ENTRY(0x0008FFFF, 0, GSI0), + PRT_ENTRY(0x0008FFFF, 1, GSI1), + PRT_ENTRY(0x0008FFFF, 2, GSI2), + PRT_ENTRY(0x0008FFFF, 3, GSI3), + + PRT_ENTRY(0x0009FFFF, 0, GSI1), + PRT_ENTRY(0x0009FFFF, 1, GSI2), + PRT_ENTRY(0x0009FFFF, 2, GSI3), + PRT_ENTRY(0x0009FFFF, 3, GSI0), + + PRT_ENTRY(0x000AFFFF, 0, GSI2), + PRT_ENTRY(0x000AFFFF, 1, GSI3), + PRT_ENTRY(0x000AFFFF, 2, GSI0), + PRT_ENTRY(0x000AFFFF, 3, GSI1), + + PRT_ENTRY(0x000BFFFF, 0, GSI3), + PRT_ENTRY(0x000BFFFF, 1, GSI0), + PRT_ENTRY(0x000BFFFF, 2, GSI1), + PRT_ENTRY(0x000BFFFF, 3, GSI2), + + PRT_ENTRY(0x000CFFFF, 0, GSI0), + PRT_ENTRY(0x000CFFFF, 1, GSI1), + PRT_ENTRY(0x000CFFFF, 2, GSI2), + PRT_ENTRY(0x000CFFFF, 3, GSI3), + + PRT_ENTRY(0x000DFFFF, 0, GSI1), + PRT_ENTRY(0x000DFFFF, 1, GSI2), + PRT_ENTRY(0x000DFFFF, 2, GSI3), + PRT_ENTRY(0x000DFFFF, 3, GSI0), + + PRT_ENTRY(0x000EFFFF, 0, GSI2), + PRT_ENTRY(0x000EFFFF, 1, GSI3), + PRT_ENTRY(0x000EFFFF, 2, GSI0), + PRT_ENTRY(0x000EFFFF, 3, GSI1), + + PRT_ENTRY(0x000FFFFF, 0, GSI3), + PRT_ENTRY(0x000FFFFF, 1, GSI0), + PRT_ENTRY(0x000FFFFF, 2, GSI1), + PRT_ENTRY(0x000FFFFF, 3, GSI2), + + PRT_ENTRY(0x0010FFFF, 0, GSI0), + PRT_ENTRY(0x0010FFFF, 1, GSI1), + PRT_ENTRY(0x0010FFFF, 2, GSI2), + PRT_ENTRY(0x0010FFFF, 3, GSI3), + + PRT_ENTRY(0x0011FFFF, 0, GSI1), + PRT_ENTRY(0x0011FFFF, 1, GSI2), + PRT_ENTRY(0x0011FFFF, 2, GSI3), + PRT_ENTRY(0x0011FFFF, 3, GSI0), + + PRT_ENTRY(0x0012FFFF, 0, GSI2), + PRT_ENTRY(0x0012FFFF, 1, GSI3), + PRT_ENTRY(0x0012FFFF, 2, GSI0), + PRT_ENTRY(0x0012FFFF, 3, GSI1), + + PRT_ENTRY(0x0013FFFF, 0, GSI3), + PRT_ENTRY(0x0013FFFF, 1, GSI0), + PRT_ENTRY(0x0013FFFF, 2, GSI1), + PRT_ENTRY(0x0013FFFF, 3, GSI2), + + PRT_ENTRY(0x0014FFFF, 0, GSI0), + PRT_ENTRY(0x0014FFFF, 1, GSI1), + PRT_ENTRY(0x0014FFFF, 2, GSI2), + PRT_ENTRY(0x0014FFFF, 3, GSI3), + + PRT_ENTRY(0x0015FFFF, 0, GSI1), + PRT_ENTRY(0x0015FFFF, 1, GSI2), + PRT_ENTRY(0x0015FFFF, 2, GSI3), + PRT_ENTRY(0x0015FFFF, 3, GSI0), + + PRT_ENTRY(0x0016FFFF, 0, GSI2), + PRT_ENTRY(0x0016FFFF, 1, GSI3), + PRT_ENTRY(0x0016FFFF, 2, GSI0), + PRT_ENTRY(0x0016FFFF, 3, GSI1), + + PRT_ENTRY(0x0017FFFF, 0, GSI3), + PRT_ENTRY(0x0017FFFF, 1, GSI0), + PRT_ENTRY(0x0017FFFF, 2, GSI1), + PRT_ENTRY(0x0017FFFF, 3, GSI2), + + PRT_ENTRY(0x0018FFFF, 0, GSI0), + PRT_ENTRY(0x0018FFFF, 1, GSI1), + PRT_ENTRY(0x0018FFFF, 2, GSI2), + PRT_ENTRY(0x0018FFFF, 3, GSI3), + + PRT_ENTRY(0x0019FFFF, 0, GSI1), + PRT_ENTRY(0x0019FFFF, 1, GSI2), + PRT_ENTRY(0x0019FFFF, 2, GSI3), + PRT_ENTRY(0x0019FFFF, 3, GSI0), + + PRT_ENTRY(0x001AFFFF, 0, GSI2), + PRT_ENTRY(0x001AFFFF, 1, GSI3), + PRT_ENTRY(0x001AFFFF, 2, GSI0), + PRT_ENTRY(0x001AFFFF, 3, GSI1), + + PRT_ENTRY(0x001BFFFF, 0, GSI3), + PRT_ENTRY(0x001BFFFF, 1, GSI0), + PRT_ENTRY(0x001BFFFF, 2, GSI1), + PRT_ENTRY(0x001BFFFF, 3, GSI2), + + PRT_ENTRY(0x001CFFFF, 0, GSI0), + PRT_ENTRY(0x001CFFFF, 1, GSI1), + PRT_ENTRY(0x001CFFFF, 2, GSI2), + PRT_ENTRY(0x001CFFFF, 3, GSI3), + + PRT_ENTRY(0x001DFFFF, 0, GSI1), + PRT_ENTRY(0x001DFFFF, 1, GSI2), + PRT_ENTRY(0x001DFFFF, 2, GSI3), + PRT_ENTRY(0x001DFFFF, 3, GSI0), + + PRT_ENTRY(0x001EFFFF, 0, GSI2), + PRT_ENTRY(0x001EFFFF, 1, GSI3), + PRT_ENTRY(0x001EFFFF, 2, GSI0), + PRT_ENTRY(0x001EFFFF, 3, GSI1), + + PRT_ENTRY(0x001FFFFF, 0, GSI3), + PRT_ENTRY(0x001FFFFF, 1, GSI0), + PRT_ENTRY(0x001FFFFF, 2, GSI1), + PRT_ENTRY(0x001FFFFF, 3, GSI2), + }) + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + SBSA_PCIE_MMIO_BASE, // Min Base Address + SBSA_PCIE_MMIO_LIMIT, // Max Base Address + 0, // Translate + SBSA_PCIE_MMIO_SIZE // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + SBSA_PCIE_MMIO_HIGH_BASE, // Min Base Address + SBSA_PCIE_MMIO_HIGH_LIMIT, // Max Base Address + 0, // Translate + SBSA_PCIE_MMIO_HIGH_SIZE // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + 0, // Min Base Address + 0xffff, // Max Base Address + SBSA_PCIE_PIO_BASE, // Translate + 0x10000, // Length + ,,,TypeTranslation + ) + }) // Name(RBUF) + + Return (RBUF) + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + SBSA_PCIE_ECAM_BASE, // Range Minimum + SBSA_PCIE_ECAM_LIMIT, // Range Maximum + 0x0000000000000000, // Translation Offset + SBSA_PCIE_ECAM_SIZE, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Method (_STA) { + Return (0xF) + } + } + + // OS Control Handoff + Name (SUPP, Zero) // PCI _OSC Support Field value + Name (CTRL, Zero) // PCI _OSC Control Field value + + /* + * See [1] 6.2.10, [2] 4.5 + */ + Method (_OSC,4) { + // Check for proper UUID + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField (Arg3,0,CDW1) + CreateDWordField (Arg3,4,CDW2) + CreateDWordField (Arg3,8,CDW3) + + // Save Capabilities DWord2 & 3 + Store (CDW2,SUPP) + Store (CDW3,CTRL) + + // Only allow native hot plug control if OS supports: + // * ASPM + // * Clock PM + // * MSI/MSI-X + If ((SUPP & 0x16) != 0x16) { + CTRL &= 0x1E // Mask bit 0 (and undefined bits) + } + + // Always allow native PME, AER (no dependencies) + + // Never allow SHPC (no SHPC controller in this system) + CTRL &= 0x1D + + If (Arg1 != One) { // Unknown revision + CDW1 |= 0x08 + } + + If (CDW3 != CTRL) { // Capabilities bits were masked + CDW1 |= 0x10 + } + + // Update DWORD3 in the buffer + Store (CTRL,CDW3) + Return (Arg3) + } Else { + CDW1 |= 4 // Unrecognized UUID + Return (Arg3) + } + } // End _OSC + } + } // Scope (_SB) +} diff --git a/src/mainboard/emulation/qemu-sbsa/flash.fmd b/src/mainboard/emulation/qemu-sbsa/flash.fmd new file mode 100644 index 0000000..e847aab --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/flash.fmd @@ -0,0 +1,23 @@ +# +# custom fmap which takes the additional TF-A region into account +# +# +-------------+ <-- 0x0 +# | TF-A | +# +-------------+ <-- BIOS_BASE +# | bootblock | +# +-------------+ <-- BIOS_BASE + 128K +# | FMAP | +# +-------------+ <-- BIOS_BASE + 128K + FMAP_SIZE +# | CBFS | +# +-------------+ <-- ROM_SIZE +# + +FLASH@0x10000000 CONFIG_ROM_SIZE { + + BIOS@0x0 CONFIG_ROM_SIZE { + + BOOTBLOCK 128K + FMAP@0x20000 0x200 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/emulation/qemu-sbsa/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-sbsa/include/mainboard/addressmap.h new file mode 100644 index 0000000..0bfaf5a --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/include/mainboard/addressmap.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Base addreses for QEMU sbsa-ref machine + * [hw/arm/sbsa-ref.c, c6f3cbca32bde9ee94d9949aa63e8a7ef2d7bc5b] + */ + +#define SBSA_FLASH_BASE 0x00000000 +#define SBSA_FLASH_SIZE 0x20000000 +#define SBSA_GIC_DIST 0x40060000 +#define SBSA_GIC_REDIST 0x40080000 +#define SBSA_GWDT_REFRESH 0x50010000 +#define SBSA_GWDT_CONTROL 0x50011000 +#define SBSA_UART_BASE 0x60000000 +#define SBSA_RTC_BASE 0x60010000 +#define SBSA_GPIO_BASE 0x60020000 +#define SBSA_SECURE_UART_BASE 0x60030000 +#define SBSA_SMMU_BASE 0x60050000 +#define SBSA_AHCI_BASE 0x60100000 +#define SBSA_EHCI_BASE 0x60110000 +#define SBSA_SECMEM_BASE 0x20000000 +#define SBSA_SECMEM_SIZE 0x20000000 +#define SBSA_PCIE_MMIO_BASE 0x80000000 +#define SBSA_PCIE_MMIO_LIMIT 0xefffffff +#define SBSA_PCIE_MMIO_SIZE 0x70000000 +#define SBSA_PCIE_PIO_BASE 0x7fff0000 +#define SBSA_PCIE_ECAM_BASE 0xf0000000 +#define SBSA_PCIE_ECAM_LIMIT 0xffffffff +#define SBSA_PCIE_ECAM_SIZE 0x10000000 +#define SBSA_PCIE_MMIO_HIGH_BASE 0x100000000 +#define SBSA_PCIE_MMIO_HIGH_LIMIT 0xffffffffff +#define SBSA_PCIE_MMIO_HIGH_SIZE 0xff00000000 diff --git a/src/mainboard/emulation/qemu-sbsa/mainboard.c b/src/mainboard/emulation/qemu-sbsa/mainboard.c new file mode 100644 index 0000000..6458e9d --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/mainboard.c @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "chip.h" +#include <acpi/acpigen.h> +#include <arch/mmu.h> +#include <bootmem.h> +#include <cbfs.h> +#include <device/device.h> +#include <device_tree.h> +#include <bootmem.h> +#include <arch/mmu.h> +#include <mainboard/addressmap.h> +#include <ramdetect.h> +#include <stdint.h> +#include <symbols.h> + +static size_t ram_size(void) +{ + return (size_t)cbmem_top() - (uintptr_t)_dram;; +} + +static void mainboard_init(void *chip_info) +{ + mmu_config_range(_dram, ram_size(), MA_MEM | MA_RW); +} + +DECLARE_REGION(fdt_pointer) +void smbios_cpu_get_core_counts(u16 *core_count, u16 *thread_count) +{ + *core_count = 0; + struct device *dev = NULL; + while ((dev = dev_find_path(dev, DEVICE_PATH_GICC_V3))) + *core_count += 1; + + *thread_count = 1; +} + +static void qemu_aarch64_init(struct device *dev) +{ + struct memory_info *mem_info; + + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) + return; + + memset(mem_info, 0, sizeof(*mem_info)); + + mem_info->ecc_type = MEMORY_ARRAY_ECC_UNKNOWN; + mem_info->max_capacity_mib = 0x800000; // Fixed at 8 TiB for qemu-sbsa + mem_info->number_of_devices = mem_info->dimm_cnt = 1; + + mem_info->dimm[0].dimm_size = ram_size() / MiB; + mem_info->dimm[0].ddr_type = MEMORY_TYPE_DRAM; + mem_info->dimm[0].ddr_frequency = 0; + mem_info->dimm[0].channel_num = mem_info->dimm[0].dimm_num = 0; + mem_info->dimm[0].bank_locator = 0; + + mem_info->dimm[0].bus_width = 0x03; // 64-bit, no parity + mem_info->dimm[0].vdd_voltage = 0; + mem_info->dimm[0].max_speed_mts = mem_info->dimm[0].configured_speed_mts = 0; +} + +static unsigned long mb_write_acpi_tables(const struct device *dev, unsigned long current, + acpi_rsdp_t *rsdp) +{ + printk(BIOS_DEBUG, "ACPI: * DBG2\n"); + return acpi_pl011_write_dbg2_uart(rsdp, current, SBSA_UART_BASE, "\\_SB.COM0"); +} + + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = qemu_aarch64_init; + dev->ops->write_acpi_tables = mb_write_acpi_tables; +} + + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .init = mainboard_init, +}; + +struct chip_operations mainboard_emulation_qemu_sbsa_ops = { }; + +static void qemu_aarch64_domain_read_resources(struct device *dev) +{ + struct resource *res; + int index = 0; + + /* Initialize the system-wide I/O space constraints. */ + res = new_resource(dev, index++); + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; + + /* Initialize the system-wide memory resources constraints. */ + res = new_resource(dev, index++); + res->base = SBSA_PCIE_MMIO_BASE; + res->limit = SBSA_PCIE_MMIO_LIMIT; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + + res = new_resource(dev, index++); + res->base = SBSA_PCIE_MMIO_HIGH_BASE; + res->limit = SBSA_PCIE_MMIO_HIGH_LIMIT; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + + mmio_range(dev, index++, SBSA_PCIE_ECAM_BASE, SBSA_PCIE_ECAM_SIZE); + + ram_range(dev, index++, (uintptr_t)_dram, ram_size()); + + mmio_range(dev, index++, SBSA_FLASH_BASE, SBSA_FLASH_SIZE); + reserved_ram_range(dev, index++, SBSA_SECMEM_BASE, SBSA_SECMEM_SIZE); +} + +struct device_operations qemu_aarch64_pci_domain_ops = { + .read_resources = qemu_aarch64_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_host_bridge_scan_bus, +}; + +static void qemu_sbsa_fill_cpu_ssdt(const struct device *dev) +{ + acpigen_write_processor_device(dev->path.gicc_v3.mpidr); + acpigen_write_processor_device_end(); +} + +struct device_operations qemu_sbsa_cpu_ops = { + .acpi_fill_ssdt = qemu_sbsa_fill_cpu_ssdt, +}; + +static void qemu_aarch64_scan_bus(struct device *dev) +{ + if (!dev->link_list) + add_more_links(dev, 1); + + uintptr_t fdt_blob = *(uintptr_t *)_fdt_pointer; + struct device_tree *tree; + char path[14]; + u16 fdt_cpu_count = 0; + struct mainboard_emulation_qemu_sbsa_config *config = dev->chip_info; + + tree = fdt_unflatten((void *)fdt_blob); + if (tree == NULL) + return; + snprintf(path, sizeof(path), "/cpus/cpu@%d", fdt_cpu_count); + for (struct device_tree_node *node = dt_find_node_by_path(tree, path, NULL, NULL, 0); node;) { + struct device_tree_property *prop; + int64_t mpidr = -1; + list_for_each(prop, node->properties, list_node) { + if (!strcmp("reg", prop->prop.name)) { + mpidr = be64toh(*(uint64_t *)prop->prop.data); + break; + } + } + if (mpidr >= 0) { + struct device_path devpath = { .type = DEVICE_PATH_GICC_V3, + .gicc_v3 = { .mpidr = mpidr, + .vgic_mi = config->vgic_maintenance_interrupt, + .pi_gsiv = config->performance_interrupt_gsiv, }, + + }; + struct device *cpu = alloc_dev(dev->link_list, &devpath); + assert(cpu); + cpu->ops = &qemu_sbsa_cpu_ops; + } + snprintf(path, sizeof(path), "/cpus/cpu@%d", ++fdt_cpu_count); + node = dt_find_node_by_path(tree, path, NULL, NULL, 0); + } + +} + +struct device_operations qemu_aarch64_cpu_ops = { + .scan_bus = qemu_aarch64_scan_bus, +}; diff --git a/src/mainboard/emulation/qemu-sbsa/media.c b/src/mainboard/emulation/qemu-sbsa/media.c new file mode 100644 index 0000000..00ed54c --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/media.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <boot_device.h> + +/* Maps directly to NOR flash up to ROM size. */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT((void *)0x10000000, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/emulation/qemu-sbsa/memlayout.ld b/src/mainboard/emulation/qemu-sbsa/memlayout.ld new file mode 100644 index 0000000..885d766 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/memlayout.ld @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <memlayout.h> +#include <arch/header.ld> + +/* + * Memory map for QEMU sbsa-ref machine since + * [hw/arm/sbsa-ref.c, c6f3cbca32bde9ee94d9949aa63e8a7ef2d7bc5b] + */ +SECTIONS +{ + REGION(flash, 0x10000000, CONFIG_ROM_SIZE, 8) + + DRAM_START(0x10000000000) + BOOTBLOCK(0x10020010000, 64K) + STACK(0x10020020000, 54K) + CBFS_MCACHE(0x1002002D800, 8K) + FMAP_CACHE(0x1002002F800, 2K) + TIMESTAMP(0x10020030000, 1K) + ROMSTAGE(0x10020031000, 128K) + TTB(0x10020070000, 128K) + RAMSTAGE(0x100200b0000, 16M) + REGION(fdt_pointer, 0x100210b0000, ARCH_POINTER_ALIGN_SIZE, ARCH_POINTER_ALIGN_SIZE) + + POSTRAM_CBFS_CACHE(0x10021200000, 1M) +} diff --git a/src/mainboard/emulation/qemu-sbsa/mmio.c b/src/mainboard/emulation/qemu-sbsa/mmio.c new file mode 100644 index 0000000..6b50856 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/mmio.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/uart.h> +#include <mainboard/addressmap.h> + +uintptr_t uart_platform_base(unsigned int idx) +{ + return SBSA_UART_BASE; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19fbaeed991fc6dbc6c001765a9b9571bf9297a4 Gerrit-Change-Number: 79107 Gerrit-PatchSet: 1 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/geralt/Kconfig: Simplify SDCARD_INIT with def_bool
by Yu-Ping Wu (Code Review) 17 Nov '23

17 Nov '23

Yu-Ping Wu has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/79076?usp=email ) Change subject: mb/google/geralt/Kconfig: Simplify SDCARD_INIT with def_bool ...................................................................... Abandoned See CB:79063 -- To view, visit https://review.coreboot.org/c/coreboot/+/79076?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie033204894e829ab3bff79297e93861a4585495a Gerrit-Change-Number: 79076 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[XS] Change in coreboot[main]: mb/google/corsola/Kconfig: Simplify SDCARD_INIT with def_bool
by Yu-Ping Wu (Code Review) 17 Nov '23

17 Nov '23

Yu-Ping Wu has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/79075?usp=email ) Change subject: mb/google/corsola/Kconfig: Simplify SDCARD_INIT with def_bool ...................................................................... Abandoned See CB:79063 -- To view, visit https://review.coreboot.org/c/coreboot/+/79075?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I249917cccfd644d69546c4602a3190d03d0b3277 Gerrit-Change-Number: 79075 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[XS] Change in coreboot[main]: mb/google/geralt/Kconfig: Simplify SDCARD_INIT with def_bool
by Yidi Lin (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79076?usp=email ) Change subject: mb/google/geralt/Kconfig: Simplify SDCARD_INIT with def_bool ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79076?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie033204894e829ab3bff79297e93861a4585495a Gerrit-Change-Number: 79076 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 01:11:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/corsola/Kconfig: Simplify SDCARD_INIT with def_bool
by Yidi Lin (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79075?usp=email ) Change subject: mb/google/corsola/Kconfig: Simplify SDCARD_INIT with def_bool ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79075?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I249917cccfd644d69546c4602a3190d03d0b3277 Gerrit-Change-Number: 79075 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 01:10:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: google/*: Clean up Kconfig board selection for non-MTK Google Arm boards
by Yu-Ping Wu (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Felix Singer, Julius Werner, Shelley Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79022?usp=email ) Change subject: google/*: Clean up Kconfig board selection for non-MTK Google Arm boards ...................................................................... Patch Set 1: Code-Review+2 (2 comments) Patchset: PS1: Everything looks good to me except for the problem mentioned by Nico. File src/mainboard/google/gru/Kconfig: https://review.coreboot.org/c/coreboot/+/79022/comment/0399b813_466169ed : PS1, Line 30: def_bool BOARD_GOOGLE_SCARLET || \ sort if you prefer. -- To view, visit https://review.coreboot.org/c/coreboot/+/79022?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If679a05afd10869afba9c2a33b54862e102b5f40 Gerrit-Change-Number: 79022 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 17 Nov 2023 01:03:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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