coreboot-gerrit November 2023

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[M] Change in coreboot[main]: mb/google/geralt: Move backlight-related functions to common panel.c
by Yu-Ping Wu (Code Review) 17 Nov '23

17 Nov '23

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78955?usp=email ) Change subject: mb/google/geralt: Move backlight-related functions to common panel.c ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78955?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d4035d5f480551c428c450826e23bf77f2fe08a Gerrit-Change-Number: 78955 Gerrit-PatchSet: 6 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 23:52:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/geralt: Disable SD card support for Ciri
by Yu-Ping Wu (Code Review) 17 Nov '23

17 Nov '23

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78958?usp=email ) Change subject: mb/google/geralt: Disable SD card support for Ciri ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78958?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id4e021e7896d093560f39c40573ac616d76438c2 Gerrit-Change-Number: 78958 Gerrit-PatchSet: 4 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 23:47:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: util/docker: Switch back to root user in jenkins-node
by Martin L Roth (Code Review) 17 Nov '23

17 Nov '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79067?usp=email ) Change subject: util/docker: Switch back to root user in jenkins-node ...................................................................... util/docker: Switch back to root user in jenkins-node Leaving the user as coreboot caused the entrypoint to run as coreboot, which means we couldn't mount directories or run sshd correctly. Switching to root at the end of the file fixes this. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ie10e1d7ad4def0faafe3bcd580a77e23c3bfe948 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79067 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/docker/coreboot-jenkins-node/Dockerfile 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile index 2cd8d78..f1ab4e9 100644 --- a/util/docker/coreboot-jenkins-node/Dockerfile +++ b/util/docker/coreboot-jenkins-node/Dockerfile @@ -89,3 +89,4 @@ echo "{{SSH_KEY}}" > /home/coreboot/.ssh/authorized_keys && \ chmod 0700 /home/coreboot/.ssh && \ chmod 0600 /home/coreboot/.ssh/authorized_keys +USER root -- To view, visit https://review.coreboot.org/c/coreboot/+/79067?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie10e1d7ad4def0faafe3bcd580a77e23c3bfe948 Gerrit-Change-Number: 79067 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: util/ifdtool/ifdtool.c: Add NULL check for fmapname
by Matt DeVillier (Code Review) 17 Nov '23

17 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79010?usp=email ) Change subject: util/ifdtool/ifdtool.c: Add NULL check for fmapname ...................................................................... util/ifdtool/ifdtool.c: Add NULL check for fmapname Some boards (e.g. prodrive/hermes) that do not provide their own FMAP and therefore have been generated by the build system (+ ifdtool) experience a failure when trying to build with an IFD that contains regions which do not have equivalent fmap names (set to NULL). Therefore add a NULL check for the fmapname and ignore the region if we do not have an fmapname. Test: compile prodrive/hermes Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Ib4589b7fdbd11d644214ca5601536e9aeb26882f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79010 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M util/ifdtool/ifdtool.c 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index ddbc0fb..43451b1 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -1068,6 +1068,14 @@ if (region.limit == 0 || region.base == 0x07FFF000) continue; + /* Is there an FMAP equivalent? IFD reserved regions are usually thrown out + * of the FMAP here + */ + if (!region_names[region.type].fmapname) { + printf("Skip IFD region: %s\n", region_names[region.type].pretty); + continue; + } + /* Here we decide to use the coreboot generated FMAP BIOS region, instead of * the one specified in the IFD. The case when IFD and FMAP BIOS region do not * match cannot be caught here, therefore one should still validate IFD and -- To view, visit https://review.coreboot.org/c/coreboot/+/79010?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4589b7fdbd11d644214ca5601536e9aeb26882f Gerrit-Change-Number: 79010 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: ec/google/chromeec: Update ec_cmd_api.h and ec_commands.h
by Matt DeVillier (Code Review) 17 Nov '23

17 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79066?usp=email ) Change subject: ec/google/chromeec: Update ec_cmd_api.h and ec_commands.h ...................................................................... ec/google/chromeec: Update ec_cmd_api.h and ec_commands.h Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: ab9b64ac4c Add a host command to print info about AP-firmware state The original include/ec_cmd_api.h version in the EC repo is: ab9b64ac4c Add a host command to print info about AP-firmware state BUG=b:300525571 BRANCH=none TEST=none Change-Id: I3570e073a91621cb1d28a24aa35c1f4beedceaab Signed-off-by: Simon Glass <sjg(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79066 Reviewed-by: Caveh Jalali <caveh(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/chromeec/ec_cmd_api.h M src/ec/google/chromeec/ec_commands.h 2 files changed, 471 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Caveh Jalali: Looks good to me, approved diff --git a/src/ec/google/chromeec/ec_cmd_api.h b/src/ec/google/chromeec/ec_cmd_api.h index 7438ee6..2b0bdde 100644 --- a/src/ec/google/chromeec/ec_cmd_api.h +++ b/src/ec/google/chromeec/ec_cmd_api.h @@ -45,6 +45,12 @@ * Please keep this list sorted by function name. */ +static inline int ec_cmd_battery_config(CROS_EC_COMMAND_INFO *h, uint8_t *r) +{ + return CROS_EC_COMMAND(h, EC_CMD_BATTERY_CONFIG, 0, NULL, 0, r, + BATT_CONF_MAX_SIZE); +} + static inline int ec_cmd_get_sku_id(CROS_EC_COMMAND_INFO *h, struct ec_sku_id_info *r) { @@ -232,6 +238,7 @@ _CROS_EC_C0_F_PF_RF(EC_CMD_ADC_READ, adc_read); _CROS_EC_CV_F_P(EC_CMD_ADD_ENTROPY, 0, add_entropy, rollback_add_entropy); +_CROS_EC_C0_F_PF(EC_CMD_AP_FW_STATE, ap_fw_state); _CROS_EC_C0_F(EC_CMD_AP_RESET, ap_reset); _CROS_EC_CV_F_P(EC_CMD_BATTERY_CUT_OFF, 1, battery_cut_off_v1, battery_cutoff); _CROS_EC_C0_F(EC_CMD_BATTERY_CUT_OFF, battery_cut_off); @@ -247,6 +254,9 @@ _CROS_EC_C0_F_PF(EC_CMD_BUTTON, button); _CROS_EC_C0_F_PF_RF(EC_CMD_CEC_GET, cec_get); _CROS_EC_C0_F_PF(EC_CMD_CEC_SET, cec_set); +_CROS_EC_C1_F_PF(EC_CMD_CEC_WRITE_MSG, cec_write); +_CROS_EC_C0_F_PF_RF(EC_CMD_CEC_READ_MSG, cec_read); +_CROS_EC_C0_F_RF(EC_CMD_CEC_PORT_COUNT, cec_port_count); _CROS_EC_C0_F_PF_RF(EC_CMD_CHARGESPLASH, chargesplash); _CROS_EC_CV_F_P_R(EC_CMD_CHARGE_CONTROL, 2, charge_control_v2, charge_control, charge_control); diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index a55c075..b66f9d3 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -693,6 +693,49 @@ EC_RES_MAX = UINT16_MAX, /**< Force enum to be 16 bits */ } __packed; BUILD_ASSERT(sizeof(enum ec_status) == sizeof(uint16_t)); +#ifdef CONFIG_EC_HOST_CMD +/* + * Make sure Zephyre uses the same status codes. + */ +#include <zephyr/mgmt/ec_host_cmd/ec_host_cmd.h> + +BUILD_ASSERT((uint16_t)EC_RES_SUCCESS == (uint16_t)EC_HOST_CMD_SUCCESS); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_COMMAND == + (uint16_t)EC_HOST_CMD_INVALID_COMMAND); +BUILD_ASSERT((uint16_t)EC_RES_ERROR == (uint16_t)EC_HOST_CMD_ERROR); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_PARAM == + (uint16_t)EC_HOST_CMD_INVALID_PARAM); +BUILD_ASSERT((uint16_t)EC_RES_ACCESS_DENIED == + (uint16_t)EC_HOST_CMD_ACCESS_DENIED); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_RESPONSE == + (uint16_t)EC_HOST_CMD_INVALID_RESPONSE); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_VERSION == + (uint16_t)EC_HOST_CMD_INVALID_VERSION); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_CHECKSUM == + (uint16_t)EC_HOST_CMD_INVALID_CHECKSUM); +BUILD_ASSERT((uint16_t)EC_RES_IN_PROGRESS == (uint16_t)EC_HOST_CMD_IN_PROGRESS); +BUILD_ASSERT((uint16_t)EC_RES_UNAVAILABLE == (uint16_t)EC_HOST_CMD_UNAVAILABLE); +BUILD_ASSERT((uint16_t)EC_RES_TIMEOUT == (uint16_t)EC_HOST_CMD_TIMEOUT); +BUILD_ASSERT((uint16_t)EC_RES_OVERFLOW == (uint16_t)EC_HOST_CMD_OVERFLOW); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_HEADER == + (uint16_t)EC_HOST_CMD_INVALID_HEADER); +BUILD_ASSERT((uint16_t)EC_RES_REQUEST_TRUNCATED == + (uint16_t)EC_HOST_CMD_REQUEST_TRUNCATED); +BUILD_ASSERT((uint16_t)EC_RES_RESPONSE_TOO_BIG == + (uint16_t)EC_HOST_CMD_RESPONSE_TOO_BIG); +BUILD_ASSERT((uint16_t)EC_RES_BUS_ERROR == (uint16_t)EC_HOST_CMD_BUS_ERROR); +BUILD_ASSERT((uint16_t)EC_RES_BUSY == (uint16_t)EC_HOST_CMD_BUSY); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_HEADER_VERSION == + (uint16_t)EC_HOST_CMD_INVALID_HEADER_VERSION); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_HEADER_CRC == + (uint16_t)EC_HOST_CMD_INVALID_HEADER_CRC); +BUILD_ASSERT((uint16_t)EC_RES_INVALID_DATA_CRC == + (uint16_t)EC_HOST_CMD_INVALID_DATA_CRC); +BUILD_ASSERT((uint16_t)EC_RES_DUP_UNAVAILABLE == + (uint16_t)EC_HOST_CMD_DUP_UNAVAILABLE); +BUILD_ASSERT((uint16_t)EC_RES_MAX == (uint16_t)EC_HOST_CMD_MAX); + +#endif /* * Host event codes. ACPI query EC command uses code 0 to mean "no event @@ -1591,6 +1634,30 @@ * The EC supports the AP composing VDMs for us to send. */ EC_FEATURE_TYPEC_AP_VDM_SEND = 46, + /* + * The EC supports system safe mode panic recovery. + */ + EC_FEATURE_SYSTEM_SAFE_MODE = 47, + /* + * The EC will reboot on runtime assertion failures. + */ + EC_FEATURE_ASSERT_REBOOTS = 48, + /* + * The EC image is built with tokenized logging enabled. + */ + EC_FEATURE_TOKENIZED_LOGGING = 49, + /* + * The EC supports triggering an STB dump. + */ + EC_FEATURE_AMD_STB_DUMP = 50, + /* + * The EC supports memory dump commands. + */ + EC_FEATURE_MEMORY_DUMP = 51, + /* + * The EC supports DP2.1 capability + */ + EC_FEATURE_TYPEC_DP2_1 = 52, }; #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) @@ -1880,6 +1947,19 @@ uint32_t flags; } __ec_align4; +enum flash_protect_action { + FLASH_PROTECT_ASYNC = 0, + FLASH_PROTECT_GET_RESULT = 1, +}; + +/* Version 2 of the command is "asynchronous". */ +struct ec_params_flash_protect_v2 { + uint8_t action; /**< enum flash_protect_action */ + uint8_t reserved[3]; /**< padding for alignment */ + uint32_t mask; + uint32_t flags; +} __ec_align4; + /** * struct ec_response_flash_protect - Response to the flash protect command. * @flags: Current value of flash protect flags. @@ -4377,7 +4457,7 @@ * discharge the battery. */ #define EC_CMD_CHARGE_CONTROL 0x0096 -#define EC_VER_CHARGE_CONTROL 2 +#define EC_VER_CHARGE_CONTROL 3 enum ec_charge_control_mode { CHARGE_CONTROL_NORMAL = 0, @@ -4399,12 +4479,16 @@ EC_CHARGE_CONTROL_CMD_GET, }; +enum ec_charge_control_flag { + EC_CHARGE_CONTROL_FLAG_NO_IDLE = BIT(0), +}; + struct ec_params_charge_control { uint32_t mode; /* enum charge_control_mode */ /* Below are the fields added in V2. */ uint8_t cmd; /* enum ec_charge_control_cmd. */ - uint8_t reserved; + uint8_t flags; /* enum ec_charge_control_flag (v3+) */ /* * Lower and upper thresholds for battery sustainer. This struct isn't * named to avoid tainting foreign projects' name spaces. @@ -4426,7 +4510,8 @@ int8_t lower; int8_t upper; } sustain_soc; - uint16_t reserved; + uint8_t flags; /* enum ec_charge_control_flag (v3+) */ + uint8_t reserved; } __ec_align4; /*****************************************************************************/ @@ -5098,8 +5183,20 @@ * These commands are for sending and receiving message via HDMI CEC */ +#define EC_CEC_MAX_PORTS 16 + #define MAX_CEC_MSG_LEN 16 +/* + * Helper macros for packing/unpacking cec_events. + * bits[27:0] : bitmask of events from enum mkbp_cec_event + * bits[31:28]: port number + */ +#define EC_MKBP_EVENT_CEC_PACK(events, port) \ + (((events)&GENMASK(27, 0)) | (((port)&0xf) << 28)) +#define EC_MKBP_EVENT_CEC_GET_EVENTS(event) ((event)&GENMASK(27, 0)) +#define EC_MKBP_EVENT_CEC_GET_PORT(event) (((event) >> 28) & 0xf) + /* CEC message from the AP to be written on the CEC bus */ #define EC_CMD_CEC_WRITE_MSG 0x00B8 @@ -5111,19 +5208,54 @@ uint8_t msg[MAX_CEC_MSG_LEN]; } __ec_align1; +/** + * struct ec_params_cec_write_v1 - Message to write to the CEC bus + * @port: CEC port to write the message on + * @msg_len: length of msg in bytes + * @msg: message content to write to the CEC bus + */ +struct ec_params_cec_write_v1 { + uint8_t port; + uint8_t msg_len; + uint8_t msg[MAX_CEC_MSG_LEN]; +} __ec_align1; + +/* CEC message read from a CEC bus reported back to the AP */ +#define EC_CMD_CEC_READ_MSG 0x00B9 + +/** + * struct ec_params_cec_read - Read a message from the CEC bus + * @port: CEC port to read a message on + */ +struct ec_params_cec_read { + uint8_t port; +} __ec_align1; + +/** + * struct ec_response_cec_read - Message read from the CEC bus + * @msg_len: length of msg in bytes + * @msg: message content read from the CEC bus + */ +struct ec_response_cec_read { + uint8_t msg_len; + uint8_t msg[MAX_CEC_MSG_LEN]; +} __ec_align1; + /* Set various CEC parameters */ #define EC_CMD_CEC_SET 0x00BA /** * struct ec_params_cec_set - CEC parameters set * @cmd: parameter type, can be CEC_CMD_ENABLE or CEC_CMD_LOGICAL_ADDRESS + * @port: CEC port to set the parameter on * @val: in case cmd is CEC_CMD_ENABLE, this field can be 0 to disable CEC * or 1 to enable CEC functionality, in case cmd is * CEC_CMD_LOGICAL_ADDRESS, this field encodes the requested logical * address between 0 and 15 or 0xff to unregister */ struct ec_params_cec_set { - uint8_t cmd; /* enum cec_command */ + uint8_t cmd : 4; /* enum cec_command */ + uint8_t port : 4; uint8_t val; } __ec_align1; @@ -5133,9 +5265,11 @@ /** * struct ec_params_cec_get - CEC parameters get * @cmd: parameter type, can be CEC_CMD_ENABLE or CEC_CMD_LOGICAL_ADDRESS + * @port: CEC port to get the parameter on */ struct ec_params_cec_get { - uint8_t cmd; /* enum cec_command */ + uint8_t cmd : 4; /* enum cec_command */ + uint8_t port : 4; } __ec_align1; /** @@ -5149,6 +5283,17 @@ uint8_t val; } __ec_align1; +/* Get the number of CEC ports */ +#define EC_CMD_CEC_PORT_COUNT 0x00C1 + +/** + * struct ec_response_cec_port_count - CEC port count response + * @port_count: number of CEC ports + */ +struct ec_response_cec_port_count { + uint8_t port_count; +} __ec_align1; + /* CEC parameters command */ enum cec_command { /* CEC reading, writing and events enable */ @@ -5163,6 +5308,8 @@ EC_MKBP_CEC_SEND_OK = BIT(0), /* Outgoing message was not acknowledged */ EC_MKBP_CEC_SEND_FAILED = BIT(1), + /* Incoming message can be read out by AP */ + EC_MKBP_CEC_HAVE_DATA = BIT(2), }; /*****************************************************************************/ @@ -5474,6 +5621,11 @@ */ #define EC_CMD_GET_PANIC_INFO 0x00D3 +struct ec_params_get_panic_info_v1 { + /* Do not modify PANIC_DATA_FLAG_OLD_HOSTCMD when reading panic info */ + uint8_t preserve_old_hostcmd_flag; +} __ec_align1; + /*****************************************************************************/ /* * Special commands @@ -5877,6 +6029,10 @@ /* Negative port parameters have special meaning */ enum usb_pd_override_ports { + /* + * DONT_CHARGE is for all ports. Thus it's persistent across plug-in + * or plug-out. + */ OVERRIDE_DONT_CHARGE = -2, OVERRIDE_OFF = -1, /* [0, CONFIG_USB_PD_PORT_MAX_COUNT): Port# */ @@ -6149,9 +6305,29 @@ CBI_TAG_SSFC = 8, /* uint32_t bit field */ CBI_TAG_REWORK_ID = 9, /* uint64_t or smaller */ CBI_TAG_FACTORY_CALIBRATION_DATA = 10, /* uint32_t bit field */ + + /* + * A uint32_t field reserved for controlling common features at runtime. + * It shouldn't be used at board-level. See union ec_common_control for + * the bit definitions. + */ + CBI_TAG_COMMON_CONTROL = 11, + + /* struct board_batt_params */ + CBI_TAG_BATTERY_CONFIG = 12, + /* CBI_TAG_BATTERY_CONFIG_1 ~ 15 will use 13 ~ 27. */ + + /* Last entry */ CBI_TAG_COUNT, }; +union ec_common_control { + struct { + uint32_t bcic_enabled : 1; + }; + uint32_t raw_value; +}; + /* * Flags to control read operation * @@ -7460,6 +7636,166 @@ uint32_t vdm_attention[2]; } __ec_align1; +/* + * Get an active battery config from the EC. + */ +#define EC_CMD_BATTERY_CONFIG 0x013D + +/* Version of struct batt_conf_header and its internals. */ +#define EC_BATTERY_CONFIG_STRUCT_VERSION 0x00 + +/* Number of writes needed to invoke battery cutoff command */ +#define SHIP_MODE_WRITES 2 + +struct ship_mode_info { + uint8_t reg_addr; + uint8_t reserved; + uint16_t reg_data[SHIP_MODE_WRITES]; +} __packed __aligned(2); + +struct sleep_mode_info { + uint8_t reg_addr; + uint8_t reserved; + uint16_t reg_data; +} __packed __aligned(2); + +struct fet_info { + uint8_t reg_addr; + uint8_t reserved; + uint16_t reg_mask; + uint16_t disconnect_val; + uint16_t cfet_mask; /* CHG FET status mask */ + uint16_t cfet_off_val; +} __packed __aligned(2); + +enum fuel_gauge_flags { + /* + * Write Block Support. If enabled, we use a i2c write block command + * instead of a 16-bit write. The effective difference is the i2c + * transaction will prefix the length (2). + */ + FUEL_GAUGE_FLAG_WRITE_BLOCK = BIT(0), + /* Sleep command support. fuel_gauge_info.sleep_mode must be defined. */ + FUEL_GAUGE_FLAG_SLEEP_MODE = BIT(1), + /* + * Manufacturer access command support. If enabled, FET status is read + * from the OperationStatus (0x54) register using the + * ManufacturerBlockAccess (0x44). + */ + FUEL_GAUGE_FLAG_MFGACC = BIT(2), + /* + * SMB block protocol support in manufacturer access command. If + * enabled, FET status is read from the OperationStatus (0x54) register + * using the ManufacturerBlockAccess (0x44). + */ + FUEL_GAUGE_FLAG_MFGACC_SMB_BLOCK = BIT(3), +}; + +struct fuel_gauge_info { + uint32_t flags; + uint32_t board_flags; + struct ship_mode_info ship_mode; + struct sleep_mode_info sleep_mode; + struct fet_info fet; +} __packed __aligned(4); + +/* Battery constants */ +struct battery_info { + /* Operation voltage in mV */ + uint16_t voltage_max; + uint16_t voltage_normal; + uint16_t voltage_min; + /* (TODO(chromium:756700): add desired_charging_current */ + /** + * Pre-charge to fast charge threshold in mV, + * default to voltage_min if not specified. + * This option is only available on isl923x and rt946x. + */ + uint16_t precharge_voltage; + /* Pre-charge current in mA */ + uint16_t precharge_current; + /* Working temperature ranges in degrees C */ + int8_t start_charging_min_c; + int8_t start_charging_max_c; + int8_t charging_min_c; + int8_t charging_max_c; + int8_t discharging_min_c; + int8_t discharging_max_c; + /* Used only if CONFIG_BATTERY_VENDOR_PARAM is defined. */ + uint8_t vendor_param_start; + uint8_t reserved; +} __packed __aligned(2); + +/** + * The 'config' of a battery. + */ +struct board_batt_params { + struct fuel_gauge_info fuel_gauge; + struct battery_info batt_info; +} __packed __aligned(4); + +#define SBS_MAX_STRING_SIZE 32 + +/** + * Header describing a battery config stored in CBI. Only struct_version has + * size and position independent of struct_version. The rest varies as + * struct_version changes. + * + * Version 0 + * Layout: + * +-------------+ + * | header | + * +-------------+ + * | | ^ + * | manuf_name | | manuf_name_size + * | | v + * +-------------+ + * | device_name | ^ + * | | | device_name_size + * | | v + * +-------------+ + * | config | ^ + * | | | + * | | | cbi data size + * | | | - (header_size+manuf_name_size+device_name_size) + * | | | + * | | v + * +-------------+ + * Note: + * - manuf_name and device_name are not null-terminated. + * - The config isn't aligned. It should be copied to struct board_batt_params + * before its contents are accessed. + */ +struct batt_conf_header { + /* Version independent field. It's always here as a uint8_t. */ + uint8_t struct_version; + /* Version 0 members */ + uint8_t manuf_name_size; + uint8_t device_name_size; + uint8_t reserved; + /* manuf_name, device_name, board_batt_params follow after this. */ +} __packed; + +#define BATT_CONF_MAX_SIZE \ + (sizeof(struct batt_conf_header) + SBS_MAX_STRING_SIZE * 2 + \ + sizeof(struct board_batt_params)) + +/* + * Record the current AP firmware state. This is used to help testing, such as + * with FAFT (Fully-Automated Firmware Test), which likes to know which firmware + * screen is currently displayed. + */ + +#define EC_CMD_AP_FW_STATE 0x013E + +struct ec_params_ap_fw_state { + /* + * Value which indicates the state. This is not decoded by the EC, so + * its meaning is entirely outside this code base. + */ + uint32_t state; +} __ec_align1; + /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ @@ -7473,7 +7809,11 @@ /*****************************************************************************/ /* Fingerprint MCU commands: range 0x0400-0x040x */ -/* Fingerprint SPI sensor passthru command: prototyping ONLY */ +/* + * Fingerprint SPI sensor passthru command + * + * This command was used for prototyping and it's now deprecated. + */ #define EC_CMD_FP_PASSTHRU 0x0400 #define EC_FP_FLAG_NOT_COMPLETE 0x1 @@ -7721,6 +8061,12 @@ /* FP TPM seed has been set or not */ #define FP_ENC_STATUS_SEED_SET BIT(0) +/* FP using nonce context or not */ +#define FP_CONTEXT_STATUS_NONCE_CONTEXT_SET BIT(1) +/* FP match had been processed or not */ +#define FP_CONTEXT_STATUS_MATCH_PROCESSED_SET BIT(2) +/* FP auth_nonce had been set or not*/ +#define FP_CONTEXT_AUTH_NONCE_SET BIT(3) struct ec_response_fp_encryption_status { /* Used bits in encryption engine status */ @@ -7740,6 +8086,115 @@ uint8_t positive_match_secret[FP_POSITIVE_MATCH_SECRET_BYTES]; } __ec_align4; +#define FP_ELLIPTIC_CURVE_PUBLIC_KEY_POINT_LEN 32 + +struct fp_elliptic_curve_public_key { + uint8_t x[FP_ELLIPTIC_CURVE_PUBLIC_KEY_POINT_LEN]; + uint8_t y[FP_ELLIPTIC_CURVE_PUBLIC_KEY_POINT_LEN]; +} __ec_align4; + +#define FP_AES_KEY_ENC_METADATA_VERSION 1 +#define FP_AES_KEY_NONCE_BYTES 12 +#define FP_AES_KEY_ENCRYPTION_SALT_BYTES 16 +#define FP_AES_KEY_TAG_BYTES 16 + +struct fp_auth_command_encryption_metadata { + /* Version of the structure format */ + uint16_t struct_version; + /* Reserved bytes, set to 0. */ + uint16_t reserved; + /* + * The salt is *only* ever used for key derivation. The nonce is unique, + * a different one is used for every message. + */ + uint8_t nonce[FP_AES_KEY_NONCE_BYTES]; + uint8_t encryption_salt[FP_AES_KEY_ENCRYPTION_SALT_BYTES]; + uint8_t tag[FP_AES_KEY_TAG_BYTES]; +} __ec_align4; + +#define FP_ELLIPTIC_CURVE_PRIVATE_KEY_LEN 32 +#define FP_ELLIPTIC_CURVE_PUBLIC_KEY_IV_LEN 16 + +struct fp_encrypted_private_key { + struct fp_auth_command_encryption_metadata info; + uint8_t data[FP_ELLIPTIC_CURVE_PRIVATE_KEY_LEN]; +} __ec_align4; + +#define EC_CMD_FP_ESTABLISH_PAIRING_KEY_KEYGEN 0x0410 + +struct ec_response_fp_establish_pairing_key_keygen { + struct fp_elliptic_curve_public_key pubkey; + struct fp_encrypted_private_key encrypted_private_key; +} __ec_align4; + +#define FP_PAIRING_KEY_LEN 32 + +struct ec_fp_encrypted_pairing_key { + struct fp_auth_command_encryption_metadata info; + uint8_t data[FP_PAIRING_KEY_LEN]; +} __ec_align4; + +#define EC_CMD_FP_ESTABLISH_PAIRING_KEY_WRAP 0x0411 + +struct ec_params_fp_establish_pairing_key_wrap { + struct fp_elliptic_curve_public_key peers_pubkey; + struct fp_encrypted_private_key encrypted_private_key; +} __ec_align4; + +struct ec_response_fp_establish_pairing_key_wrap { + struct ec_fp_encrypted_pairing_key encrypted_pairing_key; +} __ec_align4; + +#define EC_CMD_FP_LOAD_PAIRING_KEY 0x0412 + +typedef struct ec_response_fp_establish_pairing_key_wrap + ec_params_fp_load_pairing_key; + +#define FP_CK_AUTH_NONCE_LEN 32 + +#define EC_CMD_FP_GENERATE_NONCE 0x0413 +struct ec_response_fp_generate_nonce { + uint8_t nonce[FP_CK_AUTH_NONCE_LEN]; +} __ec_align4; + +#define FP_CONTEXT_USERID_LEN 32 +#define FP_CONTEXT_USERID_IV_LEN 16 +#define FP_CONTEXT_KEY_LEN 32 + +#define EC_CMD_FP_NONCE_CONTEXT 0x0414 +struct ec_params_fp_nonce_context { + uint8_t gsc_nonce[FP_CK_AUTH_NONCE_LEN]; + uint8_t enc_user_id[FP_CONTEXT_USERID_LEN]; + uint8_t enc_user_id_iv[FP_CONTEXT_USERID_IV_LEN]; +} __ec_align4; + +#define FP_ELLIPTIC_CURVE_PUBLIC_KEY_IV_LEN 16 + +#define EC_CMD_FP_READ_MATCH_SECRET_WITH_PUBKEY 0x0415 + +struct ec_params_fp_read_match_secret_with_pubkey { + uint16_t fgr; + uint16_t reserved; + struct fp_elliptic_curve_public_key pubkey; +} __ec_align4; + +struct ec_response_fp_read_match_secret_with_pubkey { + struct fp_elliptic_curve_public_key pubkey; + uint8_t iv[FP_ELLIPTIC_CURVE_PUBLIC_KEY_IV_LEN]; + uint8_t enc_secret[FP_POSITIVE_MATCH_SECRET_BYTES]; +} __ec_align4; + +/* Preload encrypted template into the MCU buffer */ +#define EC_CMD_FP_PRELOAD_TEMPLATE 0x0416 + +struct ec_params_fp_preload_template { + uint32_t offset; + uint32_t size; + uint16_t fgr; + uint8_t reserved[2]; + uint8_t data[]; +} __ec_align4; + /*****************************************************************************/ /* Touchpad MCU commands: range 0x0500-0x05FF */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79066?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3570e073a91621cb1d28a24aa35c1f4beedceaab Gerrit-Change-Number: 79066 Gerrit-PatchSet: 2 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: [RFC] nb/intel/haswell: Allow specifying SPD addresses in devicetree
by Keith Hui (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Angel Pons. Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79025?usp=email ) Change subject: [RFC] nb/intel/haswell: Allow specifying SPD addresses in devicetree ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I'm not sure if the potential for confusion (SPD addresses can be specified in two different places, […] Following this line of thought, have I gone too far with sandybridge? An earlier iteration was exactly the Haswell approach, but during review some devs called for SPD addresses in devicetree for boards without SPD in CBFS (which is the majority) when I proposed to drop that pre-existing (but unused) setting and go full Haswell. Boilerplate reduction I guess. We all know with memory down there is no avoiding runtime code. -- To view, visit https://review.coreboot.org/c/coreboot/+/79025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I574aec9cb6a47c8aaf275ae06c7e1fb695534b34 Gerrit-Change-Number: 79025 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Nov 2023 22:41:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: Documentation/releases: Add 24.02 release notes template
by Martin L Roth (Code Review) 16 Nov '23

16 Nov '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79073?usp=email ) Change subject: Documentation/releases: Add 24.02 release notes template ...................................................................... Documentation/releases: Add 24.02 release notes template In preparation for the upcoming release, add the template for the 24.02 release and update index.md. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I694142c31ba684e7b94640d55302b2440e25619a --- A Documentation/releases/coreboot-24.02-relnotes.md M Documentation/releases/index.md 2 files changed, 101 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/79073/1 diff --git a/Documentation/releases/coreboot-24.02-relnotes.md b/Documentation/releases/coreboot-24.02-relnotes.md new file mode 100644 index 0000000..40350ec --- /dev/null +++ b/Documentation/releases/coreboot-24.02-relnotes.md @@ -0,0 +1,99 @@ +Upcoming release - coreboot 24.02 +======================================================================== + +The 24.02 release is scheduled for Mid February, 2024 + + +Update this document with changes that should be in the release notes. + +* Please use Markdown. +* See the past few release notes for the general format. +* The chip and board additions and removals will be updated right + before the release, so those do not need to be added. +* Note that all changes before the release are done are marked upcoming. + A final version of the notes are done after the release. + +### Release number format update + +The previous release was the last to use the incrementing 4.xx release +name scheme. For this and future releases, coreboot has switched to a +Year.Month.Sub-version naming scheme. As such, the next release, +scheduled for May of 2024 will be numbered 24.05, with the sub-version +of 00 implied. If we need to do a fix or incremental release, we’ll +append the values .01, .02 and so on to the initial release value. + + +Significant or interesting changes +---------------------------------- + +* Add changes that need a full description here + +* This section should have full descriptions and can or should have + a link to the referenced commits. + + + +Additional coreboot changes +--------------------------- + +The following are changes across a number of patches, or changes worth +noting, but not needing a full description. + +* Changes that only need a line or two of description go here. + + +Changes to external resources +----------------------------- + +### Toolchain updates + + +### Git submodule pointers + + +### External payloads + + +Platform Updates +---------------- + +### Added mainboards: +* To be filled in immediately before the release by the release team + + +### Removed Mainboards +* To be filled in immediately before the release by the release team + + +### Updated SoCs +* To be filled in immediately before the release by the release team + + +Plans to move platform support to a branch +------------------------------------------ +* To be filled in immediately before the release by the release team + + +Statistics from the 4.22 to the 24.02 release +-------------------------------------------- +* To be filled in immediately before the release by the release team + + + +Significant Known and Open Issues +--------------------------------- + +Issues from the coreboot bugtracker: https://ticket.coreboot.org/ +* To be filled in immediately before the release by the release team + + + +coreboot Links and Contact Information +-------------------------------------- + +* Main Web site: https://www.coreboot.org +* Downloads: https://coreboot.org/downloads.html +* Source control: https://review.coreboot.org +* Documentation: https://doc.coreboot.org +* Issue tracker: https://ticket.coreboot.org/projects/coreboot +* Donations: https://coreboot.org/donate.html diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md index d23b03a..74968d3 100644 --- a/Documentation/releases/index.md +++ b/Documentation/releases/index.md @@ -3,7 +3,7 @@ ## Upcoming release Please add to the release notes as changes are added: -* [4.22 - November 2023](coreboot-4.22-relnotes.md) +* [24.02 - February 2024](coreboot-24.02-relnotes.md) The [checklist] contains instructions to ensure that a release covers all important things and provides a reliable format for tarballs, branch @@ -15,6 +15,7 @@ ## Previous releases +* [4.22 - November 2023](coreboot-4.22-relnotes.md) * [4.21 - August 2023](coreboot-4.21-relnotes.md) * [4.20.1 - May 2023](coreboot-4.20.1-relnotes.md) * [4.19 - January 2023](coreboot-4.19-relnotes.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/79073?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I694142c31ba684e7b94640d55302b2440e25619a Gerrit-Change-Number: 79073 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: acpi/device: Only return dev->ops->acpi_name if non-NULL
by Matt DeVillier (Code Review) 16 Nov '23

16 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77413?usp=email ) Change subject: acpi/device: Only return dev->ops->acpi_name if non-NULL ...................................................................... acpi/device: Only return dev->ops->acpi_name if non-NULL Returning a NULL device name can cause issues if something else does handle it. E.g. UART and GNA devices on Intel Alder Lake-N cause INTERNAL_POWER_ERROR BSOD's in Windows when enabled due to invalid packages being created from a NULL name Test: build/boot google/nissa (craaskvin) to Win11 Change-Id: I0679147ad3e330d706bbf97c30bc11b2432e2e8a Signed-off-by: CoolStar <coolstarorganization(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77413 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/acpi/device.c 1 file changed, 5 insertions(+), 2 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/acpi/device.c b/src/acpi/device.c index b76357e..92000a3 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -76,8 +76,11 @@ return NULL; /* Check for device specific handler */ - if (dev->ops && dev->ops->acpi_name) - return dev->ops->acpi_name(dev); + if (dev->ops && dev->ops->acpi_name) { + name = dev->ops->acpi_name(dev); + if (name) + return name; + } /* Walk up the tree to find if any parent can identify this device */ while (pdev->bus) { -- To view, visit https://review.coreboot.org/c/coreboot/+/77413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0679147ad3e330d706bbf97c30bc11b2432e2e8a Gerrit-Change-Number: 77413 Gerrit-PatchSet: 7 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: docker/coreboot-sdk: Add perl modules for gcov
by Martin L Roth (Code Review) 16 Nov '23

16 Nov '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79072?usp=email ) Change subject: docker/coreboot-sdk: Add perl modules for gcov ...................................................................... docker/coreboot-sdk: Add perl modules for gcov These perl modules are needed to run the coverage-report target for gcov. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: If32a42ce17edcbae94394f770c26d3300abebcbe --- M util/docker/coreboot-sdk/Dockerfile 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/79072/1 diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index daced1b..f1d7908 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -40,9 +40,11 @@ graphviz \ lcov \ less \ + libcapture-tiny-perl \ libcrypto++-dev \ libcurl4 \ libcurl4-openssl-dev \ + libdatetime-perl \ libelf-dev \ libfreetype-dev \ libftdi1-dev \ @@ -56,6 +58,7 @@ libpci-dev \ libreadline-dev \ libssl-dev \ + libtimedate-perl \ libusb-1.0-0-dev \ libxml2-dev \ libyaml-dev \ -- To view, visit https://review.coreboot.org/c/coreboot/+/79072?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32a42ce17edcbae94394f770c26d3300abebcbe Gerrit-Change-Number: 79072 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: Docs/security/vboot: Update list of boards with vboot
by Martin L Roth (Code Review) 16 Nov '23

16 Nov '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79071?usp=email ) Change subject: Docs/security/vboot: Update list of boards with vboot ...................................................................... Docs/security/vboot: Update list of boards with vboot Update the vboot board list for the 4.22 release. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I77c5ca2c2c36d8b1ddadad4f15d2d4148ff0b325 --- M Documentation/security/vboot/list_vboot.md 1 file changed, 26 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/79071/1 diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md index 35535d8..cbdf135 100644 --- a/Documentation/security/vboot/list_vboot.md +++ b/Documentation/security/vboot/list_vboot.md @@ -33,6 +33,7 @@ - Panther (ASUS Chromebox CN60) - Tricky (Dell Chromebox 3010) - Zako (HP Chromebox G1) +- Brox - Agah - Anahera - Anahera4ES @@ -67,6 +68,7 @@ - Primus - Primus4ES - Pujjo +- Quandiso - Redrix - Redrix4ES - Skolas @@ -81,6 +83,9 @@ - Yaviks - Yavilla - Zydron +- Nokris +- Dochi +- Anraggar - Butterfly (HP Pavilion Chromebook 14) - Cherry - Dojo @@ -92,6 +97,7 @@ - Krabby - Tentacruel - Magikarp +- Chinchou - Starmie - Banon (Acer Chromebook 15 (CB3-532)) - Celes (Samsung Chromebook 3) @@ -112,6 +118,7 @@ - Foster - Gale (Google WiFi) - Geralt +- Ciri - Asuka (Dell Chromebook 13 3380) - Caroline (Samsung Chromebook Pro) - Cave (Asus Chromebook Flip C302SA) @@ -125,9 +132,9 @@ - Scarlet - Nefario - Rainier +- Dewatt (Acer Chromebook Spin 514) - Guybrush -- Nipperkin -- Dewatt +- Nipperkin (HP Elite c645 G2 Chromebook) - Akemi (IdeaPad Flex 5/5i Chromebook) - Dratini (HP Pro c640 Chromebook) - Hatch @@ -221,14 +228,17 @@ - Rex EC ISH - Ovis - Ovis4ES +- Deku +- Deku4ES - Rex4ES +- Rex4ES EC ISH - Arcada (Latitude 5300 2-in-1 Chromebook Enterprise) - Sarien (Dell Latitude 5400 Chromebook Enterprise) -- Skyrim -- Winterhold -- Frostflow - Crystaldrift -- Markarth +- Frostflow (ASUS Chromebook CM34 Flip) +- Markarth (Acer Chromebook Plus 514) +- Skyrim +- Winterhold (Dell Latitude 3445 Chromebook) - Falco (HP Chromebook 14) - Leon (Toshiba Chromebook) - Peppy (Acer C720/C720P Chromebook) @@ -275,16 +285,16 @@ - Volteer2 - Volteer2_Ti50 - Voxel (Acer Chromebook Spin 713 (CP713-3W)) -- Dalboz -- Vilboz (Lenovo 100e/300e Gen3 AMD) -- Ezkinil (Acer Chromebook Spin 514) -- Morphius (Lenovo ThinkPad C13 Yoga Chromebook) -- Trembyle - Berknip (HP Pro c645 Chromebook Enterprise) -- Woomax (ASUS Chromebook Flip CM5) +- Dalboz - Dirinboz (HP Chromebook 14a-nd0097nr) -- Shuboz +- Ezkinil (Acer Chromebook Spin 514) - Gumboz (HP Chromebook x360 14a) +- Morphius (Lenovo ThinkPad C13 Yoga Chromebook) +- Shuboz +- Trembyle +- Vilboz (Lenovo 100e/300e Gen3 AMD) +- Woomax (ASUS Chromebook Flip CM5) ## HP - Z220 CMT Workstation @@ -316,7 +326,8 @@ - Kabylake DDR4 RVP11 - Kunimitsu - Meteorlake-P RVP -- Meteorlake-P RVP with Chrome EC +- Meteorlake-P RVP with Chrome EC for Prod Silicon +- Meteorlake-P RVP with Chrome EC for non-Prod Silicon - Meteorlake-P RVP with Microchip EC - shadowmountain - Strago @@ -395,6 +406,7 @@ - X11SSH-TF - X11SSM-F - X11SSH-F/LN4F +- X11SSW-F ## UP - Squared -- To view, visit https://review.coreboot.org/c/coreboot/+/79071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I77c5ca2c2c36d8b1ddadad4f15d2d4148ff0b325 Gerrit-Change-Number: 79071 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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