coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

1 participants
3037 discussions

[M] Change in coreboot[main]: arch/arm64: Extend cache helper functions
by David Milosevic (Code Review) 16 Nov '23

16 Nov '23

David Milosevic has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79106?usp=email ) Change subject: arch/arm64: Extend cache helper functions ...................................................................... arch/arm64: Extend cache helper functions This patch extends the cpu_get_cache_info function, so that additional information like size of cache lines can be retrieved. Furthermore, static functions were grouped and moved to the top and non-static functions to the bottom, in order to provide a better structure to the file. Patch was tested against the qemu-sbsa mainboard. Change-Id: If6fe731dc67ffeaff9344d2bd2627f45185c27de Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> --- M src/arch/arm64/armv8/cache.c M src/arch/arm64/include/armv8/arch/cache.h 2 files changed, 91 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/79106/1 diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index dbaedec..94087ce 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -11,16 +11,16 @@ #include <arch/lib_helpers.h> #include <program_loading.h> -enum cache_type cpu_get_cache_type(enum cache_level level) -{ - uint32_t ctype_bitshift = (level - 1) * 3; +enum dcache_op { + OP_DCCSW, + OP_DCCISW, + OP_DCISW, + OP_DCCIVAC, + OP_DCCVAC, + OP_DCIVAC, +}; - if (level < CACHE_L1 || level > CACHE_L7) - return NO_CACHE; - - /* 3-bits per cache-level */ - return (raw_read_clidr_el1() >> ctype_bitshift) & 0x7; -} +/* non exposed functions */ static uint64_t get_ccsidr_el1_assoc(uint64_t ccsidr_el1) { @@ -46,55 +46,36 @@ } } -void cpu_get_cache_info(enum cache_level level, enum cache_type type, size_t *cache_size, size_t *assoc) +static inline void cache_select(const enum cache_level level, const enum cache_type type) { - uint64_t ccsidr_el1; - - if (cache_size == NULL || assoc == NULL) - return; - - if (level < CACHE_L1 || level > CACHE_L7) - return; - /* [0] - Indicates instruction cache; [3:1] - Indicates cache level */ raw_write_csselr_el1(((level - 1) << 1) | (type == CACHE_INSTRUCTION)); - ccsidr_el1 = raw_read_ccsidr_el1(); +} + +static uint64_t cache_numsets(const enum cache_level level, const enum cache_type type) +{ + cache_select(level, type); + + /* (Number of sets in cache) - 1 */ + return get_ccsidr_el1_numsets( raw_read_ccsidr_el1() ) + 1; +} + +static uint64_t cache_associativity(const enum cache_level level, const enum cache_type type) +{ + cache_select(level, type); + + /* (Associativity of cache) - 1 */ + return get_ccsidr_el1_assoc( raw_read_ccsidr_el1() ) + 1; +} + +static uint8_t cache_line_bytes(const enum cache_level level, const enum cache_type type) +{ + cache_select(level, type); /* [2:0] - Indicates (Log2(Number of bytes in cache line) - 4) */ - uint8_t line_length = 1 << ((ccsidr_el1 & 0x7) + 4); - /* (Number of sets in cache) - 1 */ - uint64_t num_sets = get_ccsidr_el1_numsets(ccsidr_el1) + 1; - /* (Associativity of cache) - 1 */ - *assoc = get_ccsidr_el1_assoc(ccsidr_el1) + 1; - *cache_size = line_length * *assoc * num_sets; + return (1 << ((raw_read_ccsidr_el1() & 0x7) + 4)); } -unsigned int dcache_line_bytes(void) -{ - uint32_t ctr_el0; - static unsigned int line_bytes = 0; - - if (line_bytes) - return line_bytes; - - ctr_el0 = raw_read_ctr_el0(); - /* [19:16] - Indicates (Log2(number of words in cache line) */ - line_bytes = 1 << ((ctr_el0 >> 16) & 0xf); - /* Bytes in a word (32-bit) */ - line_bytes *= sizeof(uint32_t); - - return line_bytes; -} - -enum dcache_op { - OP_DCCSW, - OP_DCCISW, - OP_DCISW, - OP_DCCIVAC, - OP_DCCVAC, - OP_DCIVAC, -}; - /* * Do a dcache operation by virtual address. This is useful for maintaining * coherency in drivers which do DMA transfers and only need to perform @@ -127,6 +108,57 @@ isb(); } +/* exposed functions */ + +enum cache_type cpu_get_cache_type(enum cache_level level) +{ + uint32_t ctype_bitshift = (level - 1) * 3; + + if (level < CACHE_L1 || level > CACHE_L7) + return NO_CACHE; + + /* 3-bits per cache-level */ + return (raw_read_clidr_el1() >> ctype_bitshift) & 0x7; +} + +int cpu_get_cache_info(enum cache_level level, enum cache_type type, struct cache_info *info) +{ + if (info == NULL) + return -1; + + if (level < CACHE_L1 || level > CACHE_L7) + return -1; + + *info = (struct cache_info) { + + .line_bytes = cache_line_bytes(level, type), + .numsets = cache_numsets(level, type), + .associativity = cache_associativity(level, type) + }; + + /* calculate total size of the cache */ + info->size = info->line_bytes * info->associativity * info->numsets; + + return 0; +} + +unsigned int dcache_line_bytes(void) +{ + uint32_t ctr_el0; + static unsigned int line_bytes = 0; + + if (line_bytes) + return line_bytes; + + ctr_el0 = raw_read_ctr_el0(); + /* [19:16] - Indicates (Log2(number of words in cache line) */ + line_bytes = 1 << ((ctr_el0 >> 16) & 0xf); + /* Bytes in a word (32-bit) */ + line_bytes *= sizeof(uint32_t); + + return line_bytes; +} + void dcache_clean_by_mva(void const *addr, size_t len) { dcache_op_va(addr, len, OP_DCCVAC); diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index 3a72d40..a54c0ad 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -31,8 +31,15 @@ CACHE_UNIFIED = 4, }; +struct cache_info { + uint64_t size; // total size of cache in bytes + uint64_t associativity; // associativity of cache + uint64_t numsets; // number of sets in a cache + uint8_t line_bytes; // size of cache line in bytes +}; + enum cache_type cpu_get_cache_type(enum cache_level level); -void cpu_get_cache_info(enum cache_level level, enum cache_type, size_t *cache_size, size_t *assoc); +int cpu_get_cache_info(enum cache_level level, enum cache_type, struct cache_info *info); /* dcache clean by virtual address to PoC */ void dcache_clean_by_mva(void const *addr, size_t len); -- To view, visit https://review.coreboot.org/c/coreboot/+/79106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If6fe731dc67ffeaff9344d2bd2627f45185c27de Gerrit-Change-Number: 79106 Gerrit-PatchSet: 1 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: nb/amd/pi/00730F01: assign IOMMU ops in chipset devicetree
by Felix Held (Code Review) 16 Nov '23

16 Nov '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79105?usp=email ) Change subject: nb/amd/pi/00730F01: assign IOMMU ops in chipset devicetree ...................................................................... nb/amd/pi/00730F01: assign IOMMU ops in chipset devicetree Since the IOMMU is always function 2 of device 0 on bus 0, the device operations can be statically assigned in the devicetree and there's no need to bind the IOMMU device operations to the PCI device during runtime via a list of PCI IDs. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I84e949500ee86e0fcb2d15791502f5e3e7127703 --- M src/northbridge/amd/pi/00730F01/chipset.cb M src/northbridge/amd/pi/00730F01/iommu.c 2 files changed, 4 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/79105/1 diff --git a/src/northbridge/amd/pi/00730F01/chipset.cb b/src/northbridge/amd/pi/00730F01/chipset.cb index 6e065c2..b0cb0a5 100644 --- a/src/northbridge/amd/pi/00730F01/chipset.cb +++ b/src/northbridge/amd/pi/00730F01/chipset.cb @@ -10,7 +10,9 @@ device pci 0.0 alias gnb on ops amd_pi_northbridge_ops end - device pci 0.2 alias iommu off end + device pci 0.2 alias iommu off + ops amd_pi_iommu_ops + end device pci 1.0 alias gfx off end device pci 1.1 alias gfx_hda off end device pci 2.0 on end # Dummy Host Bridge, do not disable diff --git a/src/northbridge/amd/pi/00730F01/iommu.c b/src/northbridge/amd/pi/00730F01/iommu.c index 3c31db4..986c6fa 100644 --- a/src/northbridge/amd/pi/00730F01/iommu.c +++ b/src/northbridge/amd/pi/00730F01/iommu.c @@ -21,15 +21,9 @@ res->flags = IORESOURCE_MEM; } -static struct device_operations iommu_ops = { +struct device_operations amd_pi_iommu_ops = { .read_resources = iommu_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .ops_pci = &pci_dev_ops_pci, }; - -static const struct pci_driver iommu_driver __pci_driver = { - .ops = &iommu_ops, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_16H_MODEL_303F_NB_IOMMU, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/79105?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84e949500ee86e0fcb2d15791502f5e3e7127703 Gerrit-Change-Number: 79105 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: nb/amd/pi/00730F01: assign northbridge ops in chipset devicetree
by Felix Held (Code Review) 16 Nov '23

16 Nov '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79104?usp=email ) Change subject: nb/amd/pi/00730F01: assign northbridge ops in chipset devicetree ...................................................................... nb/amd/pi/00730F01: assign northbridge ops in chipset devicetree Since the northbridge is always function 0 of device 0 on bus 0, the device operations can be statically assigned in the devicetree and there's no need to bind the northbridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia7faaa468ff77e05c378c5555622c3584cfe3f81 --- M src/northbridge/amd/pi/00730F01/chipset.cb M src/northbridge/amd/pi/00730F01/northbridge.c 2 files changed, 4 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/79104/1 diff --git a/src/northbridge/amd/pi/00730F01/chipset.cb b/src/northbridge/amd/pi/00730F01/chipset.cb index bc79426..6e065c2 100644 --- a/src/northbridge/amd/pi/00730F01/chipset.cb +++ b/src/northbridge/amd/pi/00730F01/chipset.cb @@ -7,7 +7,9 @@ device domain 0 on ops amd_fam16_mod30_pci_domain_ops - device pci 0.0 alias gnb on end + device pci 0.0 alias gnb on + ops amd_pi_northbridge_ops + end device pci 0.2 alias iommu off end device pci 1.0 alias gfx off end device pci 1.1 alias gfx_hda off end diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index be4e75a..9fa9f2d 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -633,7 +633,7 @@ return current; } -static struct device_operations northbridge_operations = { +struct device_operations amd_pi_northbridge_ops = { .read_resources = nb_read_resources, .set_resources = nb_set_resources, .enable_resources = pci_dev_enable_resources, @@ -643,12 +643,6 @@ .write_acpi_tables = agesa_write_acpi_tables, }; -static const struct pci_driver family16_northbridge __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_16H_MODEL_303F_NB_HT, -}; - static void fam16_finalize(void *chip_info) { struct device *dev; -- To view, visit https://review.coreboot.org/c/coreboot/+/79104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7faaa468ff77e05c378c5555622c3584cfe3f81 Gerrit-Change-Number: 79104 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[main]: [wip] mb/emulation/rdn2: Add Arm Neoverse N2
by Naresh Solanki (Code Review) 16 Nov '23

16 Nov '23

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79103?usp=email ) Change subject: [wip] mb/emulation/rdn2: Add Arm Neoverse N2 ...................................................................... [wip] mb/emulation/rdn2: Add Arm Neoverse N2 Add support for Arm Neoverse N2 Reference design. Change-Id: I17908d3ce773d4a88924bafb1d0e9e2a043c7fbc Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- A src/mainboard/emulation/rdn2/Kconfig A src/mainboard/emulation/rdn2/Kconfig.name A src/mainboard/emulation/rdn2/Makefile.inc A src/mainboard/emulation/rdn2/acpi.c A src/mainboard/emulation/rdn2/board_info.txt A src/mainboard/emulation/rdn2/bootblock.c A src/mainboard/emulation/rdn2/bootblock_custom.S A src/mainboard/emulation/rdn2/cbmem.c A src/mainboard/emulation/rdn2/chip.h A src/mainboard/emulation/rdn2/devicetree.cb A src/mainboard/emulation/rdn2/dsdt.asl A src/mainboard/emulation/rdn2/flash.fmd A src/mainboard/emulation/rdn2/include/mainboard/addressmap.h A src/mainboard/emulation/rdn2/mainboard.c A src/mainboard/emulation/rdn2/media.c A src/mainboard/emulation/rdn2/memlayout.ld A src/mainboard/emulation/rdn2/mmio.c 17 files changed, 883 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/79103/1 diff --git a/src/mainboard/emulation/rdn2/Kconfig b/src/mainboard/emulation/rdn2/Kconfig new file mode 100644 index 0000000..ab54d5e --- /dev/null +++ b/src/mainboard/emulation/rdn2/Kconfig @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_EMULATION_RDN2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARM64_USE_ARCH_TIMER + select BOARD_ROMSIZE_KB_32768 + select BOOTBLOCK_CUSTOM + select BOOT_DEVICE_NOT_SPI_FLASH + select DRIVERS_UART_PL011 + select FLATTENED_DEVICE_TREE + select HAVE_LINEAR_FRAMEBUFFER + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MISSING_BOARD_RESET + select PCI + select HAVE_ACPI_TABLES + select ACPI_GTDT + select ACPI_COMMON_MADT_GICC_V3 + select GENERATE_SMBIOS_TABLES + +config ECAM_MMCONF_BASE_ADDRESS + default 0x1010000000 + +config ECAM_MMCONF_BUS_NUMBER + default 256 + +config MEMLAYOUT_LD_FILE + string + default "src/mainboard/emulation/rdn2/memlayout.ld" + +config FATAL_ASSERTS + default y + +config FMDFILE + default "src/mainboard/emulation/rdn2/flash.fmd" + +config MAINBOARD_DIR + default "emulation/rdn2" + +config MAINBOARD_PART_NUMBER + default "Neoverse N2" + +config MAX_CPUS + int + default 16 + +config MAINBOARD_VENDOR + string + default "Arm" + +config DRAM_SIZE_MB + int + default 2048 + +endif # BOARD_EMULATION_RDN2 diff --git a/src/mainboard/emulation/rdn2/Kconfig.name b/src/mainboard/emulation/rdn2/Kconfig.name new file mode 100644 index 0000000..f6b14bf --- /dev/null +++ b/src/mainboard/emulation/rdn2/Kconfig.name @@ -0,0 +1,6 @@ +config BOARD_EMULATION_RDN2 + bool "Neoverse N2" + help + To execute, do: + FVP_RD_N2\models\Win64_VC2019\FVP_RD_N2 -C board.flashloader0.fname=coreboot.rom \ + -C css.trustedBootROMloader.fname=bl1.bin diff --git a/src/mainboard/emulation/rdn2/Makefile.inc b/src/mainboard/emulation/rdn2/Makefile.inc new file mode 100644 index 0000000..8727f4c --- /dev/null +++ b/src/mainboard/emulation/rdn2/Makefile.inc @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c + +romstage-y += cbmem.c + +bootblock-y += media.c +romstage-y += media.c +ramstage-y += media.c + +bootblock-y += mmio.c +romstage-y += mmio.c +ramstage-y += mmio.c + +ramstage-y += acpi.c + +bootblock-y += bootblock_custom.S + +CPPFLAGS_common += -mcmodel=large -I$(src)/mainboard/$(MAINBOARDDIR)/include +CPPFLAGS_common += -mstrict-align diff --git a/src/mainboard/emulation/rdn2/acpi.c b/src/mainboard/emulation/rdn2/acpi.c new file mode 100644 index 0000000..9fe53dc --- /dev/null +++ b/src/mainboard/emulation/rdn2/acpi.c @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <console/console.h> +#include <mainboard/addressmap.h> + + +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->ARM_boot_arch |= ACPI_FADT_ARM_PSCI_COMPLIANT; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + return current; +} + +uintptr_t platform_get_gicd_base(void) +{ + return RDN2_GIC_DIST; +} + +uintptr_t platform_get_gicr_base(void) +{ + return RDN2_GIC_REDIST; +} + +void acpi_soc_fill_gtdt(acpi_gtdt_t *gtdt) +{ + /* This value is optional if the system implements EL3 (Security + Extensions). If not provided, this field must be 0xFFFFFFFFFFFFFFFF. */ + gtdt->counter_block_address = UINT64_MAX; + gtdt->secure_el1_interrupt = SEC_EL1_TIMER_GISV; + gtdt->secure_el1_flags = RDN2_TIMER_FLAGS; + + gtdt->non_secure_el1_interrupt = NONSEC_EL1_TIMER_GSIV; + gtdt->non_secure_el1_flags = RDN2_TIMER_FLAGS; + + gtdt->virtual_timer_interrupt = VIRTUAL_TIMER_GSIV; + gtdt->virtual_timer_flags = RDN2_TIMER_FLAGS; + + gtdt->non_secure_el2_interrupt = NONSEC_EL2_TIMER_GSIV; + gtdt->non_secure_el2_flags = RDN2_TIMER_FLAGS; + /* This value is optional if the system implements EL3 + (Security Extensions). If not provided, this field must be + 0xFFFFFFFFFFFFFFF. */ + gtdt->counter_read_block_address = UINT64_MAX; +} + +unsigned long acpi_soc_gtdt_add_timers(uint32_t *count, unsigned long current) +{ + struct acpi_gtdt_timer_entry timers[2]; + + memset(timers, 0, sizeof(timers)); + (*count)++; + timers[0].frame_number = 0; + timers[0].base_address = RDN2_GT_FRAME1_CTL_BASE; + timers[0].el0_base_address = UINT64_MAX; + timers[0].timer_interrupt = RDN2_GT_FRAME1_GSIV; + timers[0].timer_flags = 0; + timers[0].virtual_timer_interrupt = 0; + timers[0].virtual_timer_flags = 0; + timers[0].common_flags = ACPI_GTDT_GT_ALWAYS_ON; + + + (*count)++; + timers[1].frame_number = 1; + timers[1].base_address = RDN2_GT_FRAME0_CTL_BASE; + timers[1].el0_base_address = UINT64_MAX; + timers[1].timer_interrupt = RDN2_GT_FRAME0_GSIV; + timers[1].timer_flags = 0; + timers[1].virtual_timer_interrupt = 0; + timers[1].virtual_timer_flags = 0; + timers[1].common_flags = ACPI_GTDT_GT_ALWAYS_ON | ACPI_GTDT_GT_IS_SECURE_TIMER; + + current = acpi_gtdt_add_timer_block(current, RDN2_GT_CTL_BASE, timers, 2); + + (*count)++; + current = acpi_gtdt_add_watchdog(current, RDN2_GWDT_REFRESH, RDN2_GWDT_CONTROL, + RDN2_GWDT_WS0_GSIV, 0); + /* Secure */ + current = acpi_gtdt_add_watchdog(current, RDN2_GWDT_REFRESH, RDN2_GWDT_CONTROL, + RDN2_GWDT_WS1_GSIV, ACPI_GTDT_WATCHDOG_SECURE); + + return current; +} + diff --git a/src/mainboard/emulation/rdn2/board_info.txt b/src/mainboard/emulation/rdn2/board_info.txt new file mode 100644 index 0000000..1338ec2 --- /dev/null +++ b/src/mainboard/emulation/rdn2/board_info.txt @@ -0,0 +1,3 @@ +Board name: Neoverse N2 +Category: emulation +Board URL: https://developer.arm.com/documentation/102337/latest/ diff --git a/src/mainboard/emulation/rdn2/bootblock.c b/src/mainboard/emulation/rdn2/bootblock.c new file mode 100644 index 0000000..1a30236 --- /dev/null +++ b/src/mainboard/emulation/rdn2/bootblock.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/mmu.h> +#include <bootblock_common.h> +#include <console/console.h> +#include <mainboard/addressmap.h> +#include <symbols.h> + +void bootblock_mainboard_init(void) +{ + mmu_init(); + + /* NOR Flash 0 */ + mmu_config_range((void *)RDN2_FLASH_BASE, (uintptr_t)RDN2_FLASH_SIZE, MA_DEV | MA_RO); + + /* device memory (till dram ?)*/ + mmu_config_range((void *)0xc000000, (uintptr_t)(_dram - 0xc000000), MA_DEV | MA_RW); + + /* Set a dummy value for DRAM. ramstage should update the mapping. */ + mmu_config_range(_dram, ((size_t) 2 * GiB) - 16*MiB, MA_MEM | MA_RW); + + mmu_config_range((void *)RDN2_DRAM2_BASE, RDN2_DRAM2_SIZE, MA_MEM | MA_RW); + + mmu_config_range(_ttb, REGION_SIZE(ttb), MA_MEM | MA_S | MA_RW); + + mmu_config_range(_stack, REGION_SIZE(stack), MA_MEM | MA_S | MA_RW); + mmu_config_range(_cbfs_mcache, REGION_SIZE(cbfs_mcache), MA_MEM | MA_S | MA_RW); + mmu_config_range(_fmap_cache, REGION_SIZE(fmap_cache), MA_MEM | MA_S | MA_RW); + mmu_config_range(_timestamp, REGION_SIZE(timestamp), MA_MEM | MA_S | MA_RW); + + mmu_config_range((void *)CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, + MA_DEV | MA_RW); + mmu_enable(); +} diff --git a/src/mainboard/emulation/rdn2/bootblock_custom.S b/src/mainboard/emulation/rdn2/bootblock_custom.S new file mode 100644 index 0000000..e8b67be --- /dev/null +++ b/src/mainboard/emulation/rdn2/bootblock_custom.S @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <arch/asm.h> + +ENTRY(_start) + + /* TF-A arg which contains a pointer to fdt */ + ldr x1, =_fdt_pointer + str x0, [x1] + + /* Setup CPU. */ + /* bl arm64_init_cpu */ + + /* ==== stack init from arm64_init_cpu ==== */ + + msr SPSel, #0 /* use SP_EL0 */ + + ldr x2, =0xdeadbeefdeadbeef + ldr x0, =_stack + ldr x1, =_estack +1: + stp x2, x2, [x0], #16 + cmp x0, x1 + bne 1b + + sub sp, x0, #16 + + /* ==== END ==== */ + + /* Jump to main() in DRAM. */ + adr x0, main + #add x0, x0, x1 + blr x0 +ENDPROC(_start) diff --git a/src/mainboard/emulation/rdn2/cbmem.c b/src/mainboard/emulation/rdn2/cbmem.c new file mode 100644 index 0000000..a8ad033 --- /dev/null +++ b/src/mainboard/emulation/rdn2/cbmem.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cbmem.h> +#include <console/console.h> +#include <ramdetect.h> +#include <symbols.h> + +uintptr_t cbmem_top_chipset(void) +{ + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); +} diff --git a/src/mainboard/emulation/rdn2/chip.h b/src/mainboard/emulation/rdn2/chip.h new file mode 100644 index 0000000..d6a0168 --- /dev/null +++ b/src/mainboard/emulation/rdn2/chip.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EMULATION_RDN2_CHIP_H +#define MAINBOARD_EMULATION_RDN2_CHIP_H + +#include <types.h> + +struct mainboard_emulation_rdn2_config { + uint32_t vgic_maintenance_interrupt; + uint32_t performance_interrupt_gsiv; +}; + +#endif diff --git a/src/mainboard/emulation/rdn2/devicetree.cb b/src/mainboard/emulation/rdn2/devicetree.cb new file mode 100644 index 0000000..79527a1 --- /dev/null +++ b/src/mainboard/emulation/rdn2/devicetree.cb @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip mainboard/emulation/rdn2 + register "vgic_maintenance_interrupt" = "0x19" + register "performance_interrupt_gsiv" = "0x17" + + device cpu_cluster 0 on ops rdn2_aarch64_cpu_ops end + + device domain 0 on ops rdn2_aarch64_pci_domain_ops + device pci 00.0 on end + end +end diff --git a/src/mainboard/emulation/rdn2/dsdt.asl b/src/mainboard/emulation/rdn2/dsdt.asl new file mode 100644 index 0000000..56d21a2 --- /dev/null +++ b/src/mainboard/emulation/rdn2/dsdt.asl @@ -0,0 +1,286 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <mainboard/addressmap.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20230621 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + + Scope (_SB) { + // UART PL011 + Device (COM0) { + Name (_HID, "ARMH0011") + Name (_UID, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, RDN2_UART_NS_BASE, 0x00001000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { RDN2_UART_NS_GSIV } + }) + Method (_STA) { + Return (0xF) + } + } + + Device (VR00) { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + RDN2_AHCI_BASE, // Address Base + 0x00010000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + RDN2_AHCI_INT, + } + }) + } + + Device (VR01) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + RDN2_VNET_BASE, // Address Base + 0x00010000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + RDN2_VNET_INT, + } + }) + } + + + + Device (\_SB.DMA0) + { + Name (_HID, "ARMH0330") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_STA, 0x0F) // _STA: Status + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0x0000000000000001, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000000000002, // Length + ,, _Y02, AddressRangeMemory, TypeStatic) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x000001ED, + 0x000001EE, + 0x000001EF, + 0x000001F0, + 0x000001F1, + 0x000001F2, + 0x000001F3, + 0x000001F4, + 0x000001F5, + } + }) + CreateQWordField (RBUF, \_SB.DMA0._CRS._Y02._MIN, MIN2) // _MIN: Minimum Base Address + CreateQWordField (RBUF, \_SB.DMA0._CRS._Y02._MAX, MAX2) // _MAX: Maximum Base Address + CreateQWordField (RBUF, \_SB.DMA0._CRS._Y02._LEN, LEN2) // _LEN: Length + MIN2 = 0x0000001090000000 + MAX2 = (MIN2 + 0xFFFF) + LEN2 = 0x00010000 + Return (RBUF) /* \_SB_.DMA0._CRS.RBUF */ + } + } + + Device (\_SB.DMA1) + { + Name (_HID, "ARMH0330") // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_STA, 0x0F) // _STA: Status + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0x0000000000000001, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000000000002, // Length + ,, _Y03, AddressRangeMemory, TypeStatic) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x000001F7, + 0x000001F8, + 0x000001F9, + 0x000001FA, + 0x000001FB, + 0x000001FC, + 0x000001FD, + 0x000001FE, + 0x000001FF, + } + }) + CreateQWordField (RBUF, \_SB.DMA1._CRS._Y03._MIN, MIN2) // _MIN: Minimum Base Address + CreateQWordField (RBUF, \_SB.DMA1._CRS._Y03._MAX, MAX2) // _MAX: Maximum Base Address + CreateQWordField (RBUF, \_SB.DMA1._CRS._Y03._LEN, LEN2) // _LEN: Length + MIN2 = 0x00000010B0000000 + MAX2 = (MIN2 + 0xFFFF) + LEN2 = 0x00010000 + Return (RBUF) /* \_SB_.DMA1._CRS.RBUF */ + } + } + + Device (\_SB.GPI0) { + Name (_HID, "ARMH0061") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + RDN2_GPIO0, // Address Base + 0x00010000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + RDN2_GPIO0_INT, + } + }) + Name (_AEI, ResourceTemplate () // _AEI: ACPI Event Interrupts + { + GpioInt (Level, ActiveHigh, Exclusive, PullDown, 0x0000, + "\\_SB.GPI0", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0000 + } + }) + Method (_L00, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + Debug = "GPIO0 Pin0 Toggled" + INC0 = One + } + + OperationRegion (GIO0, SystemMemory, RDN2_GPIO0, 0x00010000) + Field (GIO0, ByteAcc, NoLock, Preserve) + { + Offset (0x41C), + INC0, 8 + } + } + + Device (\_SB.GED0) + { + Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + RDN2_DUAL_TIMER_INT, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + OperationRegion (DTIM, SystemMemory, RDN2_DUAL_TIMER, 0x00010000) + Field (DTIM, DWordAcc, NoLock, Preserve) + { + Offset (0x0C), + T1IC, 32 + } + + Method (_EVT, 1, Serialized) // _EVT: Event + { + Switch (ToInteger (Arg0)) + { + Case (0x01E6) + { + T1IC = One + } + + } + } + } + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge + Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge + Name (_SEG, Zero) // PCI Segment Group number + Name (_BBN, Zero) // PCI Base Bus Number + Name (_UID, "PCI0") + Name (_CCA, One) // Initially mark the PCI coherent (for JunoR1) + + Method (_STA) { + Return (0xF) + } + + Method (_CBA, 0, NotSerialized) { + return (RDN2_PCIE_ECAM_BASE) + } + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + RDN2_PCIE_MMIO_BASE, // Min Base Address + RDN2_PCIE_MMIO_LIMIT, // Max Base Address + 0, // Translate + RDN2_PCIE_MMIO_SIZE // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + RDN2_PCIE_MMIO_HIGH_BASE, // Min Base Address + RDN2_PCIE_MMIO_HIGH_LIMIT, // Max Base Address + 0, // Translate + RDN2_PCIE_MMIO_HIGH_SIZE // Length + ) + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0x007FFFFF, // Range Maximum + 0x77800000, // Translation Offset + 0x00800000, // Length + ,, , TypeTranslation, DenseTranslation) + }) // Name(RBUF) + + Return (RBUF) + } // Method(_CRS) + + + } + } // Scope (_SB) +} diff --git a/src/mainboard/emulation/rdn2/flash.fmd b/src/mainboard/emulation/rdn2/flash.fmd new file mode 100644 index 0000000..cab66ed --- /dev/null +++ b/src/mainboard/emulation/rdn2/flash.fmd @@ -0,0 +1,23 @@ +# +# custom fmap which takes the additional TF-A region into account +# +# +-------------+ <-- 0x0 +# | TF-A | +# +-------------+ <-- BIOS_BASE +# | bootblock | +# +-------------+ <-- BIOS_BASE + 128K +# | FMAP | +# +-------------+ <-- BIOS_BASE + 128K + FMAP_SIZE +# | CBFS | +# +-------------+ <-- ROM_SIZE +# + +FLASH@0x8000000 CONFIG_ROM_SIZE { + + BIOS@0x0 CONFIG_ROM_SIZE { + + BOOTBLOCK 128K + FMAP@0x20000 0x200 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/emulation/rdn2/include/mainboard/addressmap.h b/src/mainboard/emulation/rdn2/include/mainboard/addressmap.h new file mode 100644 index 0000000..592565e --- /dev/null +++ b/src/mainboard/emulation/rdn2/include/mainboard/addressmap.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Memory map for Neoverse N2 + * See Technical Reference: Table 5-2: FVP board peripherals + */ + +#define RDN2_FLASH_BASE 0x8000000 +#define RDN2_FLASH_SIZE (64 * MiB) + +/* Actual DRAM size should be probed */ +#define RDN2_DRAM_BASE 0x80000000 +#define RDN2_DRAM_SIZE (2 * GiB) + +#define RDN2_SECMEM_BASE 0xff000000 +#define RDN2_SECMEM_SIZE (16 * MiB) + +#define RDN2_DRAM2_BASE 0x8080000000 +#define RDN2_DRAM2_SIZE (6UL * GiB) + +#define RDN2_GIC_DIST 0x30000000 +#define RDN2_GIC_REDIST 0x301C0000 + +#define SEC_EL1_TIMER_GISV 29 +#define NONSEC_EL1_TIMER_GSIV 30 +#define VIRTUAL_TIMER_GSIV 27 +#define NONSEC_EL2_TIMER_GSIV 26 + +#define RDN2_TIMER_FLAGS (ACPI_GTDT_INTERRUPT_POLARITY) +#define RDN2_GT_CTL_BASE 0x2A810000 +#define RDN2_GT_FRAME0_CTL_BASE 0x2A820000 +#define RDN2_GT_FRAME0_EL0_BASE -1 +#define RDN2_GT_FRAME0_GSIV 0x6c + +#define RDN2_GT_FRAME1_CTL_BASE 0x2A830000 +#define RDN2_GT_FRAME1_EL0_BASE -1 +#define RDN2_GT_FRAME1_GSIV 0x6d + +#define RDN2_GWDT_REFRESH 0x2a450000 +#define RDN2_GWDT_CONTROL 0x2a440000 +#define RDN2_GWDT_WS0_GSIV 0x6e +#define RDN2_GWDT_WS1_GSIV 0x6f + +#define RDN2_UART_CLK_HZ 7372800 +#define RDN2_UART_NS_BASE 0x2a400000 +#define RDN2_UART_NS_GSIV 112 +#define RDN2_SECURE_UART_BASE 0x2a410000 +#define RDN2_SECURE_UART_GSIV 81 + +#define RDN2_RTC_BASE 0x0C170000 +#define RDN2_RTC1_BASE 0x0C180000 +#define RDN2_GPIO_BASE 0x0c1d0000 +#define RDN2_GPIO1_BASE 0x0c1e0000 + +#define RDN2_SMMU_BASE 0x40000000 + +/* Virtio block device */ +#define RDN2_AHCI_BASE 0x0C130000 +#define RDN2_AHCI_INT 458 + +/* Virtio net */ +#define RDN2_VNET_BASE 0x0C150000 +#define RDN2_VNET_INT 460 + +/* Arm Dual-Timer Module */ +#define RDN2_DUAL_TIMER 0x0C110000 +#define RDN2_DUAL_TIMER_INT 486 + +#define RDN2_GPIO0 0x0C1D0000 +#define RDN2_GPIO0_INT 392 + +#define RDN2_EHCI_BASE 0x60110000 + +#define RDN2_PCIE_MMIO_BASE 0x60000000 +#define RDN2_PCIE_MMIO_LIMIT 0x7fffffff +#define RDN2_PCIE_MMIO_SIZE 0x20000000 +#define RDN2_PCIE_ECAM_BASE 0x1010000000 +#define RDN2_PCIE_ECAM_LIMIT 0x101FFFFFFF +#define RDN2_PCIE_ECAM_SIZE 0x10000000 +#define RDN2_PCIE_MMIO_HIGH_BASE 0x4000000000 +#define RDN2_PCIE_MMIO_HIGH_LIMIT 0x807fffffff +#define RDN2_PCIE_MMIO_HIGH_SIZE 0x4080000000 diff --git a/src/mainboard/emulation/rdn2/mainboard.c b/src/mainboard/emulation/rdn2/mainboard.c new file mode 100644 index 0000000..905fe38 --- /dev/null +++ b/src/mainboard/emulation/rdn2/mainboard.c @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "chip.h" +#include <acpi/acpigen.h> +#include <arch/mmu.h> +#include <bootmem.h> +#include <cbfs.h> +#include <device/device.h> +#include <device_tree.h> +#include <mainboard/addressmap.h> +#include <ramdetect.h> +#include <stdint.h> +#include <symbols.h> + +static size_t ram_size(void) +{ + return (size_t)cbmem_top() - (uintptr_t)_dram; +} + +static size_t ram2_size(void) +{ + return (size_t)probe_ramsize((uintptr_t)RDN2_DRAM2_BASE, RDN2_DRAM2_SIZE) * MiB; +} + +static void mainboard_init(void *chip_info) +{ + mmu_config_range(_dram, ram_size(), MA_MEM | MA_RW); + mmu_config_range((void *)RDN2_DRAM2_BASE, ram2_size(), MA_MEM | MA_RW); + +} + +DECLARE_REGION(fdt_pointer) +void smbios_cpu_get_core_counts(u16 *core_count, u16 *thread_count) +{ + *core_count = 0; + struct device *dev = NULL; + while ((dev = dev_find_path(dev, DEVICE_PATH_GICC_V3))) + *core_count += 1; + + *thread_count = 1; +} + +static void rdn2_aarch64_init(struct device *dev) +{ + struct memory_info *mem_info; + + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) + return; + + memset(mem_info, 0, sizeof(*mem_info)); + + mem_info->ecc_type = MEMORY_ARRAY_ECC_UNKNOWN; + mem_info->max_capacity_mib = 0x800000; + mem_info->number_of_devices = mem_info->dimm_cnt = 1; + + mem_info->dimm[0].dimm_size = (ram_size() + ram2_size()) / MiB; + mem_info->dimm[0].ddr_type = MEMORY_TYPE_DRAM; + mem_info->dimm[0].ddr_frequency = 0; + mem_info->dimm[0].channel_num = mem_info->dimm[0].dimm_num = 0; + mem_info->dimm[0].bank_locator = 0; + + mem_info->dimm[0].bus_width = 0x03; // 64-bit, no parity + mem_info->dimm[0].vdd_voltage = 0; + mem_info->dimm[0].max_speed_mts = mem_info->dimm[0].configured_speed_mts = 0; +} + +static unsigned long mb_write_acpi_tables(const struct device *dev, unsigned long current, + acpi_rsdp_t *rsdp) +{ + printk(BIOS_DEBUG, "ACPI: * DBG2\n"); + return acpi_pl011_write_dbg2_uart(rsdp, current, RDN2_UART_NS_BASE, "\\_SB.COM0"); +} + + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = rdn2_aarch64_init; + dev->ops->write_acpi_tables = mb_write_acpi_tables; +} + + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; + +struct chip_operations mainboard_emulation_rdn2_ops = { }; + +static void rdn2_aarch64_domain_read_resources(struct device *dev) +{ + struct resource *res; + int index = 0; + + /* Initialize the system-wide I/O space constraints. */ + res = new_resource(dev, index++); + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; + + /* Initialize the system-wide memory resources constraints. */ + res = new_resource(dev, index++); + res->base = RDN2_PCIE_MMIO_BASE; + res->limit = RDN2_PCIE_MMIO_LIMIT; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + + res = new_resource(dev, index++); + res->base = RDN2_PCIE_MMIO_HIGH_BASE; + res->limit = RDN2_PCIE_MMIO_HIGH_LIMIT; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + + mmio_range(dev, index++, RDN2_PCIE_ECAM_BASE, RDN2_PCIE_ECAM_SIZE); + + ram_range(dev, index++, (uintptr_t)_dram, ram_size()); + reserved_ram_range(dev, index++, (uintptr_t)RDN2_SECMEM_BASE, RDN2_SECMEM_SIZE); + + ram_range(dev, index++, (uintptr_t)RDN2_DRAM2_BASE, ram2_size()); + + mmio_range(dev, index++, RDN2_FLASH_BASE, RDN2_FLASH_SIZE); +} + +struct device_operations rdn2_aarch64_pci_domain_ops = { + .read_resources = rdn2_aarch64_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_host_bridge_scan_bus, +}; + +static void rdn2_fill_cpu_ssdt(const struct device *dev) +{ + acpigen_write_processor_device(dev->path.gicc_v3.mpidr); + acpigen_write_processor_device_end(); +} + +struct device_operations rdn2_cpu_ops = { + .acpi_fill_ssdt = rdn2_fill_cpu_ssdt, +}; + +static void rdn2_aarch64_scan_bus(struct device *dev) +{ + if (!dev->link_list) + add_more_links(dev, 1); + + u16 i = 0; + struct mainboard_emulation_rdn2_config *config = dev->chip_info; + + for (i = 0; i < 16; i++) { + printk(BIOS_DEBUG, "Allocating CPU %d\n", i); + struct device_path devpath = { .type = DEVICE_PATH_GICC_V3, + .gicc_v3 = { .mpidr = i << 16, + .vgic_mi = config->vgic_maintenance_interrupt, + .pi_gsiv = config->performance_interrupt_gsiv, }, + + }; + struct device *cpu = alloc_dev(dev->link_list, &devpath); + assert(cpu); + cpu->ops = &rdn2_cpu_ops; + + } + +} + +struct device_operations rdn2_aarch64_cpu_ops = { + .scan_bus = rdn2_aarch64_scan_bus, +}; diff --git a/src/mainboard/emulation/rdn2/media.c b/src/mainboard/emulation/rdn2/media.c new file mode 100644 index 0000000..cf6ab06 --- /dev/null +++ b/src/mainboard/emulation/rdn2/media.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <boot_device.h> +#include <mainboard/addressmap.h> + +/* Maps directly to NOR flash up to ROM size. */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT((void *)RDN2_FLASH_BASE, RDN2_FLASH_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/emulation/rdn2/memlayout.ld b/src/mainboard/emulation/rdn2/memlayout.ld new file mode 100644 index 0000000..16a6fb7 --- /dev/null +++ b/src/mainboard/emulation/rdn2/memlayout.ld @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <memlayout.h> +#include <arch/header.ld> + +/* + * Memory map for Neoverse N2 + * See Technical Reference: Table 5-2: FVP board peripherals + */ +SECTIONS +{ + REGION(flash, 0x8000000, CONFIG_ROM_SIZE, 8) + + DRAM_START(0x80000000) + BOOTBLOCK(0xe0000000, 64K) + STACK(0xe0010000, 64K) + CBFS_MCACHE(0xe0020000, 8K) + FMAP_CACHE(0xe0022000 , 4K) + TIMESTAMP(0xe0023000, 4K) + ROMSTAGE(0xe0024000, 128K) + TTB(0xe0060000, 128K) + RAMSTAGE(0xe00a0000, 16M) + REGION(fdt_pointer, 0xe10a0000, ARCH_POINTER_ALIGN_SIZE, ARCH_POINTER_ALIGN_SIZE) + + POSTRAM_CBFS_CACHE(0xe11f0000, 1M) +} diff --git a/src/mainboard/emulation/rdn2/mmio.c b/src/mainboard/emulation/rdn2/mmio.c new file mode 100644 index 0000000..1b87205 --- /dev/null +++ b/src/mainboard/emulation/rdn2/mmio.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/uart.h> +#include <mainboard/addressmap.h> + +uintptr_t uart_platform_base(unsigned int idx) +{ + return RDN2_UART_NS_BASE; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17908d3ce773d4a88924bafb1d0e9e2a043c7fbc Gerrit-Change-Number: 79103 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: acpi: Add IO Remapping Table structures
by Naresh Solanki (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Arthur Heymans, Cliff Huang, Lance Zhao, Martin L Roth, Patrick Rudolph, Paul Menzel, Tim Wawrzynczak. Naresh Solanki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77884?usp=email ) Change subject: acpi: Add IO Remapping Table structures ...................................................................... Patch Set 6: (1 comment) File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/77884/comment/06daedde_4e3ff8ce : PS4, Line 1527: /* IORT - IO Remapping Table */ > Acknowledged Done -- To view, visit https://review.coreboot.org/c/coreboot/+/77884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e8e3323caa714a56882939914cac510bf95d30b Gerrit-Change-Number: 77884 Gerrit-PatchSet: 6 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 16 Nov 2023 20:44:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: acpi: Add IO Remapping Table structures
by Naresh Solanki (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Arthur Heymans, Cliff Huang, Lance Zhao, Martin L Roth, Patrick Rudolph, Paul Menzel, Tim Wawrzynczak. Hello Arthur Heymans, Cliff Huang, Lance Zhao, Martin L Roth, Patrick Rudolph, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77884?usp=email to look at the new patch set (#6). Change subject: acpi: Add IO Remapping Table structures ...................................................................... acpi: Add IO Remapping Table structures Input Output Remapping Table (IORT) represents the IO topology of an Arm based system. IORT subtable revision: IORT - Type: 0 - ITS Group rev 0 IORT - Type: 1 - Named componenet rev 4 IORT - Type: 2 - Root complex rev 1 IORT - Type: 4 - SMMUv3 rev 2 Change-Id: I4e8e3323caa714a56882939914cac510bf95d30b Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/acpi/Kconfig M src/acpi/acpi.c M src/include/acpi/acpi.h A src/include/acpi/acpi_iort.h 4 files changed, 137 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/77884/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/77884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e8e3323caa714a56882939914cac510bf95d30b Gerrit-Change-Number: 77884 Gerrit-PatchSet: 6 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[main]: acpi/acpi.h: Add IO Remapping Table structures
by Naresh Solanki (Code Review) 16 Nov '23

16 Nov '23

Attention is currently required from: Arthur Heymans, Cliff Huang, Lance Zhao, Martin L Roth, Patrick Rudolph, Paul Menzel, Tim Wawrzynczak. Hello Arthur Heymans, Cliff Huang, Lance Zhao, Martin L Roth, Patrick Rudolph, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77884?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+2 by Martin L Roth, Verified+1 by build bot (Jenkins) Change subject: acpi/acpi.h: Add IO Remapping Table structures ...................................................................... acpi/acpi.h: Add IO Remapping Table structures Input Output Remapping Table (IORT) represents the IO topology of an Arm based system. IORT subtable revision: IORT - Type: 0 - ITS Group rev 0 IORT - Type: 1 - Named componenet rev 4 IORT - Type: 2 - Root complex rev 1 IORT - Type: 4 - SMMUv3 rev 2 Change-Id: I4e8e3323caa714a56882939914cac510bf95d30b Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/acpi/Kconfig M src/acpi/acpi.c M src/include/acpi/acpi.h A src/include/acpi/acpi_iort.h 4 files changed, 137 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/77884/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/77884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e8e3323caa714a56882939914cac510bf95d30b Gerrit-Change-Number: 77884 Gerrit-PatchSet: 5 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: Fix configuration for TPM in Kconfig
by Shelley Chen (Code Review) 16 Nov '23

16 Nov '23

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79102?usp=email ) Change subject: Fix configuration for TPM in Kconfig ...................................................................... Fix configuration for TPM in Kconfig Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/79102/1 diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 9de2a35..e91b9fe 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -76,7 +76,7 @@ config DRIVER_TPM_I2C_BUS hex - default 0x1 if BOARD_GOOGLE_BROX + default 0x4 if BOARD_GOOGLE_BROX config DRIVER_TPM_I2C_ADDR hex @@ -87,7 +87,7 @@ config TPM_TIS_ACPI_INTERRUPT int - default 13 + default 33 # GPE0_DW1_01 (GPP_D01) config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -- To view, visit https://review.coreboot.org/c/coreboot/+/79102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5 Gerrit-Change-Number: 79102 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: Set ic2 configs in device tree
by Shelley Chen (Code Review) 16 Nov '23

16 Nov '23

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79101?usp=email ) Change subject: Set ic2 configs in device tree ...................................................................... Set ic2 configs in device tree Change-Id: I10a7463effd85aec4551385963197bc1021319fe Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb 1 file changed, 11 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/79101/1 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index 2b73ad2..1a5a602 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -76,13 +76,12 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| GSPI1 | Fingerprint MCU | - #| I2C0 | Audio and WFC | - #| I2C1 | cr50 TPM. Early init is | + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C2 | ISH EC | + #| I2C4 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | - #| I2C2 | SAR0 | - #| I2C3 | Touchscreen | #| I2C5 | Trackpad | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -167,6 +166,13 @@ device generic 0 on end end end + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D1_IRQ)" + device i2c 50 on end + end + end device ref i2c3 on end device ref heci1 on end device ref sata on end -- To view, visit https://review.coreboot.org/c/coreboot/+/79101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10a7463effd85aec4551385963197bc1021319fe Gerrit-Change-Number: 79101 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: mb/google/brox: Use Ti50 config
by Shelley Chen (Code Review) 16 Nov '23

16 Nov '23

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79100?usp=email ) Change subject: mb/google/brox: Use Ti50 config ...................................................................... mb/google/brox: Use Ti50 config Brox is using Ti50, so make sure that we set the right config for that. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: If4a16448eebc028b2989c1de150b9e0f9067ee92 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/Kconfig M src/mainboard/google/brox/chromeos.fmd 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/79100/1 diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index dcd1705..9de2a35 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -48,7 +48,7 @@ select SOC_INTEL_RAPTORLAKE select SOC_INTEL_ALDERLAKE_PCH_P select SYSTEM_TYPE_LAPTOP - select TPM_GOOGLE_CR50 + select TPM_GOOGLE_TI50 config BOARD_GOOGLE_BROX select BOARD_GOOGLE_BASEBOARD_BROX diff --git a/src/mainboard/google/brox/chromeos.fmd b/src/mainboard/google/brox/chromeos.fmd index 65ceba7..fffb77e 100644 --- a/src/mainboard/google/brox/chromeos.fmd +++ b/src/mainboard/google/brox/chromeos.fmd @@ -47,6 +47,7 @@ # memory protected range specification. WP_RO 8M { RO_VPD(PRESERVE) 16K + RO_GSCVD 8K RO_SECTION { FMAP 2K RO_FRID 64 -- To view, visit https://review.coreboot.org/c/coreboot/+/79100?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If4a16448eebc028b2989c1de150b9e0f9067ee92 Gerrit-Change-Number: 79100 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2023