coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: acpi: Add PPTT support
by Angel Pons (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Arthur Heymans, Cliff Huang, David Milosevic, Lance Zhao, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78071?usp=email ) Change subject: acpi: Add PPTT support ...................................................................... Patch Set 21: (6 comments) File src/acpi/acpi_pptt.c: https://review.coreboot.org/c/coreboot/+/78071/comment/66093488_05c550b0 : PS17, Line 12: typedef > IMO, it's highly subjective. Upstream, code is more often read than worked on. […] I would prefer *not* to use typedefs for structs either, as they hide the fact that the underlying type is a struct. Plus, if a function's signature is too long, you can spread the parameter list of a function over several lines. If you have too many parameters, consider passing a pointer to a struct instead. https://review.coreboot.org/c/coreboot/+/78071/comment/35c482c2_cb4ee13d : PS17, Line 131: cache_reference_t cache_refs[CONFIG_ACPI_PPTT_MAX_CACHES]; > As promised, here is the platform code https://review.coreboot. […] Note: I may have mixed up "caches shared by several processors" and "several processors with the same kind of cache". The grouping approach is for shared caches only. If I understand correctly, the problem here is that cache information can be the same across some but not all processors (e.g. big.LITTLE), and such redundancy should preferrably be avoided. Looks like https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/05_ACPI_Software_Programming_… says that the "processor hierarchy node structure (Type 0) [...] can be used to describe a single processor or a group". Looks like the code doesn't make use of this yet? Processors with a shared cache must be grouped to accurately reflect reality. This grouping could already be done in `acpi_get_pptt_topology()`, i.e. the data passed to the PPTT serializer (this code). There's a few things to keep in mind: - The processor info needs to match that of MADT, not sure if MADT accounts for processor groups. - It is assumed that whoever defines `acpi_get_pptt_topology()` can figure out how to group the processors better than common code (e.g. soc/rockchip/rk3399 knows the chip has 2x Cortex-A72 and 4x Cortex-A53, common code doesn't). [It was at this point that I realized I had mixed up both types of caches.] As for private resources, they need to appear in every individual type 0 (processor) entry. Assuming SoC code is sane, the PPTT serializer could just compare pointers to check if they're the same structure. This works as long as the data structures returned by `acpi_get_pptt_topology()` are not modified at all during their serialization into ACPI PPTT. If one processor has L1->L2->0 and another processor only has L2->0 (where 0 means NULL and L2 is the exact same data), one could try to reuse parts of the first processor's L1->L2-0 data for the second processor. This can also be done by comparing pointers and will work provided that `acpi_get_pptt_topology()` also reuses said pointers. File src/acpi/acpi_pptt.c: https://review.coreboot.org/c/coreboot/+/78071/comment/a5260444_a09284c4 : PS21, Line 148: cpu_node->resources[cpu_node->n_resources++] = new_pptt_cache(current, it->cache, cache_list); In https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/05_ACPI_Software_Programming_… figure 5.15, the type 1 (cache) entries being placed above the type 0 (processor) entries. Not sure if it matters, but writing down all the type 1 (cache) entries before the type 0 (processor) entries seems to make things like reusing entries easier to implement. File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/78071/comment/d7b800c7_2a1c40dc : PS21, Line 1405: PPTT_PROCESSOR_FLAG_* Macros do not exist https://review.coreboot.org/c/coreboot/+/78071/comment/839ae3b0_bfa84f21 : PS21, Line 1416: PPTT_CACHE_FLAG_* Macros do not exist https://review.coreboot.org/c/coreboot/+/78071/comment/369ac393_5c02b8f5 : PS21, Line 1448: u32 size_valid : 1; : u32 n_sets_valid : 1; : u32 associativity_valid : 1; : u32 alloc_type_valid : 1; : u32 cache_type_valid : 1; : u32 write_policy_valid : 1; : u32 line_size_valid : 1; : u32 cache_id_valid : 1; : u32 reserved : 24; Are bitfields portable? Or can they break depending on endianness? -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 21 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 12:21:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: libpayload: Move ttb_buffer to a standalone section
by Yi Chou (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Julius Werner, Yi Chou, Yu-Ping Wu. Hello Julius Werner, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79078?usp=email to look at the new patch set (#5). Change subject: libpayload: Move ttb_buffer to a standalone section ...................................................................... libpayload: Move ttb_buffer to a standalone section When cleaning the sensitive data in the memory, we will want to prevent zero out the content of tbb_buffer. Move the ttb_buffer to a standalone section will simplify the problem. BUG=b:248610274 TEST=emerge-cherry libpayload BRANCH=none Change-Id: I610276cbe30552263d791860c15e5ad9a201c744 Signed-off-by: Yi Chou <yich(a)google.com> --- M payloads/libpayload/arch/arm64/mmu.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/79078/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/79078?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I610276cbe30552263d791860c15e5ad9a201c744 Gerrit-Change-Number: 79078 Gerrit-PatchSet: 5 Gerrit-Owner: Yi Chou <yich(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yi Chou <yich(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: libpayload: Move ttb_buffer to a standalone section
by Yi Chou (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Julius Werner, Yi Chou, Yu-Ping Wu. Hello Julius Werner, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79078?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: libpayload: Move ttb_buffer to a standalone section ...................................................................... libpayload: Move ttb_buffer to a standalone section When cleaning the sensitive data in the memory, we will want to prevent zero out the content of tbb_buffer. Move the ttb_buffer to a standalone section will simplify the problem. BUG=b:248610274 TEST=emerge-cherry libpayload BRANCH=none Change-Id: I610276cbe30552263d791860c15e5ad9a201c744 Signed-off-by: Yi Chou <yich(a)google.com> --- M payloads/libpayload/arch/arm64/mmu.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/79078/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/79078?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I610276cbe30552263d791860c15e5ad9a201c744 Gerrit-Change-Number: 79078 Gerrit-PatchSet: 4 Gerrit-Owner: Yi Chou <yich(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yi Chou <yich(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: libpayload: Move ttb_buffer to a standalone section
by Yi Chou (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Julius Werner, Yu-Ping Wu. Hello Julius Werner, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79078?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: libpayload: Move ttb_buffer to a standalone section ...................................................................... libpayload: Move ttb_buffer to a standalone section When cleaning the sensitive data in the memory, we will want to prevent zero out the content of tbb_buffer. Move the ttb_buffer to a standalone section will simplify the problem. BUG=b:248610274 TEST=emerge-cherry libpayload BRANCH=none Change-Id: I610276cbe30552263d791860c15e5ad9a201c744 Signed-off-by: Yi Chou <yich(a)google.com> --- M payloads/libpayload/arch/arm64/mmu.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/79078/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79078?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I610276cbe30552263d791860c15e5ad9a201c744 Gerrit-Change-Number: 79078 Gerrit-PatchSet: 2 Gerrit-Owner: Yi Chou <yich(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: libpayload: Move ttb_buffer to a standalone section
by Yi Chou (Code Review) 17 Nov '23

17 Nov '23

Yi Chou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79078?usp=email ) Change subject: libpayload: Move ttb_buffer to a standalone section ...................................................................... libpayload: Move ttb_buffer to a standalone section When cleaning the sensitive data in the memory, we will want to prevent zero out the content of tbb_buffer. Move the ttb_buffer to a standalone section will simplify the problem. BUG=b:248610274 TEST=emerge-cherry libpayload BRANCH=none Change-Id: I610276cbe30552263d791860c15e5ad9a201c744 Signed-off-by: Yi Chou <yich(a)google.com> --- M payloads/libpayload/arch/arm64/mmu.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/79078/1 diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index 4c8f8c1..8823cc0 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -41,7 +41,7 @@ static uint64_t *xlat_addr; static int free_idx; -static uint8_t ttb_buffer[TTB_DEFAULT_SIZE] __attribute__((aligned(GRANULE_SIZE))); +static uint8_t ttb_buffer[TTB_DEFAULT_SIZE] __attribute__((aligned(GRANULE_SIZE),section(".ttb_buffer"))); static const char * const tag_to_string[] = { [TYPE_NORMAL_MEM] = "normal", -- To view, visit https://review.coreboot.org/c/coreboot/+/79078?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I610276cbe30552263d791860c15e5ad9a201c744 Gerrit-Change-Number: 79078 Gerrit-PatchSet: 1 Gerrit-Owner: Yi Chou <yich(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/geralt: Remove unnecessary delay for MIPI panel
by Paul Menzel (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79109?usp=email ) Change subject: mb/google/geralt: Remove unnecessary delay for MIPI panel ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79109?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92bca5ec8269f4bad4dfab4ee193cdb5665de233 Gerrit-Change-Number: 79109 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-CC: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 11:47:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/geralt: Remove unnecessary delay for MIPI panel
by Yidi Lin (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79109?usp=email ) Change subject: mb/google/geralt: Remove unnecessary delay for MIPI panel ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79109/comment/5a866475_2638f825 : PS2, Line 7: mb/google/geralt: Move 200ms delay to eDP path > Remove unnecessary delay for MIPI panel Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79109?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92bca5ec8269f4bad4dfab4ee193cdb5665de233 Gerrit-Change-Number: 79109 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-CC: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 11:43:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/geralt: Remove unnecessary delay for MIPI panel
by Yidi Lin (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin. Hello Hung-Te Lin, Ruihai Zhou, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79109?usp=email to look at the new patch set (#3). Change subject: mb/google/geralt: Remove unnecessary delay for MIPI panel ...................................................................... mb/google/geralt: Remove unnecessary delay for MIPI panel According to eDP panel datasheet[1], the eDP panel needs 0 <= x <=200ms delay after VDD powering on. The MIPI panel[2] does not need this delay. Move this delay to eDP path. [1] NE135FBM-N41 V8.0 Product Spec_P2 20191025.pdf [2] B5 TV110C9M-LL0 Product Specification Rev.P0 BRANCH=none BUG=none TEST=check FW screen TEST=check timestamp Before: 60:device initialization 696,422 (1) 15:starting LZMA decompress (ignore for x86) 696,587 (165) 16:finished LZMA decompress (ignore for x86) 696,675 (88) 17:starting LZ4 decompress (ignore for x86) 1,340,226 (643,551) After: 60:device initialization 724,259 (1) 15:starting LZMA decompress (ignore for x86) 724,425 (166) 16:finished LZMA decompress (ignore for x86) 724,512 (87) 17:starting LZ4 decompress (ignore for x86) 1,168,176 (443,664) Change-Id: I92bca5ec8269f4bad4dfab4ee193cdb5665de233 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/mainboard/google/geralt/display.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/79109/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79109?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92bca5ec8269f4bad4dfab4ee193cdb5665de233 Gerrit-Change-Number: 79109 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-CC: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: arch/arm64: Add EL1/EL2/EL3 support for arm64
by Angel Pons (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Milosevic, Julius Werner, Lean Sheng Tan, Martin L Roth, Maximilian Brune, Nico Huber. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74798?usp=email ) Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64 ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74798/comment/d7b3cbf5_18ef7fbe : PS5, Line 11: one boots into TF-A first and drops into EL2 for coreboot afterwards. > I mean... […] I agree with Julius, this is not the way forward. Although I don't really know stuff about ARM, I still feel that I should express my thoughts and feelings on the matter. ``` -- Starting with a rant is useful to vent excess emotions procedure Rant is begin ``` This approach feels like making coreboot bend over backwards just so that the SoC vendor can sell their chips as "runs open source firmware". - "runs" ---> happens to work, but please don't look at the code - "open source" ---> may contain trace amounts of coreboot code - "firmware" ---> firmness is side-effect of old coreboot branch ``` end Rant; ``` On a more serious note, trying to convince SoC vendors to switch from TF-A to coreboot while having to strip down coreboot of its guts so that it works with the SoC vendor's TF-A blobs seems downright counterproductive to me. The end result is even worse than blobboot (coreboot, but with too many blobs), it's pretty much shimboot (blobs, but glued together with a bit of coreboot code). This situation reminds me of some awful thing Intel once proposed: FSP-at-Reset. And I'm pretty sure nobody liked that. -- To view, visit https://review.coreboot.org/c/coreboot/+/74798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e Gerrit-Change-Number: 74798 Gerrit-PatchSet: 9 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 11:20:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/geralt: Move 200ms delay to eDP path
by Yu-Ping Wu (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79109?usp=email ) The change is no longer submittable: All-Comments-Resolved and Code-Review are unsatisfied now. Change subject: mb/google/geralt: Move 200ms delay to eDP path ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79109/comment/fa8366c6_2481625a : PS2, Line 7: mb/google/geralt: Move 200ms delay to eDP path Remove unnecessary delay for MIPI panel -- To view, visit https://review.coreboot.org/c/coreboot/+/79109?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92bca5ec8269f4bad4dfab4ee193cdb5665de233 Gerrit-Change-Number: 79109 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-CC: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 11:04:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2023