coreboot-gerrit November 2023

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[XS] Change in coreboot[main]: nb/intel/sandybridge/pcie: drop unneeded HAVE_ACPI_TABLES guards
by Felix Held (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Angel Pons. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79116?usp=email ) Change subject: nb/intel/sandybridge/pcie: drop unneeded HAVE_ACPI_TABLES guards ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: not tested on hardware yet -- To view, visit https://review.coreboot.org/c/coreboot/+/79116?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e8c8b3e3672d1589a5910753986e4033d2ce766 Gerrit-Change-Number: 79116 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 15:56:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: nb/intel/sandybridge: assign PCIe root port ops in chipset devicetree
by Felix Held (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Angel Pons. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79115?usp=email ) Change subject: nb/intel/sandybridge: assign PCIe root port ops in chipset devicetree ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: not tested on hardware yet -- To view, visit https://review.coreboot.org/c/coreboot/+/79115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I357aa0b27fcc73814f60d0aa5b5141add8917825 Gerrit-Change-Number: 79115 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 15:56:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: nb/intel/sandybridge: assign gma ops in chipset devicetree
by Felix Held (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Angel Pons. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79114?usp=email ) Change subject: nb/intel/sandybridge: assign gma ops in chipset devicetree ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: not tested on hardware yet -- To view, visit https://review.coreboot.org/c/coreboot/+/79114?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I20e387e626e19dc441aceda18451186d1e86cd5f Gerrit-Change-Number: 79114 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 15:56:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: nb/intel/sandybridge: assign host bridge ops in chipset devicetree
by Felix Held (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Angel Pons. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79113?usp=email ) Change subject: nb/intel/sandybridge: assign host bridge ops in chipset devicetree ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: not tested on hardware yet -- To view, visit https://review.coreboot.org/c/coreboot/+/79113?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf3d9f8cd2be2f8ef71fd9fdb5f005f3b683332e Gerrit-Change-Number: 79113 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 15:55:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetree
by Felix Held (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Angel Pons. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79118?usp=email ) Change subject: sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetree ...................................................................... sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetree Since the HD audio controller in the PCH are always on the same device functions, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9bbbe9f4490dc6fb21174d63d1c8906d69ea3ee0 --- M src/northbridge/intel/sandybridge/chipset.cb M src/southbridge/intel/bd82x6x/azalia.c 2 files changed, 2 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/79118/1 diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index 258318c1..00ec492 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -26,7 +26,7 @@ device pci 16.3 alias me_kt off end # Management Engine KT device pci 19.0 alias gbe off end # Intel Gigabit Ethernet device pci 1a.0 alias ehci2 off end # USB2 EHCI #2 - device pci 1b.0 alias hda off end # High Definition Audio + device pci 1b.0 alias hda off ops bd82x6x_azalia_ops end # High Definition Audio device pci 1c.0 alias pcie_rp1 off ops bd82x6x_pcie_rp_ops end # PCIe Port #1 device pci 1c.1 alias pcie_rp2 off ops bd82x6x_pcie_rp_ops end # PCIe Port #2 device pci 1c.2 alias pcie_rp3 off ops bd82x6x_pcie_rp_ops end # PCIe Port #3 diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 97884c6..ddaa8a1 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -122,7 +122,7 @@ return "HDEF"; } -static struct device_operations azalia_ops = { +struct device_operations bd82x6x_azalia_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -130,11 +130,3 @@ .ops_pci = &pci_dev_ops_pci, .acpi_name = azalia_acpi_name, }; - -static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0 }; - -static const struct pci_driver pch_azalia __pci_driver = { - .ops = &azalia_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/79118?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9bbbe9f4490dc6fb21174d63d1c8906d69ea3ee0 Gerrit-Change-Number: 79118 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetree
by Felix Held (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Angel Pons. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79117?usp=email ) Change subject: sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetree ...................................................................... sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetree Since the PCIe root ports in the PCH are always on the same device functions, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I05bfe8db88fd54415f320f32ea147636ca4e0df8 --- M src/northbridge/intel/sandybridge/chipset.cb M src/southbridge/intel/bd82x6x/pcie.c 2 files changed, 9 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/79117/1 diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index 61e86e4..258318c1 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -27,14 +27,14 @@ device pci 19.0 alias gbe off end # Intel Gigabit Ethernet device pci 1a.0 alias ehci2 off end # USB2 EHCI #2 device pci 1b.0 alias hda off end # High Definition Audio - device pci 1c.0 alias pcie_rp1 off end # PCIe Port #1 - device pci 1c.1 alias pcie_rp2 off end # PCIe Port #2 - device pci 1c.2 alias pcie_rp3 off end # PCIe Port #3 - device pci 1c.3 alias pcie_rp4 off end # PCIe Port #4 - device pci 1c.4 alias pcie_rp5 off end # PCIe Port #5 - device pci 1c.5 alias pcie_rp6 off end # PCIe Port #6 - device pci 1c.6 alias pcie_rp7 off end # PCIe Port #7 - device pci 1c.7 alias pcie_rp8 off end # PCIe Port #8 + device pci 1c.0 alias pcie_rp1 off ops bd82x6x_pcie_rp_ops end # PCIe Port #1 + device pci 1c.1 alias pcie_rp2 off ops bd82x6x_pcie_rp_ops end # PCIe Port #2 + device pci 1c.2 alias pcie_rp3 off ops bd82x6x_pcie_rp_ops end # PCIe Port #3 + device pci 1c.3 alias pcie_rp4 off ops bd82x6x_pcie_rp_ops end # PCIe Port #4 + device pci 1c.4 alias pcie_rp5 off ops bd82x6x_pcie_rp_ops end # PCIe Port #5 + device pci 1c.5 alias pcie_rp6 off ops bd82x6x_pcie_rp_ops end # PCIe Port #6 + device pci 1c.6 alias pcie_rp7 off ops bd82x6x_pcie_rp_ops end # PCIe Port #7 + device pci 1c.7 alias pcie_rp8 off ops bd82x6x_pcie_rp_ops end # PCIe Port #8 device pci 1d.0 alias ehci1 off end # USB2 EHCI #1 device pci 1e.0 alias pci_bridge off end # PCI bridge device pci 1f.0 alias lpc on end # LPC bridge diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 325bfd2..13f16f8 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -258,7 +258,7 @@ pch_pcie_pm_late(dev); } -static struct device_operations device_ops = { +struct device_operations bd82x6x_pcie_rp_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, @@ -268,15 +268,3 @@ .acpi_name = pch_pcie_acpi_name, .ops_pci = &pci_dev_ops_pci, }; - -static const unsigned short pci_device_ids[] = { 0x1c10, 0x1c12, 0x1c14, 0x1c16, - 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e, - 0x1e10, 0x1e12, 0x1e14, 0x1e16, - 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e, - 0 }; - -static const struct pci_driver pch_pcie __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/79117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05bfe8db88fd54415f320f32ea147636ca4e0df8 Gerrit-Change-Number: 79117 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: nb/intel/sandybridge/pcie: drop unneeded HAVE_ACPI_TABLES guards
by Felix Held (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Angel Pons. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79116?usp=email ) Change subject: nb/intel/sandybridge/pcie: drop unneeded HAVE_ACPI_TABLES guards ...................................................................... nb/intel/sandybridge/pcie: drop unneeded HAVE_ACPI_TABLES guards Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I1e8c8b3e3672d1589a5910753986e4033d2ce766 --- M src/northbridge/intel/sandybridge/pcie.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/79116/1 diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index deb50b9..10aa283 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -6,7 +6,6 @@ #include <device/pci_ids.h> #include <assert.h> -#if CONFIG(HAVE_ACPI_TABLES) static const char *pcie_acpi_name(const struct device *dev) { assert(dev); @@ -41,7 +40,6 @@ return NULL; } -#endif struct device_operations sandybridge_nb_pcie_rp_ops = { .read_resources = pci_bus_read_resources, @@ -51,7 +49,5 @@ .reset_bus = pci_bus_reset, .init = pci_dev_init, .ops_pci = &pci_dev_ops_pci, -#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = pcie_acpi_name, -#endif }; -- To view, visit https://review.coreboot.org/c/coreboot/+/79116?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e8c8b3e3672d1589a5910753986e4033d2ce766 Gerrit-Change-Number: 79116 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: nb/intel/sandybridge: assign PCIe root port ops in chipset devicetree
by Felix Held (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Angel Pons. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79115?usp=email ) Change subject: nb/intel/sandybridge: assign PCIe root port ops in chipset devicetree ...................................................................... nb/intel/sandybridge: assign PCIe root port ops in chipset devicetree Since the PCIe root ports in the northbridge are always on the same device functions, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I357aa0b27fcc73814f60d0aa5b5141add8917825 --- M src/northbridge/intel/sandybridge/chipset.cb M src/northbridge/intel/sandybridge/pcie.c 2 files changed, 5 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/79115/1 diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index 38a53d5..61e86e4 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -11,12 +11,12 @@ device domain 0 on ops sandybridge_pci_domain_ops device pci 00.0 alias host_bridge on ops sandybridge_host_bridge_ops end - device pci 01.0 alias peg10 off end # PEG10 - device pci 01.1 alias peg11 off end # PEG11 - device pci 01.2 alias peg12 off end # PEG12 + device pci 01.0 alias peg10 off ops sandybridge_nb_pcie_rp_ops end # PEG10 + device pci 01.1 alias peg11 off ops sandybridge_nb_pcie_rp_ops end # PEG11 + device pci 01.2 alias peg12 off ops sandybridge_nb_pcie_rp_ops end # PEG12 device pci 02.0 alias igd off ops sandybridge_gma_func0_ops end # vga controller device pci 04.0 alias dev4 off end # Device 4 - device pci 06.0 alias peg60 off end # PEG60 + device pci 06.0 alias peg60 off ops sandybridge_nb_pcie_rp_ops end # PEG60 chip southbridge/intel/bd82x6x # Intel Series 6/7 PCH device pci 14.0 alias xhci off end # USB 3.0 Controller (only on 7 series) diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index ec737a2..deb50b9 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -43,7 +43,7 @@ } #endif -static struct device_operations device_ops = { +struct device_operations sandybridge_nb_pcie_rp_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, @@ -55,15 +55,3 @@ .acpi_name = pcie_acpi_name, #endif }; - -static const unsigned short pci_device_ids[] = { - 0x0101, 0x0105, 0x0109, 0x010d, - 0x0151, 0x0155, 0x0159, 0x015d, - 0, -}; - -static const struct pci_driver pch_pcie __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/79115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I357aa0b27fcc73814f60d0aa5b5141add8917825 Gerrit-Change-Number: 79115 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: nb/intel/sandybridge: assign gma ops in chipset devicetree
by Felix Held (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Angel Pons. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79114?usp=email ) Change subject: nb/intel/sandybridge: assign gma ops in chipset devicetree ...................................................................... nb/intel/sandybridge: assign gma ops in chipset devicetree Since the integrated GPU is always function 0 of device 2 on bus 0, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I20e387e626e19dc441aceda18451186d1e86cd5f --- M src/northbridge/intel/sandybridge/chipset.cb M src/northbridge/intel/sandybridge/gma.c 2 files changed, 2 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/79114/1 diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index 9fb1701..38a53d5 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -14,7 +14,7 @@ device pci 01.0 alias peg10 off end # PEG10 device pci 01.1 alias peg11 off end # PEG11 device pci 01.2 alias peg12 off end # PEG12 - device pci 02.0 alias igd off end # vga controller + device pci 02.0 alias igd off ops sandybridge_gma_func0_ops end # vga controller device pci 04.0 alias dev4 off end # Device 4 device pci 06.0 alias peg60 off end # PEG60 diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 3eed5cc..2304a04 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -640,7 +640,7 @@ dev->enabled = 0; } -static struct device_operations gma_func0_ops = { +struct device_operations sandybridge_gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -650,16 +650,3 @@ .ops_pci = &pci_dev_ops_pci, .acpi_name = gma_acpi_name, }; - -static const unsigned short pci_device_ids[] = { - 0x0102, 0x0106, 0x010a, 0x0112, - 0x0116, 0x0122, 0x0126, 0x0156, - 0x0166, 0x0162, 0x016a, 0x0152, - 0 -}; - -static const struct pci_driver gma __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/79114?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I20e387e626e19dc441aceda18451186d1e86cd5f Gerrit-Change-Number: 79114 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: nb/intel/sandybridge: assign host bridge ops in chipset devicetree
by Felix Held (Code Review) 17 Nov '23

17 Nov '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79113?usp=email ) Change subject: nb/intel/sandybridge: assign host bridge ops in chipset devicetree ...................................................................... nb/intel/sandybridge: assign host bridge ops in chipset devicetree Since the host bridge is always function 0 of device 0 on bus 0, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Icf3d9f8cd2be2f8ef71fd9fdb5f005f3b683332e --- M src/northbridge/intel/sandybridge/chipset.cb M src/northbridge/intel/sandybridge/northbridge.c 2 files changed, 2 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/79113/1 diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index 5635ca6..9fb1701 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -10,7 +10,7 @@ end device domain 0 on ops sandybridge_pci_domain_ops - device pci 00.0 alias host_bridge on end # host bridge + device pci 00.0 alias host_bridge on ops sandybridge_host_bridge_ops end device pci 01.0 alias peg10 off end # PEG10 device pci 01.1 alias peg11 off end # PEG11 device pci 01.2 alias peg12 off end # PEG12 diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 9511cc3..6b89710 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -390,7 +390,7 @@ set_above_4g_pci(dev); } -static struct device_operations mc_ops = { +struct device_operations sandybridge_host_bridge_ops = { .read_resources = mc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -399,18 +399,6 @@ .acpi_fill_ssdt = mc_gen_ssdt, }; -static const unsigned short pci_device_ids[] = { - 0x0100, 0x0104, 0x0108, /* Sandy Bridge */ - 0x0150, 0x0154, 0x0158, /* Ivy Bridge */ - 0 -}; - -static const struct pci_driver mc_driver __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VID_INTEL, - .devices = pci_device_ids, -}; - struct device_operations sandybridge_cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, -- To view, visit https://review.coreboot.org/c/coreboot/+/79113?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf3d9f8cd2be2f8ef71fd9fdb5f005f3b683332e Gerrit-Change-Number: 79113 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit November 2023