coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

1 participants
3037 discussions

[M] Change in coreboot[main]: mb/goog/brya/var/brya0/skolas: Disable LTE gpios if LTE_ABSENT
by Nick Vaccaro (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Eric Lai, Nick Vaccaro, Subrata Banik. Hello Eric Lai, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79120?usp=email to look at the new patch set (#2). Change subject: mb/goog/brya/var/brya0/skolas: Disable LTE gpios if LTE_ABSENT ...................................................................... mb/goog/brya/var/brya0/skolas: Disable LTE gpios if LTE_ABSENT Check FW_CONFIG and disable gpios for LTE if LTE_ABSENT for skolas and brya0 variants. BUG=b:311459627 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot aviko to kernel. Change-Id: Ie2143f110c6bd97ae4ebbac7489ab8f043738eab Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/brya0/variant.c M src/mainboard/google/brya/variants/skolas/variant.c 2 files changed, 64 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/79120/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79120?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2143f110c6bd97ae4ebbac7489ab8f043738eab Gerrit-Change-Number: 79120 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: Post-build control of serial
by Simon Glass (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Jérémy Compostella, Karthik Ramasubramanian, Paul Menzel, Simon Glass, Stefan Reinauer. Simon Glass has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77712?usp=email ) Change subject: Post-build control of serial ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/77712/comment/925dae59_92724f7d : PS2, Line 7: Post-build control of serial > The commit seems to do much more. Can you please give me an example? Patchset: PS2: > It’s a nice idea, but there is also NVRAM/CMOS and more, and already CBFS. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/77712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04e946b33035a493e833500351a0483761252613 Gerrit-Change-Number: 77712 Gerrit-PatchSet: 5 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 17:31:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/goog/brya: Add gpio configuration based on FW_CONFIG
by Nick Vaccaro (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Eric Lai, Nick Vaccaro, Shelley Chen, Subrata Banik. Hello Eric Lai, Nick Vaccaro, Shelley Chen, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79119?usp=email to look at the new patch set (#2). Change subject: mb/goog/brya: Add gpio configuration based on FW_CONFIG ...................................................................... mb/goog/brya: Add gpio configuration based on FW_CONFIG Add call to fw_config_gpio_padbased_override() to allow variants to configure gpios based on FW_CONFIG settings. BUG=b:311459627 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot aviko to kernel. Change-Id: Ica92ce397e1ea2769b1a698d77ccd51dc87605c8 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/mainboard.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/79119/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79119?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica92ce397e1ea2769b1a698d77ccd51dc87605c8 Gerrit-Change-Number: 79119 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: Post-build control of serial
by Simon Glass (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Jérémy Compostella, Karthik Ramasubramanian, Stefan Reinauer. Simon Glass has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77712?usp=email ) Change subject: Post-build control of serial ...................................................................... Patch Set 5: (5 comments) File Documentation/util/cbfstool/ccb.md: https://review.coreboot.org/c/coreboot/+/77712/comment/c7f1e1ec_dc932fa9 : PS2, Line 11: ccb-set > I will try: […] Done File src/commonlib/include/commonlib/ccb.h: https://review.coreboot.org/c/coreboot/+/77712/comment/b159aeb4_6beed98b : PS2, Line 32: struct ccb { : uint32_t magic; : uint32_t flags; : }; : > I thought that was a vboot-specific thing? […] Done File src/lib/ccb.c: https://review.coreboot.org/c/coreboot/+/77712/comment/325543cf_1937ab2b : PS3, Line 8: struct ccb ccb_static __attribute__((section(".init"))) = { > > `Prefer __section(".init") over __attribute__((section(".init")))` […] Actually that one doesn't seem to work. I cannot find a header file that defines it File util/cbfstool/cbfstool.c: https://review.coreboot.org/c/coreboot/+/77712/comment/92f585b2_a71a647f : PS4, Line 2140: "Get a value from the Coreboot Control Block\n" > > `code indent should use tabs where possible` […] Done https://review.coreboot.org/c/coreboot/+/77712/comment/ced8c77c_0eedca58 : PS4, Line 2142: "Set a value in the Coreboot Control Block\n" > > `code indent should use tabs where possible` […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/77712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04e946b33035a493e833500351a0483761252613 Gerrit-Change-Number: 77712 Gerrit-PatchSet: 5 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 17:30:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Comment-In-Reply-To: Simon Glass <sjg(a)chromium.org> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: Post-build control of serial
by Simon Glass (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Jérémy Compostella, Stefan Reinauer. Hello Felix Singer, Jérémy Compostella, Patrick Georgi, Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77712?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: Post-build control of serial ...................................................................... Post-build control of serial It is annoying to have to create and maintain two completely different builds of coreboot just to enable or disable the console. It would be much more convenient to have a 'silent' flag in the image, which can be updated as needed, without needing to rebuild coreboot. Introduce the 'coreboot Control Block' (CCB) which can hold such settings. It is designed to be available very early in bootblock, before CBFS is ready. It is able to control the output of the very first bootblock banner. The CCB is then placed in cbmem so it is available to other stages. Provide options in cbfstool to get and set settings in the CCB. This makes it easy to use this feature. BUG=none BRANCH=none TEST=make (to build coreboot) $ cbfstool build/coreboot.rom ccb-get -n serial serial=normal First try this to see that the bootblock outputs its banner: $ qemu-system-i386 -bios build/coreboot.rom -nographic |head -5 [NOTE ] coreboot-4.21 Fri Nov 17 12:09:01 UTC 2023 x86_32 bootblock starting (log level: 7)... ... Now set it to silent and try again, to see that the bootblock output is suppressed, so that the first output shown is the romstage: $ cbfstool build/coreboot.rom ccb-get -n serial -V silent serial=silent $ qemu-system-i386 -bios build/coreboot.rom -nographic (no output) Change-Id: I04e946b33035a493e833500351a0483761252613 Signed-off-by: Simon Glass <sjg(a)chromium.org> --- A Documentation/technotes/ccb.md M Documentation/technotes/index.md A Documentation/util/cbfstool/ccb.md M Documentation/util/cbfstool/index.md M src/arch/x86/postcar.c M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h A src/commonlib/include/commonlib/ccb.h A src/commonlib/include/commonlib/ccb_api.h M src/console/Kconfig M src/console/console.c M src/console/init.c M src/include/console/streams.h M src/include/rules.h M src/lib/Kconfig M src/lib/Makefile.inc M src/lib/bootblock.c A src/lib/ccb.c M src/lib/hardwaremain.c M src/lib/prog_loaders.c M util/cbfstool/cbfstool.c 20 files changed, 509 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/77712/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/77712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04e946b33035a493e833500351a0483761252613 Gerrit-Change-Number: 77712 Gerrit-PatchSet: 5 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/google/brya: Disable LTE gpios if LTE_ABSENT
by Nick Vaccaro (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Eric Lai, Nick Vaccaro, Subrata Banik. Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79120?usp=email ) Change subject: mb/google/brya: Disable LTE gpios if LTE_ABSENT ...................................................................... mb/google/brya: Disable LTE gpios if LTE_ABSENT Check FW_CONFIG and disable gpios for LTE if LTE_ABSENT for skolas and brya0 variants. BUG=b:311459627 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot aviko to kernel. Change-Id: Ie2143f110c6bd97ae4ebbac7489ab8f043738eab Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/brya0/variant.c M src/mainboard/google/brya/variants/skolas/variant.c 2 files changed, 64 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/79120/1 diff --git a/src/mainboard/google/brya/variants/brya0/variant.c b/src/mainboard/google/brya/variants/brya0/variant.c index e9ae51e..844313b 100644 --- a/src/mainboard/google/brya/variants/brya0/variant.c +++ b/src/mainboard/google/brya/variants/brya0/variant.c @@ -4,8 +4,40 @@ #include <fw_config.h> #include <baseboard/variants.h> +static const struct pad_config lte_disable_pads[] = { + /* A7 : WWAN_PCIE_WAKE_ODL */ + PAD_NC(GPP_A7, NONE), + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_NC(GPP_A8, NONE), + /* D5 : SRCCLKREQ0# ==> WWAN_DPR_SAR_ODL */ + PAD_NC(GPP_D5, NONE), + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ + PAD_NC(GPP_E0, NONE), + /* E10 : THC0_SPI1_CS# ==> WWAN_CONFIG0 */ + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), + /* E16 : WWAN_RST_L */ + PAD_NC(GPP_E16, NONE), + /* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */ + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L */ + PAD_NC(GPP_F21, NONE), + /* H23 : SRCCLKREQ5# ==> WWAN_CLKREQ_ODL */ + PAD_NC(GPP_H23, NONE), + /* GPD11 : LANPHYC ==> WWAN_CONFIG1 */ + PAD_NC(GPD11, NONE), +}; + void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW)); } + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (fw_config_probe(FW_CONFIG(DB_LTE, LTE_ABSENT))) { + printk(BIOS_INFO, "Disable LTE GPIO pins.\n"); + gpio_padbased_override(padbased_table, lte_disable_pads, + ARRAY_SIZE(lte_disable_pads)); + } +} diff --git a/src/mainboard/google/brya/variants/skolas/variant.c b/src/mainboard/google/brya/variants/skolas/variant.c index e9ae51e..844313b 100644 --- a/src/mainboard/google/brya/variants/skolas/variant.c +++ b/src/mainboard/google/brya/variants/skolas/variant.c @@ -4,8 +4,40 @@ #include <fw_config.h> #include <baseboard/variants.h> +static const struct pad_config lte_disable_pads[] = { + /* A7 : WWAN_PCIE_WAKE_ODL */ + PAD_NC(GPP_A7, NONE), + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_NC(GPP_A8, NONE), + /* D5 : SRCCLKREQ0# ==> WWAN_DPR_SAR_ODL */ + PAD_NC(GPP_D5, NONE), + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ + PAD_NC(GPP_E0, NONE), + /* E10 : THC0_SPI1_CS# ==> WWAN_CONFIG0 */ + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), + /* E16 : WWAN_RST_L */ + PAD_NC(GPP_E16, NONE), + /* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */ + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L */ + PAD_NC(GPP_F21, NONE), + /* H23 : SRCCLKREQ5# ==> WWAN_CLKREQ_ODL */ + PAD_NC(GPP_H23, NONE), + /* GPD11 : LANPHYC ==> WWAN_CONFIG1 */ + PAD_NC(GPD11, NONE), +}; + void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW)); } + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (fw_config_probe(FW_CONFIG(DB_LTE, LTE_ABSENT))) { + printk(BIOS_INFO, "Disable LTE GPIO pins.\n"); + gpio_padbased_override(padbased_table, lte_disable_pads, + ARRAY_SIZE(lte_disable_pads)); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79120?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2143f110c6bd97ae4ebbac7489ab8f043738eab Gerrit-Change-Number: 79120 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/brya: add gpio configuration based on FW_CONFIG
by Nick Vaccaro (Code Review) 17 Nov '23

17 Nov '23

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[L] Change in coreboot[main]: Post-build control of serial
by Simon Glass (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Jérémy Compostella, Stefan Reinauer. Simon Glass has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77712?usp=email ) Change subject: Post-build control of serial ...................................................................... Patch Set 4: (6 comments) File Documentation/util/cbfstool/ccb.md: https://review.coreboot.org/c/coreboot/+/77712/comment/169a9e0c_d532d859 : PS2, Line 11: ccb-set > can we have this be more "natural"? […] I will try: configure configure-get I don't like the last one very much. WDYT? File src/commonlib/include/commonlib/ccb.h: https://review.coreboot.org/c/coreboot/+/77712/comment/3767a75d_c9c4ec97 : PS2, Line 32: struct ccb { : uint32_t magic; : uint32_t flags; : }; : > Can we / do we want to migrate GBB into this format as well? It would be nice to not have several ty […] I thought that was a vboot-specific thing? Also, my understanding is that GBB only supports flags, which is all this does too, right now. But this can be expanded (e.g. for log levels) but I'm not sure that GBB can? File src/console/Kconfig: https://review.coreboot.org/c/coreboot/+/77712/comment/06133d7c_92ba5820 : PS2, Line 443: config CONSOLE_SILENT_IN_CCB : bool "Flag for silencing console is in coreboot control block" : default y : help : This enables using the coreboot control block (CCB) to obtain the : console silence flag in the bootblock. This is set to 0 by default, : meaning that the console is active (if enabled) but can be set to 1 : by an external tool operating on the image. > What other mechanisms would we use here instead of CCB? Can we just have one that works everywhere? […] Yes I suppose we can drop this option and just always support it? File src/lib/ccb.c: https://review.coreboot.org/c/coreboot/+/77712/comment/5c04437c_44ac4292 : PS3, Line 8: struct ccb ccb_static __attribute__((section(".init"))) = { > `Prefer __section(".init") over __attribute__((section(".init")))` Please fix. File util/cbfstool/cbfstool.c: https://review.coreboot.org/c/coreboot/+/77712/comment/a261607b_0fc307a0 : PS4, Line 2140: "Get a value from the Coreboot Control Block\n" > `code indent should use tabs where possible` Please fix. https://review.coreboot.org/c/coreboot/+/77712/comment/4e28c69a_aa3fa186 : PS4, Line 2142: "Set a value in the Coreboot Control Block\n" > `code indent should use tabs where possible` Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/77712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04e946b33035a493e833500351a0483761252613 Gerrit-Change-Number: 77712 Gerrit-PatchSet: 4 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Fri, 17 Nov 2023 17:26:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: Docs/releases: Update 4.22 release notes
by Martin L Roth (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Angel Pons, Felix Singer, Jason Glenesk, Paul Menzel. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79077?usp=email ) Change subject: Docs/releases: Update 4.22 release notes ...................................................................... Patch Set 1: (5 comments) File Documentation/releases/coreboot-4.22-relnotes.md: https://review.coreboot.org/c/coreboot/+/79077/comment/77412ff0_78349214 : PS1, Line 154: Moved > *Move* for consistency? Done https://review.coreboot.org/c/coreboot/+/79077/comment/ed3b19ab_02a74924 : PS1, Line 158: chromebooks > Chromebooks Done https://review.coreboot.org/c/coreboot/+/79077/comment/877bfca1_689a785c : PS1, Line 167: * Work on chipset devicetrees for all platforms. https://review.coreboot.org/c/coreboot/+/79077/comment/9f4b4980_e1ad6803 : PS1, Line 189: Add opensil submodule https://review.coreboot.org/c/coreboot/+/79077/comment/a380e688_53bfdb51 : PS1, Line 318: * Add Chipset device trees for all SOCs Complete -- To view, visit https://review.coreboot.org/c/coreboot/+/79077?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id723f8e1fc92ef1a36e877f48e594eef59b0ba8e Gerrit-Change-Number: 79077 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 17:26:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: Post-build control of serial
by Simon Glass (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Jérémy Compostella, Simon Glass. Hello Felix Singer, Jérémy Compostella, Patrick Georgi, Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77712?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: Post-build control of serial ...................................................................... Post-build control of serial It is annoying to have to create and maintain two completely different builds of coreboot just to enable or disable the console. It would be much more convenient to have a 'silent' flag in the image, which can be updated as needed, without needing to rebuild coreboot. Introduce the 'coreboot Control Block' (CCB) which can hold such settings. It is designed to be available very early in bootblock, before CBFS is ready. It is able to control the output of the very first bootblock banner. The CCB is then placed in cbmem so it is available to other stages. Provide options in cbfstool to get and set settings in the CCB. This makes it easy to use this feature. BUG=none BRANCH=none TEST=make (to build coreboot) $ cbfstool build/coreboot.rom ccb-get -n serial serial=normal First try this to see that the bootblock outputs its banner: $ qemu-system-i386 -bios build/coreboot.rom -nographic |head -5 [NOTE ] coreboot-4.21 Fri Nov 17 12:09:01 UTC 2023 x86_32 bootblock starting (log level: 7)... ... Now set it to silent and try again, to see that the bootblock output is suppressed, so that the first output shown is the romstage: $ cbfstool build/coreboot.rom ccb-get -n serial -V silent serial=silent $ qemu-system-i386 -bios build/coreboot.rom -nographic (no output) Change-Id: I04e946b33035a493e833500351a0483761252613 Signed-off-by: Simon Glass <sjg(a)chromium.org> --- A Documentation/technotes/ccb.md M Documentation/technotes/index.md A Documentation/util/cbfstool/ccb.md M Documentation/util/cbfstool/index.md M src/arch/x86/postcar.c M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h A src/commonlib/include/commonlib/ccb.h A src/commonlib/include/commonlib/ccb_api.h M src/console/Kconfig M src/console/console.c M src/console/init.c M src/include/console/streams.h M src/include/rules.h M src/lib/Kconfig M src/lib/Makefile.inc M src/lib/bootblock.c A src/lib/ccb.c M src/lib/hardwaremain.c M src/lib/prog_loaders.c M util/cbfstool/cbfstool.c 20 files changed, 509 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/77712/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/77712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04e946b33035a493e833500351a0483761252613 Gerrit-Change-Number: 77712 Gerrit-PatchSet: 4 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2023