coreboot-gerrit November 2023

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[XS] Change in coreboot[main]: Disable separate romstage for emulation builds
by Simon Glass (Code Review) 17 Nov '23

17 Nov '23

Simon Glass has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79079?usp=email ) Change subject: Disable separate romstage for emulation builds ...................................................................... Disable separate romstage for emulation builds This does not seem to be useful for use with QEMU. Disable it. Change-Id: Ic4fa8322dba9b5a46c5a73489cb396199621e068 Signed-off-by: Simon Glass <sjg(a)chromium.org> --- M src/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/79079/1 diff --git a/src/Kconfig b/src/Kconfig index 5cb9a1a..ac4fa9c 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -245,7 +245,7 @@ config SEPARATE_ROMSTAGE bool "Build a separate romstage" - default y + default y if !VENDOR_EMULATION help Build a separate romstage that is loaded by bootblock. With this option disabled the romstage sources are linked inside the bootblock -- To view, visit https://review.coreboot.org/c/coreboot/+/79079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4fa8322dba9b5a46c5a73489cb396199621e068 Gerrit-Change-Number: 79079 Gerrit-PatchSet: 1 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: Post-build control of serial
by Simon Glass (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Simon Glass. Hello Felix Singer, Patrick Georgi, Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77712?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Post-build control of serial ...................................................................... Post-build control of serial It is annoying to have to create and maintain two completely different builds of coreboot just to enable or disable the console. It would be much more convenient to have a 'silent' flag in the image, which can be updated as needed, without needing to rebuild coreboot. Introduce the 'coreboot Control Block' (CCB) which can hold such settings. It is designed to be available very early in bootblock, before CBFS is ready. It is able to control the output of the very first bootblock banner. The CCB is then placed in cbmem so it is available to other stages. Provide options in cbfstool to get and set settings in the CCB. This makes it easy to use this feature. BUG=none BRANCH=none TEST=make (to build coreboot) $ cbfstool build/coreboot.rom ccb-get -n serial serial=normal First try this to see that the bootblock outputs its banner: $ qemu-system-i386 -bios build/coreboot.rom -nographic |head -5 [NOTE ] coreboot-4.21 Fri Nov 17 12:09:01 UTC 2023 x86_32 bootblock starting (log level: 7)... ... Now set it to silent and try again, to see that the bootblock output is suppressed, so that the first output shown is the romstage: $ cbfstool build/coreboot.rom ccb-get -n serial -V silent serial=silent $ qemu-system-i386 -bios build/coreboot.rom -nographic (no output) Change-Id: I04e946b33035a493e833500351a0483761252613 Signed-off-by: Simon Glass <sjg(a)chromium.org> --- A Documentation/technotes/ccb.md M Documentation/technotes/index.md A Documentation/util/cbfstool/ccb.md M Documentation/util/cbfstool/index.md M src/arch/x86/postcar.c M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h A src/commonlib/include/commonlib/ccb.h A src/commonlib/include/commonlib/ccb_api.h M src/console/Kconfig M src/console/console.c M src/console/init.c M src/include/console/streams.h M src/include/rules.h M src/lib/Kconfig M src/lib/Makefile.inc M src/lib/bootblock.c A src/lib/ccb.c M src/lib/hardwaremain.c M src/lib/prog_loaders.c M util/cbfstool/cbfstool.c 20 files changed, 509 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/77712/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/77712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04e946b33035a493e833500351a0483761252613 Gerrit-Change-Number: 77712 Gerrit-PatchSet: 3 Gerrit-Owner: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: nb/intel/sandybridge: Fix unitialized variable issue
by Jérémy Compostella (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Angel Pons, Keith Hui, Martin L Roth, Martin Roth, Paul Menzel. Hello Angel Pons, Keith Hui, Martin L Roth, Martin Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79093?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Angel Pons, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: nb/intel/sandybridge: Fix unitialized variable issue ...................................................................... nb/intel/sandybridge: Fix unitialized variable issue commit 1e9601c5ef80 ("nb/intel/sandybridge: Standardize MRC vs. native SPD mapping API") introduced an uninitialized variable issue. Change-Id: I41b081dc4c961acc04423067e29e0eabe5f17539 Found-by: Coverity CID 1524317 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/northbridge/intel/sandybridge/raminit_mrc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/79093/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79093?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I41b081dc4c961acc04423067e29e0eabe5f17539 Gerrit-Change-Number: 79093 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: nb/intel/sandybridge: Fix unitialized variable issue
by Jérémy Compostella (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Keith Hui, Martin L Roth, Martin Roth, Paul Menzel. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79093?usp=email ) Change subject: nb/intel/sandybridge: Fix unitialized variable issue ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79093/comment/b49477dc_41e7457c : PS1, Line 12: New defect(s) Reported-by: Coverity Scan : Showing 1 of 1 defect(s) : : ** CID 1524317: Uninitialized variables (UNINIT) : /src/northbridge/intel/sandybridge/raminit_mrc.c: 332 in : spd_fill_pei_data() > Maybe use the Found-by tag. See `git log --grep 'CID'`. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79093?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I41b081dc4c961acc04423067e29e0eabe5f17539 Gerrit-Change-Number: 79093 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 16:55:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: nb/amd/pi/00730F01: add CPU and domain ops in devicetree
by Felix Held (Code Review) 17 Nov '23

17 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79085?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: nb/amd/pi/00730F01: add CPU and domain ops in devicetree ...................................................................... nb/amd/pi/00730F01: add CPU and domain ops in devicetree Add the CPU and PCI domain operation bindings statically in the chipset devicetree instead of adding them during runtime. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I44fa57458c408e74a6341643620c5e9ac1817557 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79085 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/northbridge/amd/pi/00730F01/chipset.cb M src/northbridge/amd/pi/00730F01/northbridge.c 2 files changed, 6 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Matt DeVillier: Looks good to me, approved diff --git a/src/northbridge/amd/pi/00730F01/chipset.cb b/src/northbridge/amd/pi/00730F01/chipset.cb index 57f89c4..bc79426 100644 --- a/src/northbridge/amd/pi/00730F01/chipset.cb +++ b/src/northbridge/amd/pi/00730F01/chipset.cb @@ -1,9 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01 - device cpu_cluster 0 on end + device cpu_cluster 0 on + ops amd_fam16_mod30_cpu_bus_ops + end device domain 0 on + ops amd_fam16_mod30_pci_domain_ops device pci 0.0 alias gnb on end device pci 0.2 alias iommu off end device pci 1.0 alias gfx off end diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index e8f7abd..3ac94e5 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -831,7 +831,7 @@ return NULL; } -static struct device_operations pci_domain_ops = { +struct device_operations amd_fam16_mod30_pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = pci_host_bridge_scan_bus, @@ -863,26 +863,15 @@ } } -static struct device_operations cpu_bus_ops = { +struct device_operations amd_fam16_mod30_cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, .acpi_fill_ssdt = generate_cpu_entries, }; -static void root_complex_enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - struct chip_operations northbridge_amd_pi_00730F01_ops = { CHIP_NAME("AMD FAM16 Root Complex") - .enable_dev = root_complex_enable_dev, .final = fam16_finalize, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/79085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44fa57458c408e74a6341643620c5e9ac1817557 Gerrit-Change-Number: 79085 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: nb/amd/pi/00730F01: restructure chip ops
by Felix Held (Code Review) 17 Nov '23

17 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79084?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: nb/amd/pi/00730F01: restructure chip ops ...................................................................... nb/amd/pi/00730F01: restructure chip ops Since this chip is a SoC and also to bring the chipset devicetree more in line with the chipset devicetree of Sandy Bridge, merge the chip operations of the northbridge's root complex and the northbridge itself into one chip operations structure and use it at the top level of the devicetree. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8b42bac07b1409bbc797bc4428cf9f84a40e94c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79084 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb M src/northbridge/amd/pi/00730F01/chipset.cb M src/northbridge/amd/pi/00730F01/northbridge.c 6 files changed, 42 insertions(+), 57 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 4a09ce7..7725c65 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -1,16 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -chip northbridge/amd/pi/00730F01/root_complex +chip northbridge/amd/pi/00730F01 device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device ref iommu on end - device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) - device ref gpp_bridge_1 on end # LAN3 - device ref gpp_bridge_2 on end # LAN2 - device ref gpp_bridge_3 on end # LAN1 - device ref gpp_bridge_4 on end # mPCIe slot 1 - end + device ref iommu on end + device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) + device ref gpp_bridge_1 on end # LAN3 + device ref gpp_bridge_2 on end # LAN2 + device ref gpp_bridge_3 on end # LAN1 + device ref gpp_bridge_4 on end # mPCIe slot 1 chip southbridge/amd/pi/hudson device ref xhci on end # XHCI HC0 muxed with EHCI 2 diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index dcff5ab..5c16920 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -1,16 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -chip northbridge/amd/pi/00730F01/root_complex +chip northbridge/amd/pi/00730F01 device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device ref iommu on end - device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) - device ref gpp_bridge_1 on end # LAN3 - device ref gpp_bridge_2 on end # LAN2 - device ref gpp_bridge_3 on end # LAN1 - device ref gpp_bridge_4 on end # mPCIe slot 1 - end + device ref iommu on end + device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) + device ref gpp_bridge_1 on end # LAN3 + device ref gpp_bridge_2 on end # LAN2 + device ref gpp_bridge_3 on end # LAN1 + device ref gpp_bridge_4 on end # mPCIe slot 1 chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus device ref xhci on end # XHCI HC0 muxed with EHCI 2 diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index 02390d2..57eebb6 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -1,16 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -chip northbridge/amd/pi/00730F01/root_complex +chip northbridge/amd/pi/00730F01 device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device ref iommu on end - device ref gpp_bridge_0 on end # LAN1 - device ref gpp_bridge_1 on end # LAN2 - device ref gpp_bridge_2 on end # LAN3 - device ref gpp_bridge_3 on end # LAN4 - device ref gpp_bridge_4 on end # mPCIe slot 1 - end + device ref iommu on end + device ref gpp_bridge_0 on end # LAN1 + device ref gpp_bridge_1 on end # LAN2 + device ref gpp_bridge_2 on end # LAN3 + device ref gpp_bridge_3 on end # LAN4 + device ref gpp_bridge_4 on end # mPCIe slot 1 chip southbridge/amd/pi/hudson device ref xhci on end # XHCI HC0 muxed with EHCI 2 diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb index fb41fef..75cc446 100644 --- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -1,16 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -chip northbridge/amd/pi/00730F01/root_complex +chip northbridge/amd/pi/00730F01 device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device ref iommu on end - device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) - device ref gpp_bridge_1 on end # LAN3 - device ref gpp_bridge_2 on end # LAN2 - device ref gpp_bridge_3 on end # LAN1 - device ref gpp_bridge_4 on end # mPCIe slot 1 - end + device ref iommu on end + device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) + device ref gpp_bridge_1 on end # LAN3 + device ref gpp_bridge_2 on end # LAN2 + device ref gpp_bridge_3 on end # LAN1 + device ref gpp_bridge_4 on end # mPCIe slot 1 chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus device ref xhci on end # XHCI HC0 muxed with EHCI 2 diff --git a/src/northbridge/amd/pi/00730F01/chipset.cb b/src/northbridge/amd/pi/00730F01/chipset.cb index 2ddfceb..57f89c4 100644 --- a/src/northbridge/amd/pi/00730F01/chipset.cb +++ b/src/northbridge/amd/pi/00730F01/chipset.cb @@ -1,22 +1,20 @@ # SPDX-License-Identifier: GPL-2.0-only -chip northbridge/amd/pi/00730F01/root_complex +chip northbridge/amd/pi/00730F01 device cpu_cluster 0 on end device domain 0 on - chip northbridge/amd/pi/00730F01 - device pci 0.0 alias gnb on end - device pci 0.2 alias iommu off end - device pci 1.0 alias gfx off end - device pci 1.1 alias gfx_hda off end - device pci 2.0 on end # Dummy Host Bridge, do not disable - device pci 2.1 alias gpp_bridge_0 off end - device pci 2.2 alias gpp_bridge_1 off end - device pci 2.3 alias gpp_bridge_2 off end - device pci 2.4 alias gpp_bridge_3 off end - device pci 2.5 alias gpp_bridge_4 off end - device pci 8.0 alias psp on end - end + device pci 0.0 alias gnb on end + device pci 0.2 alias iommu off end + device pci 1.0 alias gfx off end + device pci 1.1 alias gfx_hda off end + device pci 2.0 on end # Dummy Host Bridge, do not disable + device pci 2.1 alias gpp_bridge_0 off end + device pci 2.2 alias gpp_bridge_1 off end + device pci 2.3 alias gpp_bridge_2 off end + device pci 2.4 alias gpp_bridge_3 off end + device pci 2.5 alias gpp_bridge_4 off end + device pci 8.0 alias psp on end chip southbridge/amd/pi/hudson device pci 10.0 alias xhci off end diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index bafe5a5..e8f7abd 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -695,12 +695,6 @@ } } -struct chip_operations northbridge_amd_pi_00730F01_ops = { - CHIP_NAME("AMD FAM16 Northbridge") - .enable_dev = 0, - .final = fam16_finalize, -}; - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned int hole_startk; @@ -886,9 +880,10 @@ } } -struct chip_operations northbridge_amd_pi_00730F01_root_complex_ops = { +struct chip_operations northbridge_amd_pi_00730F01_ops = { CHIP_NAME("AMD FAM16 Root Complex") .enable_dev = root_complex_enable_dev, + .final = fam16_finalize, }; /********************************************************************* -- To view, visit https://review.coreboot.org/c/coreboot/+/79084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b42bac07b1409bbc797bc4428cf9f84a40e94c2 Gerrit-Change-Number: 79084 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: nb/amd/pi/00730F01: introduce and use chipset devicetree
by Felix Held (Code Review) 17 Nov '23

17 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79083?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: nb/amd/pi/00730F01: introduce and use chipset devicetree ...................................................................... nb/amd/pi/00730F01: introduce and use chipset devicetree BKDG #52740 Rev 3.05 was used as a reference for the SoC's various PCI devices. The HDA controller in the FCH at function 2 of device 0x14 on bus 0 was missing in the mainboard's devicetrees. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79083 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb M src/northbridge/amd/pi/00730F01/Kconfig A src/northbridge/amd/pi/00730F01/chipset.cb 6 files changed, 118 insertions(+), 148 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Nico Huber: Looks good to me, but someone else must approve diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 1abcd61..4a09ce7 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -1,32 +1,22 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on end - device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 off end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) - device pci 2.2 on end # LAN3 - device pci 2.3 on end # LAN2 - device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 - device pci 8.0 on end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 + device ref iommu on end + device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) + device ref gpp_bridge_1 on end # LAN3 + device ref gpp_bridge_2 on end # LAN2 + device ref gpp_bridge_3 on end # LAN1 + device ref gpp_bridge_4 on end # mPCIe slot 1 + end chip southbridge/amd/pi/hudson - device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 - device pci 11.0 on end # SATA - device pci 12.0 off end # USB EHCI0 usb[0:3] not connected - device pci 13.0 on end # USB EHCI1 usb[4:7] - device pci 14.0 on end # SM - device pci 14.3 on # LPC 0x439d + device ref xhci on end # XHCI HC0 muxed with EHCI 2 + device ref sata on end + device ref ehci_1 on end # USB EHCI1 usb[4:7] + device ref lpc_bridge on chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" register "reset_gpios" = "1" @@ -62,18 +52,9 @@ chip drivers/pc80/tpm device pnp 0c31.0 on end end # LPC TPM - end # LPC 0x439d - - device pci 14.7 on end # SD - device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI - end #chip southbridge/amd/pi/hudson - - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - end #domain -end #northbridge/amd/pi/00730F01/root_complex + end + device ref sdhci on end + device ref ehci_2 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end + end +end diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 99353f4..dcff5ab 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -1,32 +1,23 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on end - device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 off end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) - device pci 2.2 on end # LAN3 - device pci 2.3 on end # LAN2 - device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 - device pci 8.0 on end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 + device ref iommu on end + device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) + device ref gpp_bridge_1 on end # LAN3 + device ref gpp_bridge_2 on end # LAN2 + device ref gpp_bridge_3 on end # LAN1 + device ref gpp_bridge_4 on end # mPCIe slot 1 + end - chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB EHCI0 usb[0:3] is connected - device pci 13.0 on end # USB EHCI1 usb[4:7] - device pci 14.0 on end # SM - device pci 14.3 on # LPC 0x439d + chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus + device ref xhci on end # XHCI HC0 muxed with EHCI 2 + device ref sata on end + device ref ehci_0 on end # USB EHCI0 usb[0:3] is connected + device ref ehci_1 on end # USB EHCI1 usb[4:7] + device ref lpc_bridge on chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" register "reset_gpios" = "1" @@ -58,19 +49,10 @@ device pnp 2e.107 on end device pnp 2e.607 off end device pnp 2e.f on end - end # SIO NCT5104D - end # LPC 0x439d - - device pci 14.7 on end # SD - device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI - end #chip southbridge/amd/pi/hudson - - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - end #domain -end #northbridge/amd/pi/00730F01/root_complex + end + end + device ref sdhci on end + device ref ehci_2 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end + end +end diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index c4975cc..02390d2 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -1,32 +1,23 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on end - device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 off end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # LAN1 - device pci 2.2 on end # LAN2 - device pci 2.3 on end # LAN3 - device pci 2.4 on end # LAN4 - device pci 2.5 on end # mPCIe slot 1 - device pci 8.0 on end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 + device ref iommu on end + device ref gpp_bridge_0 on end # LAN1 + device ref gpp_bridge_1 on end # LAN2 + device ref gpp_bridge_2 on end # LAN3 + device ref gpp_bridge_3 on end # LAN4 + device ref gpp_bridge_4 on end # mPCIe slot 1 + end chip southbridge/amd/pi/hudson - device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB EHCI0 usb[0:3] is connected - device pci 13.0 on end # USB EHCI1 usb[4:7] - device pci 14.0 on end # SM - device pci 14.3 on # LPC 0x439d + device ref xhci on end # XHCI HC0 muxed with EHCI 2 + device ref sata on end + device ref ehci_0 on end # USB EHCI0 usb[0:3] is connected + device ref ehci_1 on end # USB EHCI1 usb[4:7] + device ref lpc_bridge on chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" register "reset_gpios" = "1" @@ -59,18 +50,9 @@ device pnp 2e.607 off end device pnp 2e.f on end end # SIO NCT5104D - end # LPC 0x439d - - device pci 14.7 on end # SD - device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI - end #chip southbridge/amd/pi/hudson - - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - end #domain -end #northbridge/amd/pi/00730F01/root_complex + end + device ref sdhci on end + device ref ehci_2 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end + end +end diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb index 0aee11c..fb41fef 100644 --- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -1,32 +1,23 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on end - device domain 0 on subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/pi/00730F01 + device ref iommu on end + device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) + device ref gpp_bridge_1 on end # LAN3 + device ref gpp_bridge_2 on end # LAN2 + device ref gpp_bridge_3 on end # LAN1 + device ref gpp_bridge_4 on end # mPCIe slot 1 + end - chip northbridge/amd/pi/00730F01 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 off end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) - device pci 2.2 on end # LAN3 - device pci 2.3 on end # LAN2 - device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 - device pci 8.0 on end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 - - chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB EHCI0 usb[0:3] is connected - device pci 13.0 on end # USB EHCI1 usb[4:7] - device pci 14.0 on end # SM - device pci 14.3 on # LPC 0x439d + chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus + device ref xhci on end # XHCI HC0 muxed with EHCI 2 + device ref sata on end + device ref ehci_0 on end # USB EHCI0 usb[0:3] is connected + device ref ehci_1 on end # USB EHCI1 usb[4:7] + device ref lpc_bridge on chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" device pnp 2e.0 off end @@ -58,18 +49,8 @@ chip drivers/pc80/tpm device pnp 0c31.0 on end end # LPC TPM - end # LPC 0x439d - - device pci 14.7 off end # SD - device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI - end #chip southbridge/amd/pi/hudson - - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - end #domain -end #northbridge/amd/pi/00730F01/root_complex + end + device ref ehci_2 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end + end +end diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index 651735a..493bc6a 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -6,6 +6,10 @@ if NORTHBRIDGE_AMD_PI_00730F01 +config CHIPSET_DEVICETREE + string + default "northbridge/amd/pi/00730F01/chipset.cb" + config HW_MEM_HOLE_SIZEK hex default 0x100000 diff --git a/src/northbridge/amd/pi/00730F01/chipset.cb b/src/northbridge/amd/pi/00730F01/chipset.cb new file mode 100644 index 0000000..2ddfceb --- /dev/null +++ b/src/northbridge/amd/pi/00730F01/chipset.cb @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/amd/pi/00730F01/root_complex + device cpu_cluster 0 on end + + device domain 0 on + chip northbridge/amd/pi/00730F01 + device pci 0.0 alias gnb on end + device pci 0.2 alias iommu off end + device pci 1.0 alias gfx off end + device pci 1.1 alias gfx_hda off end + device pci 2.0 on end # Dummy Host Bridge, do not disable + device pci 2.1 alias gpp_bridge_0 off end + device pci 2.2 alias gpp_bridge_1 off end + device pci 2.3 alias gpp_bridge_2 off end + device pci 2.4 alias gpp_bridge_3 off end + device pci 2.5 alias gpp_bridge_4 off end + device pci 8.0 alias psp on end + end + + chip southbridge/amd/pi/hudson + device pci 10.0 alias xhci off end + device pci 11.0 alias sata off end + device pci 12.0 alias ehci_0 off end + device pci 13.0 alias ehci_1 off end + device pci 14.0 alias smbus on end + device pci 14.2 alias hda off end + device pci 14.3 alias lpc_bridge on end + device pci 14.7 alias sdhci off end + device pci 16.0 alias ehci_2 off end + end + + device pci 18.0 alias ht_0 on end + device pci 18.1 alias ht_1 on end + device pci 18.2 alias ht_2 on end + device pci 18.3 alias ht_3 on end + device pci 18.4 alias ht_4 on end + device pci 18.5 alias ht_5 on end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/79083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979 Gerrit-Change-Number: 79083 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: tests: Allow specifying vboot source directory
by Martin L Roth (Code Review) 17 Nov '23

17 Nov '23

Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78849?usp=email ) Change subject: tests: Allow specifying vboot source directory ...................................................................... Patch Set 4: (1 comment) File Makefile: https://review.coreboot.org/c/coreboot/+/78849/comment/ddac0bb9_608123af : PS4, Line 18: abspath > The problem with this patch is, when passing an absolute path to `-I`, `vboot-fixup-includes` in sec […] Thanks for tracking that down. I ran into similar issues with the openSIL code where it was assumed that directories are under $(top) when trying to change from relative to absolute paths. -- To view, visit https://review.coreboot.org/c/coreboot/+/78849?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id3bb3726c91167d2dd648d748763a3948787f28d Gerrit-Change-Number: 78849 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-CC: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 16:15:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetree
by Felix Held (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Angel Pons. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79118?usp=email ) Change subject: sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetree ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: not tested on hardware yet -- To view, visit https://review.coreboot.org/c/coreboot/+/79118?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9bbbe9f4490dc6fb21174d63d1c8906d69ea3ee0 Gerrit-Change-Number: 79118 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 15:57:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetree
by Felix Held (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Angel Pons. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79117?usp=email ) Change subject: sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetree ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: not tested on hardware yet -- To view, visit https://review.coreboot.org/c/coreboot/+/79117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05bfe8db88fd54415f320f32ea147636ca4e0df8 Gerrit-Change-Number: 79117 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 17 Nov 2023 15:56:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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