coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: libpayload: Add dma_allocator_range()
by Yi Chou (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Julius Werner, Yi Chou, Yu-Ping Wu. Hello Julius Werner, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78407?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: libpayload: Add dma_allocator_range() ...................................................................... libpayload: Add dma_allocator_range() Some sensitive data may remain DMA buffer, we will want to zero out everything on the DMA buffer before we jump into the kernel. To accomplish that, we will need this function to get the range of memory that can be allocated by the dma allocator. BUG=b:248610274 TEST=emerge-cherry libpayload BRANCH=none Signed-off-by: Yi Chou <yich(a)google.com> Change-Id: I8f3058dfd861ed44f716623967201b8cabe8d166 --- M payloads/libpayload/include/stdlib.h M payloads/libpayload/libc/malloc.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/78407/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78407?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f3058dfd861ed44f716623967201b8cabe8d166 Gerrit-Change-Number: 78407 Gerrit-PatchSet: 2 Gerrit-Owner: Yi Chou <yich(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yi Chou <yich(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/rex/var/karis: Use 2 gpio for stylus detect/wake
by David Wu (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Tarun, Tyler Wang. David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78336?usp=email ) Change subject: mb/google/rex/var/karis: Use 2 gpio for stylus detect/wake ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78336?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a83326f76932c8e501e6369bb845fc7236291b4 Gerrit-Change-Number: 78336 Gerrit-PatchSet: 6 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 16 Oct 2023 08:31:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/cmn/graphics: Implement API for IGD to join the MBUS
by Subrata Banik (Code Review) 16 Oct '23

16 Oct '23

Subrata Banik has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/78385?usp=email ) Change subject: soc/intel/cmn/graphics: Implement API for IGD to join the MBUS ...................................................................... soc/intel/cmn/graphics: Implement API for IGD to join the MBUS This patch implements `.final` hooks for the IGD device to perform the required operations before handing the control to the payload or OS. The MBUS (Memory Bus) is a high-speed interface that connects the graphics controller to the system memory. It provides a dedicated data path for graphics data, which helps to improve graphics performance. The MBUS is a key technology that helps to make the Intel i915 driver powerful and versatile graphics drivers available. It provides the high-speed data transfer capabilities that are essential for smooth and responsive graphics performance. Enable this config to ensure that the Intel GFX controller joins the MBUS before the i915 driver is loaded. This is necessary to prevent the i915 driver from re-initializing the display if the firmware has already initialized it. Without this config, the i915 driver will initialize the display to bring up the login screen although the firmware has initialized the display using the GFX MMIO registers and framebuffer. Kernel graphics driver can avoid redundant display init by firmware, which can optimize boot time by ~15ms-30ms. Ensures hashing mode is 1x4 to enable a single pipe between Pipe A or B. Typically, internal display is on Pipe-A, so 1x4 restricts MBUS joining to internal display alone. BUG=b:284799726 TEST=Able to build and boot google/rex Change-Id: I60ae76dc783383e027e66edbcdeeb535472caeb1 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/graphics/Kconfig M src/soc/intel/common/block/graphics/graphics.c 2 files changed, 41 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/78385/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78385?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60ae76dc783383e027e66edbcdeeb535472caeb1 Gerrit-Change-Number: 78385 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/common/block/acpi/northbridge.asl: Reserve SBREG BAR
by Michał Żygowski (Code Review) 16 Oct '23

16 Oct '23

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77445?usp=email ) Change subject: soc/intel/common/block/acpi/northbridge.asl: Reserve SBREG BAR ...................................................................... soc/intel/common/block/acpi/northbridge.asl: Reserve SBREG BAR Reserve SBREG BAR if it is outside of the PCH reserved memory range. Desktop series processors have larger SBREG BARs, which, unlike mobile processors, do not fall into the standard PCH reserved range (0xfc800000 - 0xfe7fffff). Create a separate reservation for such a case. There is no telling what could happen if the reservation is not made in ACPI. TEST=Boot Windows 11 and Ubuntu 22.04 on MSI PRO Z690-A DDR4 Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77445 Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl 1 file changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, but someone else must approve Krystian Hebel: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 44c873c..03295b4 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/hpet.h> +#include <commonlib/bsd/helpers.h> #include <soc/iomap.h> Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) @@ -165,6 +166,15 @@ 0x00000000, 0x10000, 0x1ffff, 0x00000000, 0x10000,,, PM02) +#if !((CONFIG_PCR_BASE_ADDRESS >= PCH_PRESERVED_BASE_ADDRESS) && \ + (CONFIG_PCR_BASE_ADDRESS < PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE)) + /* SBREG BAR if outside of PCH reserved resource */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x000000000, 0x00000000, 0x00000000, + 0x00000000,,, SM01) +#endif + /* PCH reserved resource (0xfc800000-0xfe7fffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, @@ -192,6 +202,18 @@ PMIN = \_SB.PCI0.MCHC.TLUD & (0xfff << 20) PLEN = PMAX - PMIN + 1 +#if !((CONFIG_PCR_BASE_ADDRESS >= PCH_PRESERVED_BASE_ADDRESS) && \ + (CONFIG_PCR_BASE_ADDRESS < PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE)) + /* Fix up SBREG BAR memory region if outside PCH reserved resource */ + CreateDwordField (MCRS, SM01._MIN, SMIN) + CreateDwordField (MCRS, SM01._MAX, SMAX) + CreateDwordField (MCRS, SM01._LEN, SLEN) + + SMIN = P2SB_BAR + SLEN = P2SB_SIZE + SMAX = SMIN + SLEN - 1 +#endif + /* Patch PM02 range based on Memory Size */ If (A4GS == 0) { CreateQwordField (MCRS, PM02._LEN, MSEN) -- To view, visit https://review.coreboot.org/c/coreboot/+/77445?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Gerrit-Change-Number: 77445 Gerrit-PatchSet: 20 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/intel/cmn/graphics: Implement API for IGD to join the MBUS
by Subrata Banik (Code Review) 16 Oct '23

16 Oct '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78385?usp=email ) Change subject: soc/intel/cmn/graphics: Implement API for IGD to join the MBUS ...................................................................... soc/intel/cmn/graphics: Implement API for IGD to join the MBUS This patch implements `.final` hooks for the IGD device to perform the required operations before handing the control to the payload or OS. The MBUS (Memory Bus) is a high-speed interface that connects the graphics controller to the system memory. It provides a dedicated data path for graphics data, which helps to improve graphics performance. The MBUS is a key technology that helps to make the Intel i915 driver powerful and versatile graphics drivers available. It provides the high-speed data transfer capabilities that are essential for smooth and responsive graphics performance. Enable this config to ensure that the Intel GFX controller joins the MBUS before the i915 driver is loaded. This is necessary to prevent the i915 driver from re-initializing the display if the firmware has already initialized it. Without this config, the i915 driver will initialize the display to bring up the login screen although the firmware has initialized the display using the GFX MMIO registers and framebuffer. Kernel graphics driver can avoid redundant display init by firmware, which can optimize boot time by ~15ms-30ms. Ensures hashing mode is 1x4 to enable a single pipe between Pipe A or B. Typically, internal display is on Pipe-A, so 1x4 restricts MBUS joining to internal display alone. BUG=b:284799726 TEST=Able to build and boot google/rex Change-Id: I60ae76dc783383e027e66edbcdeeb535472caeb1 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/graphics/Kconfig M src/soc/intel/common/block/graphics/graphics.c 2 files changed, 42 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/78385/1 diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig index d586fd8..30e4f8e 100644 --- a/src/soc/intel/common/block/graphics/Kconfig +++ b/src/soc/intel/common/block/graphics/Kconfig @@ -37,4 +37,24 @@ Ignore BAR0(offset 0x10)'s pre-fetchable attribute to use non-prefetchable MMIO to fix OS display driver failure. +config SOC_INTEL_GFX_MBUS_JOIN + bool + help + The MBUS (Memory Bus) is a high-speed interface that connects the graphics + controller to the system memory. It provides a dedicated data path for graphics + data, which helps to improve graphics performance. + + The MBUS is a key technology that helps to make the Intel i915 driver powerful + and versatile graphics drivers available. It provides the high-speed data transfer + capabilities that are essential for smooth and responsive graphics performance. + + Enable this config to ensure that the Intel GFX controller joins the MBUS before the + i915 driver is loaded. This is necessary to prevent the i915 driver from re-initializing + the display if the firmware has already initialized it. Without this config, the i915 + driver will initialize the display to bring up the login screen although the firmware + has initialized the display using the GFX MMIO registers and framebuffer. + + When enabled, saves 75ms-80ms of the boot time by avoiding redundent display + initialization by kernel graphics driver (i.e., i915_gfx). + endif diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 5b2484a..1173496 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -16,6 +16,12 @@ #include <soc/pci_devs.h> #include <types.h> +#define GFX_MBUS_CTL 0x4438C +#define GFX_MBUS_JOIN BIT(31) +#define GFX_MBUS_HASHING_MODE BIT(30) +#define GFX_MBUS_JOIN_PIPE_SEL (BIT(28) | BIT(27) | BIT(26)) + + /* SoC Overrides */ __weak void graphics_soc_panel_init(struct device *dev) { @@ -237,12 +243,27 @@ } } +static void graphics_dev_final(struct device *dev) +{ + pci_dev_request_bus_master(dev); + + if (CONFIG(SOC_INTEL_GFX_MBUS_JOIN)) { + uint32_t hashing_mode = 0; /* 2x2 */ + uint32_t pipe_select = 0; /* None */ + if (!get_external_display_status()) { + hashing_mode = GFX_MBUS_HASHING_MODE; /* 1x4 */ + pipe_select = GFX_MBUS_JOIN_PIPE_SEL; /* Pipe-A */ + } + graphics_gtt_rmw(GFX_MBUS_CTL, (uint32_t)(~pipe_select), GFX_MBUS_JOIN | hashing_mode); + } +} + const struct device_operations graphics_ops = { .read_resources = graphics_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_init, - .final = pci_dev_request_bus_master, + .final = graphics_dev_final, .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt = gma_generate_ssdt, -- To view, visit https://review.coreboot.org/c/coreboot/+/78385?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60ae76dc783383e027e66edbcdeeb535472caeb1 Gerrit-Change-Number: 78385 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/google/rex/var/karis: Use 2 gpio for stylus detect/wake
by Subrata Banik (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: David Wu, Eran Mitrani, Kapil Porwal, Tarun, Tyler Wang. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78336?usp=email ) Change subject: mb/google/rex/var/karis: Use 2 gpio for stylus detect/wake ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78336?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a83326f76932c8e501e6369bb845fc7236291b4 Gerrit-Change-Number: 78336 Gerrit-PatchSet: 6 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 16 Oct 2023 08:25:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Revert "soc/intel/apollolake: Correct the logic for the legacy 8254 t...
by Sean Rhodes (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Werner Zeh. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78408?usp=email ) Change subject: Revert "soc/intel/apollolake: Correct the logic for the legacy 8254 timer" ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/78408?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1dda241e91f4564cf5c756392070d704320ec58b Gerrit-Change-Number: 78408 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 16 Oct 2023 08:09:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: adapt to vboot_cbfs_integration POC
by Rizwan Qureshi (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Anil Kumar K, Eran Mitrani, Julius Werner, Kapil Porwal, Subrata Banik, Tarun. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78214?usp=email ) Change subject: adapt to vboot_cbfs_integration POC ...................................................................... Patch Set 4: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/78214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie0266e50463926b8d377825142afda7f44754eb7 Gerrit-Change-Number: 78214 Gerrit-PatchSet: 4 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 16 Oct 2023 08:03:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: acpi/acpigen: Allow general namestring in write mutex functions
by Jakub Czapiga (Code Review) 16 Oct '23

16 Oct '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78349?usp=email ) Change subject: acpi/acpigen: Allow general namestring in write mutex functions ...................................................................... acpi/acpigen: Allow general namestring in write mutex functions BUG=b:301150499 TEST=Compiled and tested on google/redrix - PERST# goes low when wwan modem goes into runtime suspend. Change-Id: Ib09d5a6091cedfce24da49390cf980414f97a2c9 Signed-off-by: Paweł Anikiel <panikiel(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78349 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland(a)gmail.com> --- M src/acpi/acpigen.c 1 file changed, 3 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 7ca4f02..ea3ef20 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -476,8 +476,7 @@ { /* MutexOp */ acpigen_emit_ext_op(MUTEX_OP); - /* NameString 4 chars only */ - acpigen_emit_simple_namestring(name); + acpigen_emit_namestring(name); acpigen_emit_byte(flags); } @@ -485,8 +484,7 @@ { /* AcquireOp */ acpigen_emit_ext_op(ACQUIRE_OP); - /* NameString 4 chars only */ - acpigen_emit_simple_namestring(name); + acpigen_emit_namestring(name); acpigen_emit_word(val); } @@ -494,8 +492,7 @@ { /* ReleaseOp */ acpigen_emit_ext_op(RELEASE_OP); - /* NameString 4 chars only */ - acpigen_emit_simple_namestring(name); + acpigen_emit_namestring(name); } static void acpigen_write_field_length(uint32_t len) -- To view, visit https://review.coreboot.org/c/coreboot/+/78349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib09d5a6091cedfce24da49390cf980414f97a2c9 Gerrit-Change-Number: 78349 Gerrit-PatchSet: 3 Gerrit-Owner: Paweł Anikiel <panikiel(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/rex/var/karis: Use 2 gpio for stylus detect/wake
by Tyler Wang (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: David Wu, Eran Mitrani, Kapil Porwal, Subrata Banik, Tarun. Tyler Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78336?usp=email ) Change subject: mb/google/rex/var/karis: Use 2 gpio for stylus detect/wake ...................................................................... Patch Set 6: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/78336?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a83326f76932c8e501e6369bb845fc7236291b4 Gerrit-Change-Number: 78336 Gerrit-PatchSet: 6 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 16 Oct 2023 07:58:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2023