coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

1 participants
3354 discussions

[XS] Change in coreboot[main]: soc/amd/common/data_fabric_helper: add pre-processor guards for ACPI
by Varshit Pandya (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Felix Held, Jason Glenesk, Matt DeVillier. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78341?usp=email ) Change subject: soc/amd/common/data_fabric_helper: add pre-processor guards for ACPI ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: same here and the next patch -- To view, visit https://review.coreboot.org/c/coreboot/+/78341?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iec6e05bbe9fad7d78002560b78169dc293294af6 Gerrit-Change-Number: 78341 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 16 Oct 2023 10:22:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: soc/amd/common/data_fabric/extended_mmio: fix compile errors
by Varshit Pandya (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Felix Held, Jason Glenesk, Matt DeVillier. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78340?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/amd/common/data_fabric/extended_mmio: fix compile errors ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: may be add the topic "amd_genoa_opensil" ? -- To view, visit https://review.coreboot.org/c/coreboot/+/78340?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5495ebf0f157fd0c456ce44acaf1ab222a188dd Gerrit-Change-Number: 78340 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 16 Oct 2023 10:21:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: superio/smsc/sch5545/acpi/superio.asl: Clear PME status bits on SCI
by Michał Żygowski (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Michał Żygowski. Hello Krystian Hebel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78351?usp=email to look at the new patch set (#2). Change subject: superio/smsc/sch5545/acpi/superio.asl: Clear PME status bits on SCI ...................................................................... superio/smsc/sch5545/acpi/superio.asl: Clear PME status bits on SCI The SCI handler for the GPE associated with the Super I/O did not clear the respective PME status bits resulting in the SCI reoccurring endlessly. The /proc/interrupts reported millions of ACPI interrupts generated in just a few minutes of uptime. The flood of interrupts caused some units to be unusable in extreme cases once attempted to boot Qubes OS for example. On systems like Qubes OS it had a huge impact on performance due to many IPCs the SCIs caused under Xen. Clear the PME bits of devices that report a PME event. Then clear the global PME status bit at the end of SCI handler to prevent the SCI from asserting again until a new event occurrs. With this change the number of ACPI interrupts generated in the first minutes of uptime settles at a few thousands. TEST=Boot Qubes OS R4.1.2 on Dell OptiPlex 9010 SFF and check /proc/interrupts in dom0 if the number of ACPI interrupts is only a few thousands. Change-Id: I64e03d268138a62b46084be41343ef7fb089dfc3 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/superio/smsc/sch5545/acpi/superio.asl 1 file changed, 25 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/78351/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78351?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64e03d268138a62b46084be41343ef7fb089dfc3 Gerrit-Change-Number: 78351 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: superio/smsc/sch5545/acpi/superio.asl: Fix UART2 device name
by Michał Żygowski (Code Review) 16 Oct '23

16 Oct '23

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78350?usp=email ) Change subject: superio/smsc/sch5545/acpi/superio.asl: Fix UART2 device name ...................................................................... superio/smsc/sch5545/acpi/superio.asl: Fix UART2 device name Due to copy-paste error, the UART2 device name is the same as UART1. Fix it. Change-Id: I796d09f321101a36731a56099af738c9485df8a2 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78350 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M src/superio/smsc/sch5545/acpi/superio.asl 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Krystian Hebel: Looks good to me, approved diff --git a/src/superio/smsc/sch5545/acpi/superio.asl b/src/superio/smsc/sch5545/acpi/superio.asl index c9a5f5a..7ef8fcf 100644 --- a/src/superio/smsc/sch5545/acpi/superio.asl +++ b/src/superio/smsc/sch5545/acpi/superio.asl @@ -470,7 +470,7 @@ #ifdef SCH5545_SHOW_UARTB #define SUPERIO_UARTB_LDN 8 - Device (UAR1) + Device (UAR2) { Name (_HID, EisaId ("PNP0501")) Name (_UID, SUPERIO_UID(SER, SUPERIO_UARTB_LDN)) -- To view, visit https://review.coreboot.org/c/coreboot/+/78350?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I796d09f321101a36731a56099af738c9485df8a2 Gerrit-Change-Number: 78350 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: Revert "soc/intel/apollolake: Correct the logic for the legacy 8254 t...
by Werner Zeh (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Sean Rhodes. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78408?usp=email ) Change subject: Revert "soc/intel/apollolake: Correct the logic for the legacy 8254 timer" ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/apollolake/chip.c: https://review.coreboot.org/c/coreboot/+/78408/comment/104ea0e7_24abac33 : PS1, Line 752: silconfig->Timer8254ClkSetting = use_8254; I am not fully sure with the revert... If I am not completely wrong the current logic is: If USE_LEGACY_8254_TIMER is not set, then clock gating is enabled. This is not terribly wrong so far but was implemented inverse for Apollo Lake. This is where the real mistake happened. What if we keep your current patch in the tree and set this switch default to yes for APL only? This way around the logic will be consistent across all platforms and there is not issue with APL because the old behavior persists. In a follow-up we could rename 'USE_LEGACY_8254_TIMER' to 'LEGACY_8254_TIMER_CLK_GATING_EN' or the like to make it clear what this switch is actually doing. What do you think? -- To view, visit https://review.coreboot.org/c/coreboot/+/78408?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1dda241e91f4564cf5c756392070d704320ec58b Gerrit-Change-Number: 78408 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 16 Oct 2023 08:51:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: soc/intel/{adl, mtl}: Avoid redundant display init by joining to MBUS
by Subrata Banik (Code Review) 16 Oct '23

16 Oct '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78387?usp=email ) Change subject: soc/intel/{adl, mtl}: Avoid redundant display init by joining to MBUS ...................................................................... soc/intel/{adl, mtl}: Avoid redundant display init by joining to MBUS This patch ensures that the IGD joins the MBUS when the firmware splash screen feature is enabled (aka BMP_LOGO config is enabled). This prevents the i915 driver from reinitializing the display, which can save up to 75ms-80ms of boot time and eliminate a brief period of blank screen between the firmware splash screen and the OS login prompt. BUG=b:284799726 TEST=Able to build and boot google/rex Change-Id: I36af167afa902053a987602d494a8830ad9b1b1a Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/meteorlake/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/78387/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 4b960c1..fcd9ebb 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -82,6 +82,7 @@ select SOC_INTEL_COMMON_RESET select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON select SOC_INTEL_CSE_SET_EOP + select SOC_INTEL_GFX_MBUS_JOIN if BMP_LOGO select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select HAVE_INTEL_COMPLIANCE_TEST_MODE select SSE2 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 590e8b8..a8332e8 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -89,6 +89,7 @@ select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_IOE_DIE_SUPPORT + select SOC_INTEL_GFX_MBUS_JOIN if BMP_LOGO select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78387?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I36af167afa902053a987602d494a8830ad9b1b1a Gerrit-Change-Number: 78387 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: libpayload: Add dma_allocator_range()
by Yi Chou (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Julius Werner, Paul Menzel, Yu-Ping Wu. Yi Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78407?usp=email ) Change subject: libpayload: Add dma_allocator_range() ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78407/comment/7d1ac93b_c4af9d7e : PS1, Line 7: dma_allocator_range > Please add (), so it’s clear it’s a function. Done https://review.coreboot.org/c/coreboot/+/78407/comment/1c4d94c8_262eba59 : PS1, Line 9: We will need this function to zero out everything allocated by the : dma allocator. > Please elaborate. […] Done File payloads/libpayload/libc/malloc.c: https://review.coreboot.org/c/coreboot/+/78407/comment/8a0165bc_06eee5fd : PS1, Line 126: void dma_allocator_range(void **start_out, size_t *size_out) : { : if (dma_initialized()) { : *start_out = dma->start; : *size_out = dma->end - dma->start; : } else { : *start_out = NULL; : *size_out = 0; : } : } > Please add a comment. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78407?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f3058dfd861ed44f716623967201b8cabe8d166 Gerrit-Change-Number: 78407 Gerrit-PatchSet: 4 Gerrit-Owner: Yi Chou <yich(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 16 Oct 2023 08:39:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: libpayload: Add dma_allocator_range()
by Yi Chou (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Julius Werner, Yi Chou, Yu-Ping Wu. Hello Julius Werner, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78407?usp=email to look at the new patch set (#4). Change subject: libpayload: Add dma_allocator_range() ...................................................................... libpayload: Add dma_allocator_range() Some sensitive data may remain DMA buffer, we will want to zero out everything on the DMA buffer before we jump into the kernel to prevent leaking sensitive data into the kernel. To accomplish that, we will need this function to get the range of memory that can be allocated by the dma allocator. BUG=b:248610274 TEST=emerge-cherry libpayload BRANCH=none Signed-off-by: Yi Chou <yich(a)google.com> Change-Id: I8f3058dfd861ed44f716623967201b8cabe8d166 --- M payloads/libpayload/include/stdlib.h M payloads/libpayload/libc/malloc.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/78407/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/78407?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f3058dfd861ed44f716623967201b8cabe8d166 Gerrit-Change-Number: 78407 Gerrit-PatchSet: 4 Gerrit-Owner: Yi Chou <yich(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yi Chou <yich(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: libpayload: Add dma_allocator_range()
by Yi Chou (Code Review) 16 Oct '23

16 Oct '23

Attention is currently required from: Julius Werner, Yi Chou, Yu-Ping Wu. Hello Julius Werner, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78407?usp=email to look at the new patch set (#3). Change subject: libpayload: Add dma_allocator_range() ...................................................................... libpayload: Add dma_allocator_range() Some sensitive data may remain on the DMA buffer, we will want to zero out everything on the DMA buffer before we jump into the kernel. To accomplish that, we will need this function to get the range of memory that can be allocated by the dma allocator. BUG=b:248610274 TEST=emerge-cherry libpayload BRANCH=none Signed-off-by: Yi Chou <yich(a)google.com> Change-Id: I8f3058dfd861ed44f716623967201b8cabe8d166 --- M payloads/libpayload/include/stdlib.h M payloads/libpayload/libc/malloc.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/78407/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/78407?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f3058dfd861ed44f716623967201b8cabe8d166 Gerrit-Change-Number: 78407 Gerrit-PatchSet: 3 Gerrit-Owner: Yi Chou <yich(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yi Chou <yich(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: drivers/intel/dptf: Add DCFG method support
by Sumeet R Pawnikar (Code Review) 16 Oct '23

16 Oct '23

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78386?usp=email ) Change subject: drivers/intel/dptf: Add DCFG method support ...................................................................... drivers/intel/dptf: Add DCFG method support After final production, it's possible that the OEM/ODM locks down thermal tuning beyond what is usually done on the given platform. In that case user space calibration tools should not try to adjust the thermal configuration of the system. By adding new DCFG (Device Configuration) method it allows the OEM/ODM to control this thermal tuning mechanism. It also gives the provision for user space to check the current mode. This method is based on BIOS specification document #640237. BUG=b:272382080 TEST=Build, boot on rex board and dump SSDT to check DCFG method. Also, verified the newly added sysfs attribute "production_mode" present under /sys/bus/platform/devices/INTC1042:00 path. Change-Id: I507c4d6eee565d39b2f42950d888d110ab94de64 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/drivers/intel/dptf/dptf.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/78386/1 diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index 71a4ec3..c1e4dfac 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -159,6 +159,16 @@ acpigen_write_method_end(); } /* \_SB.DPTF */ +static void write_dcfg_variable(void) + acpigen_write_name("DCFE"); + acpigen_emit_byte(0); + + acpigen_write_method("DCFG", 0); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("DCFE"); + acpigen_write_method_end(); +} +/* \_SB.DPTF */ static void write_oem_variables(const struct drivers_intel_dptf_config *config) { int i; @@ -520,6 +530,7 @@ } else write_fan(config, platform_info, DPTF_FAN); + write_dcfg_variable(); write_oem_variables(config); write_imok(); write_generic_devices(config, platform_info); -- To view, visit https://review.coreboot.org/c/coreboot/+/78386?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I507c4d6eee565d39b2f42950d888d110ab94de64 Gerrit-Change-Number: 78386 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2023