Attention is currently required from: Xi Chen, Rex-BC Chen, Yu-Ping Wu.
Rex-BC Chen has uploaded a new patch set (#5) to the change originally created by Hung-Te Lin. ( https://review.coreboot.org/c/coreboot/+/67359 )
Change subject: soc/mediatek: a common implementation to register BL31 reset
......................................................................
soc/mediatek: a common implementation to register BL31 reset
The implementations of register_reset_to_bl31() are the same for
MedaiTek platform, so we abstract them to soc/common/bl31.c.
BUG=None
TEST=build pass
Change-Id: I297ea2e18a6d7e92236cf415844b166523616bdf
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com>
---
M src/mainboard/google/asurada/mainboard.c
M src/mainboard/google/cherry/mainboard.c
M src/mainboard/google/corsola/mainboard.c
M src/mainboard/google/kukui/mainboard.c
A src/soc/mediatek/common/bl31.c
A src/soc/mediatek/common/include/soc/bl31.h
M src/soc/mediatek/mt8183/Makefile.inc
M src/soc/mediatek/mt8186/Makefile.inc
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8195/Makefile.inc
10 files changed, 72 insertions(+), 60 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/67359/5
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I297ea2e18a6d7e92236cf415844b166523616bdf
Gerrit-Change-Number: 67359
Gerrit-PatchSet: 5
Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com>
Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com>
Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-MessageType: newpatchset
Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu.
Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, Yidi Lin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/67355
to look at the new patch set (#5).
Change subject: soc/mediatek/mt8188: Enable mfgpll properly and fix SPMI muxes
......................................................................
soc/mediatek/mt8188: Enable mfgpll properly and fix SPMI muxes
Some of the pll settings are incorrect, which cause problems in GPU
after booting into kernel.
- MFGPLL opp_ck_en bit isn't located at MFGPLL_CON1, so we need to fix
it to enable MFGPLL properly.
- Switch SPMI clock muxes to 260M to avoid kernel hang while probing
SPMI kernel driver.
TEST=GPU bringup correctly.
BUG=b:233720142
Signed-off-by: Johnson Wang <johnson.wang(a)mediatek.com>
Change-Id: I971109a5f72e3307899daaf5a5f26022124b559b
---
M src/soc/mediatek/mt8188/pll.c
1 file changed, 24 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/67355/5
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Gerrit-Branch: master
Gerrit-Change-Id: I971109a5f72e3307899daaf5a5f26022124b559b
Gerrit-Change-Number: 67355
Gerrit-PatchSet: 5
Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org>
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Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-MessageType: newpatchset
Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67370 )
Change subject: device/pci_device: Add missing spaces to log messages
......................................................................
device/pci_device: Add missing spaces to log messages
Add the missing spaces to two log message, like the one below.
WARNING: Device PCI: 03:00.0 requests a BAR with34 bits of address space, which coreboot is notconfigured to hand out, truncating to 29 bits
Change-Id: If933d8fb0db5b58ff12f043cc73172a3f6ffc624
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
M src/device/pci_device.c
1 file changed, 18 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/67370/1
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 232328d..3828070 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -405,8 +405,8 @@
int max_requested_bits = __fls64(size_mask);
if (max_requested_bits > CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS) {
printk(BIOS_WARNING, "WARNING: Device %s requests a BAR with"
- "%u bits of address space, which coreboot is not"
- "configured to hand out, truncating to %u bits\n",
+ " %u bits of address space, which coreboot is not"
+ " configured to hand out, truncating to %u bits\n",
dev_path(dev), max_requested_bits,
CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS);
max_requested_bits = CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS;
@@ -414,8 +414,8 @@
if (!(res->flags & IORESOURCE_PCI64) && max_requested_bits > 32) {
printk(BIOS_ERR, "ERROR: Resizable BAR requested"
- "above 32 bits, but PCI function reported a"
- "32-bit BAR.");
+ " above 32 bits, but PCI function reported a"
+ " 32-bit BAR.");
return;
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If933d8fb0db5b58ff12f043cc73172a3f6ffc624
Gerrit-Change-Number: 67370
Gerrit-PatchSet: 1
Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-MessageType: newchange