coreboot-gerrit June 2022

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Change in coreboot[master]: cpu/amd: Add common helpers for TSEG and SMM
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64866 ) Change subject: cpu/amd: Add common helpers for TSEG and SMM ...................................................................... cpu/amd: Add common helpers for TSEG and SMM Change-Id: I73174766980e0405e7b8efd4f059bb400c0c0a25 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/Kconfig M src/cpu/amd/Makefile.inc M src/cpu/amd/agesa/Kconfig M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/cpu/amd/pi/Kconfig M src/cpu/amd/smm/Makefile.inc A src/cpu/amd/smm/smm_helper.c M src/soc/amd/common/block/cpu/Kconfig M src/soc/amd/common/block/cpu/noncar/memmap.c M src/soc/amd/common/block/cpu/smm/Makefile.inc M src/soc/amd/common/block/cpu/smm/finalize.c D src/soc/amd/common/block/cpu/smm/smm_helper.c M src/soc/amd/common/block/cpu/smm/smm_relocate.c M src/soc/amd/common/block/include/amdblocks/smm.h 17 files changed, 122 insertions(+), 90 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/64866/1 diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig index db8989d..0c2bd25 100644 --- a/src/cpu/amd/Kconfig +++ b/src/cpu/amd/Kconfig @@ -1,2 +1,7 @@ source "src/cpu/amd/agesa/Kconfig" source "src/cpu/amd/pi/Kconfig" + +config CPU_AMD_SMM + bool + help + Select this for SMM related functionality on AMD hardware. diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc index 5c07a66..0f44343 100644 --- a/src/cpu/amd/Makefile.inc +++ b/src/cpu/amd/Makefile.inc @@ -1,2 +1,3 @@ subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa subdirs-$(CONFIG_CPU_AMD_PI) += pi +subdirs-$(CONFIG_CPU_AMD_SMM) += smm diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 266fc89..ec97da6 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -13,6 +13,7 @@ select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select SSE2 + select CPU_AMD_SMM if CPU_AMD_AGESA diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 41fa1ef..cd7f076 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -1,14 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> #include <console/console.h> -#include <cpu/x86/msr.h> #include <cpu/amd/msr.h> -#include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> -#include <device/device.h> +#include <cpu/amd/smm.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> -#include <acpi/acpi.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <device/device.h> #include <northbridge/amd/agesa/agesa_helper.h> static void model_14_init(struct device *dev) @@ -76,9 +77,7 @@ wrmsr(NB_CFG_MSR, msr); /* Write protect SMM space with SMMLOCK. */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); + lock_smm(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index e246383..a557407 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -1,15 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> #include <console/console.h> -#include <cpu/x86/msr.h> #include <cpu/amd/msr.h> -#include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> -#include <cpu/x86/smm.h> -#include <device/device.h> +#include <cpu/amd/smm.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> -#include <acpi/acpi.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> +#include <device/device.h> #include <northbridge/amd/agesa/agesa_helper.h> static void model_15_init(struct device *dev) @@ -93,9 +94,7 @@ } /* Write protect SMM space with SMMLOCK. */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); + lock_smm(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 3c2202a..48c44f5 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -1,14 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> #include <console/console.h> -#include <cpu/x86/msr.h> #include <cpu/amd/msr.h> -#include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> -#include <device/device.h> +#include <cpu/amd/smm.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> -#include <acpi/acpi.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <device/device.h> #include <northbridge/amd/agesa/agesa_helper.h> static void model_16_init(struct device *dev) @@ -76,9 +77,7 @@ wrmsr(NB_CFG_MSR, msr); /* Write protect SMM space with SMMLOCK. */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); + lock_smm(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 1a9a2e3..9df5b73 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -3,14 +3,15 @@ #include <commonlib/helpers.h> #include <console/console.h> #include <cpu/amd/microcode.h> -#include <cpu/x86/msr.h> #include <cpu/amd/msr.h> -#include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> -#include <device/device.h> -#include <device/pci.h> +#include <cpu/amd/smm.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <device/device.h> +#include <device/pci.h> #include <smp/node.h> static void model_16_init(struct device *dev) @@ -44,9 +45,7 @@ wrmsr(NB_CFG_MSR, msr); /* Write protect SMM space with SMMLOCK. */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); + lock_smm(); amd_update_microcode_from_cbfs(); diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 2336d68..99815d3 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -12,6 +12,7 @@ select SPI_FLASH if HAVE_ACPI_RESUME select NO_SMM select SSE2 + select CPU_AMD_SMM if CPU_AMD_PI diff --git a/src/cpu/amd/smm/Makefile.inc b/src/cpu/amd/smm/Makefile.inc index 97a6694..87cbb38 100644 --- a/src/cpu/amd/smm/Makefile.inc +++ b/src/cpu/amd/smm/Makefile.inc @@ -1,2 +1,3 @@ - +romstage-y += smm_helper.c +ramstage-y += smm_helper.c ramstage-y += smm_init.c diff --git a/src/cpu/amd/smm/smm_helper.c b/src/cpu/amd/smm/smm_helper.c new file mode 100644 index 0000000..06ad735 --- /dev/null +++ b/src/cpu/amd/smm/smm_helper.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/cpu.h> +#include <assert.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/amd/msr.h> +#include <cpu/amd/smm.h> +#include <cpu/amd/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> +#include <cpu/x86/mp.h> +#include <cpu/x86/mtrr.h> +#include <stdint.h> +#include <cpu/amd/amd64_save_state.h> + +/* + * For data stored in TSEG, ensure TValid is clear so R/W access can reach + * the DRAM when not in SMM. + */ +void clear_tvalid(void) +{ + msr_t hwcr = rdmsr(HWCR_MSR); + msr_t mask = rdmsr(SMM_MASK_MSR); + int tvalid = !!(mask.lo & SMM_TSEG_VALID); + + if (hwcr.lo & SMM_LOCK) { + if (!tvalid) /* not valid but locked means still accessible */ + return; + + printk(BIOS_ERR, "can't clear TValid, already locked\n"); + return; + } + + mask.lo &= ~SMM_TSEG_VALID; + wrmsr(SMM_MASK_MSR, mask); +} + +void setup_tseg(void) +{ + uintptr_t tseg_base; + size_t tseg_size; + + smm_region(&tseg_base, &tseg_size); + + msr_t msr; + msr.lo = tseg_base; + /* Let's assume TSEG < 4G for now. */ + msr.hi = 0; + wrmsr(SMM_BASE_MSR, msr); + + msr.lo = ~(tseg_size - 1); + msr.lo |= SMM_TSEG_WB; + msr.hi = (1 << (cpu_phys_address_size() - 32)) - 1; + wrmsr(SMM_MASK_MSR, msr); +} + +void tseg_valid(void) +{ + msr_t mask = rdmsr(SMM_MASK_MSR); + mask.lo |= SMM_TSEG_VALID; + + wrmsr(SMM_MASK_MSR, mask); +} + +void lock_smm(void) +{ + msr_t hwcr = rdmsr(HWCR_MSR); + hwcr.lo |= SMM_LOCK; + wrmsr(HWCR_MSR, hwcr); +} diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 56e922d..b7468bb 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -82,3 +82,6 @@ depends on SOC_AMD_COMMON_BLOCK_UCODE help Defines the size of the uCode binary in bytes. + +config CPU_AMD_SMM + default y diff --git a/src/soc/amd/common/block/cpu/noncar/memmap.c b/src/soc/amd/common/block/cpu/noncar/memmap.c index dd057c0..6899b11 100644 --- a/src/soc/amd/common/block/cpu/noncar/memmap.c +++ b/src/soc/amd/common/block/cpu/noncar/memmap.c @@ -4,6 +4,7 @@ #include <amdblocks/smm.h> #include <console/console.h> #include <cbmem.h> +#include <cpu/amd/smm.h> #include <cpu/amd/msr.h> #include <cpu/x86/smm.h> #include <fsp/util.h> diff --git a/src/soc/amd/common/block/cpu/smm/Makefile.inc b/src/soc/amd/common/block/cpu/smm/Makefile.inc index 5694d1d..cdb0efb 100644 --- a/src/soc/amd/common/block/cpu/smm/Makefile.inc +++ b/src/soc/amd/common/block/cpu/smm/Makefile.inc @@ -1,10 +1,7 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMM),y) -romstage-y += smm_helper.c -postcar-y += smm_helper.c ramstage-y += finalize.c ramstage-y += smm_relocate.c -ramstage-y += smm_helper.c smm-y += smi_apmc_helper.c smm-y += smi_handler.c diff --git a/src/soc/amd/common/block/cpu/smm/finalize.c b/src/soc/amd/common/block/cpu/smm/finalize.c index 73b2121..08d93ea 100644 --- a/src/soc/amd/common/block/cpu/smm/finalize.c +++ b/src/soc/amd/common/block/cpu/smm/finalize.c @@ -1,31 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <cpu/x86/mp.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/msr.h> +#include <amdblocks/acpi.h> #include <bootstate.h> #include <console/console.h> -#include <amdblocks/acpi.h> +#include <cpu/amd/msr.h> +#include <cpu/amd/smm.h> +#include <cpu/x86/mp.h> +#include <cpu/x86/msr.h> #include <types.h> static void per_core_finalize(void *unused) { - msr_t hwcr, mask; + msr_t hwcr; /* Finalize SMM settings */ hwcr = rdmsr(HWCR_MSR); if (hwcr.lo & SMM_LOCK) /* Skip if already locked, avoid GPF */ return; - if (CONFIG(HAVE_SMI_HANDLER)) { - mask = rdmsr(SMM_MASK_MSR); - mask.lo |= SMM_TSEG_VALID; - wrmsr(SMM_MASK_MSR, mask); - } + if (CONFIG(HAVE_SMI_HANDLER)) + tseg_valid(); - hwcr.lo |= SMM_LOCK; - wrmsr(HWCR_MSR, hwcr); + lock_smm(); } static void finalize_cores(void) diff --git a/src/soc/amd/common/block/cpu/smm/smm_helper.c b/src/soc/amd/common/block/cpu/smm/smm_helper.c deleted file mode 100644 index ce80f16..0000000 --- a/src/soc/amd/common/block/cpu/smm/smm_helper.c +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/smm.h> -#include <console/console.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/msr.h> - -/* - * For data stored in TSEG, ensure TValid is clear so R/W access can reach - * the DRAM when not in SMM. - */ -void clear_tvalid(void) -{ - msr_t hwcr = rdmsr(HWCR_MSR); - msr_t mask = rdmsr(SMM_MASK_MSR); - int tvalid = !!(mask.lo & SMM_TSEG_VALID); - - if (hwcr.lo & SMM_LOCK) { - if (!tvalid) /* not valid but locked means still accessible */ - return; - - printk(BIOS_ERR, "can't clear TValid, already locked\n"); - return; - } - - mask.lo &= ~SMM_TSEG_VALID; - wrmsr(SMM_MASK_MSR, mask); -} diff --git a/src/soc/amd/common/block/cpu/smm/smm_relocate.c b/src/soc/amd/common/block/cpu/smm/smm_relocate.c index 11195d8..113b4c4 100644 --- a/src/soc/amd/common/block/cpu/smm/smm_relocate.c +++ b/src/soc/amd/common/block/cpu/smm/smm_relocate.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <cpu/amd/amd64_save_state.h> #include <cpu/amd/msr.h> +#include <cpu/amd/smm.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> @@ -34,23 +35,9 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) { + setup_tseg(); + amd64_smm_state_save_area_t *smm_state; - - uintptr_t tseg_base; - size_t tseg_size; - - smm_region(&tseg_base, &tseg_size); - - msr_t msr; - msr.lo = tseg_base; - msr.hi = 0; - wrmsr(SMM_ADDR_MSR, msr); - - msr.lo = ~(tseg_size - 1); - msr.lo |= SMM_TSEG_WB; - msr.hi = (1 << (cpu_phys_address_size() - 32)) - 1; - wrmsr(SMM_MASK_MSR, relo_params->tseg_mask); - smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); smm_state->smbase = staggered_smbase; } diff --git a/src/soc/amd/common/block/include/amdblocks/smm.h b/src/soc/amd/common/block/include/amdblocks/smm.h index 9124607..732dc5c 100644 --- a/src/soc/amd/common/block/include/amdblocks/smm.h +++ b/src/soc/amd/common/block/include/amdblocks/smm.h @@ -11,7 +11,6 @@ void *get_smi_source_handler(int source); void handle_smi_gsmi(void); void handle_smi_store(void); -void clear_tvalid(void); /* See SMITYPE_* for list possible of events. GEVENTS are handled with mainboard_smi_gpi. */ void mainboard_handle_smi(int event); -- To view, visit https://review.coreboot.org/c/coreboot/+/64866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73174766980e0405e7b8efd4f059bb400c0c0a25 Gerrit-Change-Number: 64866 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/smm_relocate.c: Improve TSEG programming
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

1 0

Change in coreboot[master]: amdblocks/smm.h: Add header guards
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64864 ) Change subject: amdblocks/smm.h: Add header guards ...................................................................... amdblocks/smm.h: Add header guards Change-Id: I5d01c36fa4695ee42d18701a90d1b96bceb5045f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/include/amdblocks/smm.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/64864/1 diff --git a/src/soc/amd/common/block/include/amdblocks/smm.h b/src/soc/amd/common/block/include/amdblocks/smm.h index 46008fa..4a44203 100644 --- a/src/soc/amd/common/block/include/amdblocks/smm.h +++ b/src/soc/amd/common/block/include/amdblocks/smm.h @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _AMDBLOCKS_SMM_H_ +#define _AMDBLOCKS_SMM_H_ + #include <cpu/x86/msr.h> #include <types.h> @@ -16,3 +19,5 @@ void clear_tvalid(void); /* See SMITYPE_* for list possible of events. GEVENTS are handled with mainboard_smi_gpi. */ void mainboard_handle_smi(int event); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/64864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d01c36fa4695ee42d18701a90d1b96bceb5045f Gerrit-Change-Number: 64864 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/skyrim/var/skyrim: Add audio codec and amp support
by reddysujith (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: V sujith kumar Reddy, Raul Rangel, Ian Feng, Chris Wang, Karthik Ramasubramanian. reddysujith has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63779 ) Change subject: mb/google/skyrim/var/skyrim: Add audio codec and amp support ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/skyrim/variants/skyrim/overridetree.cb: https://review.coreboot.org/c/coreboot/+/63779/comment/c82cfc38_5a3d5705 PS4, Line 174: ACPI_GPIO_IRQ_LEVEL_LOW > I use fw_config to differentiate the two audio codec setting. […] This is codec requirement on states( LEVEL_LOW and EDGE_BOTH). we can check this in the below links https://elixir.bootlin.com/linux/latest/source/sound/soc/codecs/rt5682s.c#L… https://elixir.bootlin.com/linux/latest/source/sound/soc/codecs/nau8825.c#L… -- To view, visit https://review.coreboot.org/c/coreboot/+/63779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36d7b5c4e88825ceaa6922d9e3bed366f55a0d81 Gerrit-Change-Number: 63779 Gerrit-PatchSet: 4 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: V sujith kumar Reddy <vsujithkumar.reddy(a)amd.corp-partner.google.com> Gerrit-Reviewer: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-CC: reddysujith Gerrit-Attention: V sujith kumar Reddy <vsujithkumar.reddy(a)amd.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 12:54:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Add SBOM (Software Bill of Materials) Generation
by Maximilian Brune (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Felix Singer, Nico Huber, Martin L Roth, Paul Menzel, Angel Pons. Hello build bot (Jenkins), Nico Huber, Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63639 to look at the new patch set (#30). Change subject: Add SBOM (Software Bill of Materials) Generation ...................................................................... Add SBOM (Software Bill of Materials) Generation Firmware is most of the time just one final Image that get's flashed. since this final image consists of binaries/code from a vast amount of different people/companies, it's hard to actually determine all the small parts included in it. the goal is to take a firmware image and easily find out what it consists of. basically answering the question: who supplied the code that's running on my system right now? for example buyers can use an SBOM to perform an automated vulnerability check or license analysis, both of which can be used to evaluate risk in a product. Furthermore one can check fast if the firmware is exposed to a new vulnerability included in one of the software parts (with the specified version) of the firmware. further reference: https://blogs.gnome.org/hughsie/2022/03/10/ firmware-software-bill-of-materials/ - Add Makefile.inc to generate and build coswid tags - Add templates for most payloads, coreboot, intel-microcode and intel-management engine - Add Kconfig entries to optionaly add coswid tags for payloads, coreboot, intel microcode and intel mangement engine - Add CBFS entry called SBOM to each build via Makefile.inc - Add goswid utility tool to generate SBOM data Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Icb7481d4903f95d200eddbfed7728fbec51819d0 --- M .gitmodules M Makefile.inc M src/Kconfig A src/sbom/Kconfig A src/sbom/Makefile.inc A src/sbom/coreboot.json.src A src/sbom/intel-me.json.src A src/sbom/intel-microcode.json.src A src/sbom/payload-BOOTBOOT.json.src A src/sbom/payload-FILO.json.src A src/sbom/payload-GRUB2.json.src A src/sbom/payload-LinuxBoot.json.src A src/sbom/payload-SeaBIOS.json.src A src/sbom/payload-U-Boot.json.src A src/sbom/payload-Yabits.json.src A src/sbom/payload-depthcharge.json.src A src/sbom/payload-iPXE.json.src A src/sbom/payload-skiboot.json.src A util/goswid M util/testing/Makefile.inc 20 files changed, 479 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/63639/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/63639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb7481d4903f95d200eddbfed7728fbec51819d0 Gerrit-Change-Number: 63639 Gerrit-PatchSet: 30 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)tutanota.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)tutanota.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/corsola: Add new board 'steelix'
by zanxi chen (Code Review) 01 Jun '22

01 Jun '22

zanxi chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64789 ) Change subject: mb/google/corsola: Add new board 'steelix' ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/64789/comment/45892272_8707f60a PS1, Line 11: 232195941 > Done Hi yuping, could you please help trigger merge today? I will upload other coreboot CL for steelix after this merged. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/64789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd2ed1404cde72ecdb6cc3a262e793a6272aa871 Gerrit-Change-Number: 64789 Gerrit-PatchSet: 2 Gerrit-Owner: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Knox Chiou <knoxchiou(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wen zhang <zhangwen6(a)huaqin.corp-partner.google.com> Gerrit-CC: Yuqing Huang <huangyuqing(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 12:19:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/fsp2_0: Disable NULL deref code when calling FSP
by Sean Rhodes (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Paul Menzel, Mario Scheithauer, Arthur Heymans, Andrey Petrov. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64426 ) Change subject: driver/intel/fsp2_0: Disable NULL deref code when calling FSP ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia49dde68d45b71e231aaf32a0e6fd847f0e06146 Gerrit-Change-Number: 64426 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 12:11:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm_module_loader: Use struct region in cpu map
by Kyösti Mälkki (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Arthur Heymans. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64609 ) Change subject: cpu/x86/smm_module_loader: Use struct region in cpu map ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffa36ccb89c36401d3856b24364216e83ca35f91 Gerrit-Change-Number: 64609 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 01 Jun 2022 12:06:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [VERY WIP]tests/cpu/x86/smm: Add unit tests
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63560 ) Change subject: [VERY WIP]tests/cpu/x86/smm: Add unit tests ...................................................................... Patch Set 23: Verified-1 (10 comments) File tests/cpu/x86/smm/smm_loader.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150325): https://review.coreboot.org/c/coreboot/+/63560/comment/a21d91f1_5089c391 PS23, Line 54: #define setup_rmodule(mod , c) \ space prohibited before that ',' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150325): https://review.coreboot.org/c/coreboot/+/63560/comment/7e8df1c2_39b057fa PS23, Line 54: #define setup_rmodule(mod , c) \ macros should not use a trailing semicolon Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150325): https://review.coreboot.org/c/coreboot/+/63560/comment/2839806b_a42668f9 PS23, Line 59: hdr->payload_begin_offset = (uintptr_t)(stub_module->program) - (uintptr_t)stub_module; \ line length of 97 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150325): https://review.coreboot.org/c/coreboot/+/63560/comment/d2251b4f_ed5fec63 PS23, Line 66: hdr->parameters_begin = (uintptr_t)&stub_module->params - (uintptr_t)stub_module->program; \ line length of 100 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150325): https://review.coreboot.org/c/coreboot/+/63560/comment/9238ccad_f192738a PS23, Line 80: /* hdr->payload_begin_offset = (uintptr_t)(stub_module->program) - (uintptr_t)stub_module; */ line length of 101 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150325): https://review.coreboot.org/c/coreboot/+/63560/comment/21120a4e_2ee8973a PS23, Line 87: /* hdr->parameters_begin = (uintptr_t)&stub_module->params - (uintptr_t)stub_module->program ; */ line length of 105 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150325): https://review.coreboot.org/c/coreboot/+/63560/comment/42349a41_3d8ad240 PS23, Line 93: /* stub_module->program[i] = stub_string[i % sizeof(stub_string)]; */ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150325): https://review.coreboot.org/c/coreboot/+/63560/comment/09f35fa4_91690a97 PS23, Line 106: hdr->payload_begin_offset = (uintptr_t)(handler_module->program) - (uintptr_t)handler_module; line length of 101 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150325): https://review.coreboot.org/c/coreboot/+/63560/comment/92763f78_92998dbc PS23, Line 107: hdr->payload_end_offset = (uintptr_t)(handler_module->program) - (uintptr_t)handler_module + sizeof(handler_module->program); line length of 133 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150325): https://review.coreboot.org/c/coreboot/+/63560/comment/b5118a1d_06809f94 PS23, Line 113: hdr->parameters_begin = (uintptr_t)&handler_module->params - (uintptr_t)handler_module->program; line length of 104 exceeds 96 columns -- To view, visit https://review.coreboot.org/c/coreboot/+/63560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7462fa6155b8f8085256a027692cbead0ca3f08e Gerrit-Change-Number: 63560 Gerrit-PatchSet: 23 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 01 Jun 2022 12:04:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm_module_loader: Drop superfluous checks
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63480 ) Change subject: cpu/x86/smm_module_loader: Drop superfluous checks ...................................................................... Patch Set 23: (1 comment) File src/cpu/x86/smm/smm_module_loader.c: https://review.coreboot.org/c/coreboot/+/63480/comment/4db538a3_c6556d98 PS22, Line 294: smm_stub_place_staggered_entry_points(params); > Potential follow-up: > > if (params->num_concurrent_save_states > 1) > smm_place_entry_code(params->num_concurrent_save_states); I did that in the function. -- To view, visit https://review.coreboot.org/c/coreboot/+/63480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I275d5dda9c69cc89608450ae27dd5dbd581e3595 Gerrit-Change-Number: 63480 Gerrit-PatchSet: 23 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 12:03:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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