coreboot-gerrit June 2022

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Change in coreboot[master]: amdblocks/smm.h: Add header guards
by Fred Reitberger (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Arthur Heymans, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64864 ) Change subject: amdblocks/smm.h: Add header guards ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/include/amdblocks/smm.h: https://review.coreboot.org/c/coreboot/+/64864/comment/ca1f9476_1f0bc4b0 PS1, Line 3: _AMDBLOCKS_SMM_H_ Is there a standard format for the header guards? Looking over other headers in this folder, most are in the form "AMD_BLOCK_foo_H" -- To view, visit https://review.coreboot.org/c/coreboot/+/64864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d01c36fa4695ee42d18701a90d1b96bceb5045f Gerrit-Change-Number: 64864 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 01 Jun 2022 13:05:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdblocks/smm.h: Add header guards
by Fred Reitberger (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Arthur Heymans, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64864 ) Change subject: amdblocks/smm.h: Add header guards ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d01c36fa4695ee42d18701a90d1b96bceb5045f Gerrit-Change-Number: 64864 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 01 Jun 2022 12:57:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/amd/smm: Move MP & SMM init in a common place
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64870 ) Change subject: cpu/amd/smm: Move MP & SMM init in a common place ...................................................................... Patch Set 1: (1 comment) File src/cpu/amd/smm/smm_helper.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150333): https://review.coreboot.org/c/coreboot/+/64870/comment/25e66519_ddec302a PS1, Line 88: static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) line length of 98 exceeds 96 columns -- To view, visit https://review.coreboot.org/c/coreboot/+/64870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c457ab69581f8c29f2d79c054ca3bc7e58a896e Gerrit-Change-Number: 64870 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 01 Jun 2022 12:57:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: Do SMM relocation via MSR
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Kyösti Mälkki, Fred Reitberger, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64498 ) Change subject: soc/amd: Do SMM relocation via MSR ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: CB:64872 is an alternative -- To view, visit https://review.coreboot.org/c/coreboot/+/64498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31d4d4ae20e09da5739b6bf56e7b66857b4f1afe Gerrit-Change-Number: 64498 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 01 Jun 2022 12:55:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: Do SMM relocation via MSR
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

1 0

Change in coreboot[master]: cpu/amd: Move locking SMM as part of SMM init
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

1 0

Change in coreboot[master]: cpu/amd/smm: Move MP & SMM init in a common place
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64870 ) Change subject: cpu/amd/smm: Move MP & SMM init in a common place ...................................................................... cpu/amd/smm: Move MP & SMM init in a common place Change-Id: I7c457ab69581f8c29f2d79c054ca3bc7e58a896e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/smm/smm_helper.c M src/soc/amd/cezanne/cpu.c M src/soc/amd/common/block/cpu/smm/Makefile.inc D src/soc/amd/common/block/cpu/smm/smm_relocate.c M src/soc/amd/common/block/include/amdblocks/smm.h M src/soc/amd/picasso/cpu.c M src/soc/amd/sabrina/cpu.c M src/soc/amd/stoneyridge/cpu.c 8 files changed, 64 insertions(+), 156 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/64870/1 diff --git a/src/cpu/amd/smm/smm_helper.c b/src/cpu/amd/smm/smm_helper.c index 06ad735..82fd423 100644 --- a/src/cpu/amd/smm/smm_helper.c +++ b/src/cpu/amd/smm/smm_helper.c @@ -36,7 +36,7 @@ wrmsr(SMM_MASK_MSR, mask); } -void setup_tseg(void) +static void setup_tseg(void) { uintptr_t tseg_base; size_t tseg_size; @@ -69,3 +69,58 @@ hwcr.lo |= SMM_LOCK; wrmsr(HWCR_MSR, hwcr); } + +static void pre_mp_init(void) +{ + const msr_t syscfg = rdmsr(SYSCFG_MSR); + if (!(syscfg.lo & SYSCFG_MSR_TOM2WB)) + x86_setup_mtrrs_with_detect_no_above_4gb(); + else + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); +} + +static int get_cpu_count(void) +{ + return 1 + (cpuid_ecx(0x80000008) & 0xff); +} + +static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) +{ + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + uintptr_t tseg_base; + size_t tseg_size; + + smm_region(&tseg_base, &tseg_size); + + if (!IS_ALIGNED(tseg_base, tseg_size)) { + printk(BIOS_ERR, "TSEG base not aligned to TSEG size\n"); + return; + } + if (tseg_size < (1 << 17)) { + printk(BIOS_ERR, "TSEG size too small\n"); + return; + } + + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); +} + +static void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) +{ + setup_tseg(); + + amd64_smm_state_save_area_t *smm_state; + smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); + smm_state->smbase = staggered_smbase; +} + +const struct mp_ops amd_mp_ops_with_smm = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, + .get_smm_info = get_smm_info, + .relocation_handler = smm_relocation_handler, + .post_mp_init = global_smi_enable, +}; diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index 1e2611f..2b03796 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -23,34 +23,10 @@ /* MP and SMM loading initialization */ -/* - * Do essential initialization tasks before APs can be fired up - - * - * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This - * creates the MTRR solution that the APs will use. Otherwise APs will try to - * apply the incomplete solution as the BSP is calculating it. - */ -static void pre_mp_init(void) -{ - const msr_t syscfg = rdmsr(SYSCFG_MSR); - if (!(syscfg.lo & SYSCFG_MSR_TOM2WB)) - x86_setup_mtrrs_with_detect_no_above_4gb(); - else - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); -} - -static const struct mp_ops mp_ops = { - .pre_mp_init = pre_mp_init, - .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, - .relocation_handler = smm_relocation_handler, - .post_mp_init = global_smi_enable, -}; - void mp_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) + extern const struct mp_ops amd_mp_ops_with_smm; + if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS) die_with_post_code(POST_HW_INIT_FAILURE, "mp_init_with_smm failed. Halting.\n"); diff --git a/src/soc/amd/common/block/cpu/smm/Makefile.inc b/src/soc/amd/common/block/cpu/smm/Makefile.inc index cdb0efb..2022194 100644 --- a/src/soc/amd/common/block/cpu/smm/Makefile.inc +++ b/src/soc/amd/common/block/cpu/smm/Makefile.inc @@ -1,7 +1,6 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMM),y) ramstage-y += finalize.c -ramstage-y += smm_relocate.c smm-y += smi_apmc_helper.c smm-y += smi_handler.c diff --git a/src/soc/amd/common/block/cpu/smm/smm_relocate.c b/src/soc/amd/common/block/cpu/smm/smm_relocate.c deleted file mode 100644 index 113b4c4..0000000 --- a/src/soc/amd/common/block/cpu/smm/smm_relocate.c +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/smm.h> -#include <console/console.h> -#include <cpu/amd/amd64_save_state.h> -#include <cpu/amd/msr.h> -#include <cpu/amd/smm.h> -#include <cpu/cpu.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/smm.h> -#include <types.h> - -void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - uintptr_t tseg_base; - size_t tseg_size; - - smm_region(&tseg_base, &tseg_size); - - if (!IS_ALIGNED(tseg_base, tseg_size)) { - printk(BIOS_ERR, "TSEG base not aligned to TSEG size\n"); - return; - } - if (tseg_size < (1 << 17)) { - printk(BIOS_ERR, "TSEG size too small\n"); - return; - } - - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); -} - -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) -{ - setup_tseg(); - - amd64_smm_state_save_area_t *smm_state; - smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} diff --git a/src/soc/amd/common/block/include/amdblocks/smm.h b/src/soc/amd/common/block/include/amdblocks/smm.h index 732dc5c..011fcb5 100644 --- a/src/soc/amd/common/block/include/amdblocks/smm.h +++ b/src/soc/amd/common/block/include/amdblocks/smm.h @@ -6,8 +6,6 @@ #include <cpu/x86/msr.h> #include <types.h> -void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); void *get_smi_source_handler(int source); void handle_smi_gsmi(void); void handle_smi_store(void); diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 02956aa..9d42c1a 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -27,34 +27,10 @@ /* MP and SMM loading initialization. */ -/* - * Do essential initialization tasks before APs can be fired up - - * - * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This - * creates the MTRR solution that the APs will use. Otherwise APs will try to - * apply the incomplete solution as the BSP is calculating it. - */ -static void pre_mp_init(void) -{ - const msr_t syscfg = rdmsr(SYSCFG_MSR); - if (!(syscfg.lo & SYSCFG_MSR_TOM2WB)) - x86_setup_mtrrs_with_detect_no_above_4gb(); - else - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); -} - -static const struct mp_ops mp_ops = { - .pre_mp_init = pre_mp_init, - .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, - .relocation_handler = smm_relocation_handler, - .post_mp_init = global_smi_enable, -}; - void mp_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) + extern const struct mp_ops amd_mp_ops_with_smm; + if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS) die_with_post_code(POST_HW_INIT_FAILURE, "mp_init_with_smm failed. Halting.\n"); diff --git a/src/soc/amd/sabrina/cpu.c b/src/soc/amd/sabrina/cpu.c index e801cea..c76fee7 100644 --- a/src/soc/amd/sabrina/cpu.c +++ b/src/soc/amd/sabrina/cpu.c @@ -26,34 +26,10 @@ /* MP and SMM loading initialization */ -/* - * Do essential initialization tasks before APs can be fired up - - * - * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This - * creates the MTRR solution that the APs will use. Otherwise APs will try to - * apply the incomplete solution as the BSP is calculating it. - */ -static void pre_mp_init(void) -{ - const msr_t tom2 = rdmsr(MSR_TOM2); - if (!(tom2.lo & SYSCFG_MSR_TOM2WB)) - x86_setup_mtrrs_with_detect_no_above_4gb(); - else - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); -} - -static const struct mp_ops mp_ops = { - .pre_mp_init = pre_mp_init, - .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, - .relocation_handler = smm_relocation_handler, - .post_mp_init = global_smi_enable, -}; - void mp_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) + extern const struct mp_ops amd_mp_ops_with_smm; + if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS) die_with_post_code(POST_HW_INIT_FAILURE, "mp_init_with_smm failed. Halting.\n"); diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index b5373bc..4791e39 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -24,39 +24,10 @@ * MP and SMM loading initialization. */ -/* - * Do essential initialization tasks before APs can be fired up - - * - * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This - * creates the MTRR solution that the APs will use. Otherwise APs will try to - * apply the incomplete solution as the BSP is calculating it. - */ -static void pre_mp_init(void) -{ - const msr_t syscfg = rdmsr(SYSCFG_MSR); - if (!(syscfg.lo & SYSCFG_MSR_TOM2WB)) - x86_setup_mtrrs_with_detect_no_above_4gb(); - else - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); -} - -static int get_cpu_count(void) -{ - return 1 + (cpuid_ecx(0x80000008) & 0xff); -} - -static const struct mp_ops mp_ops = { - .pre_mp_init = pre_mp_init, - .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, - .relocation_handler = smm_relocation_handler, - .post_mp_init = global_smi_enable, -}; - void mp_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) + extern const struct mp_ops amd_mp_ops_with_smm; + if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS) die_with_post_code(POST_HW_INIT_FAILURE, "mp_init_with_smm failed. Halting.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/64870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c457ab69581f8c29f2d79c054ca3bc7e58a896e Gerrit-Change-Number: 64870 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge: Align get_cpu_count to other targets
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Marshall Dawson, Felix Held. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64869 ) Change subject: soc/amd/stoneyridge: Align get_cpu_count to other targets ...................................................................... soc/amd/stoneyridge: Align get_cpu_count to other targets The CPUID function to get the number of cores on a package is common across multiple generations of AMD cpus. Change-Id: I28bff875ea2df7837e4495787cf8a4c2d522d43d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/stoneyridge/cpu.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/64869/1 diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index b14b375..b5373bc 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -43,7 +43,7 @@ static int get_cpu_count(void) { - return (pci_read_config16(SOC_HT_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK) + 1; + return 1 + (cpuid_ecx(0x80000008) & 0xff); } static const struct mp_ops mp_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/64869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28bff875ea2df7837e4495787cf8a4c2d522d43d Gerrit-Change-Number: 64869 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/*: Make mtrr decision based on syscfg
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

1 0

Change in coreboot[master]: soc/amd/*: Move apm call out of MP init code
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

1 0

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coreboot-gerrit June 2022