coreboot-gerrit June 2022

coreboot-gerrit@coreboot.org

1 participants
1234 discussions

Change in coreboot[master]: cpu/amd/smm: Move MP & SMM init in a common place
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64870 to look at the new patch set (#3). Change subject: cpu/amd/smm: Move MP & SMM init in a common place ...................................................................... cpu/amd/smm: Move MP & SMM init in a common place Change-Id: I7c457ab69581f8c29f2d79c054ca3bc7e58a896e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/smm/smm_helper.c M src/include/cpu/amd/smm.h M src/soc/amd/cezanne/cpu.c M src/soc/amd/common/block/cpu/smm/Makefile.inc D src/soc/amd/common/block/cpu/smm/smm_relocate.c M src/soc/amd/common/block/include/amdblocks/smm.h M src/soc/amd/picasso/cpu.c M src/soc/amd/sabrina/cpu.c M src/soc/amd/stoneyridge/cpu.c 9 files changed, 68 insertions(+), 188 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/64870/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/64870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c457ab69581f8c29f2d79c054ca3bc7e58a896e Gerrit-Change-Number: 64870 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/stoneyridge: Align get_cpu_count to other targets
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Marshall Dawson, Felix Held. Hello Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64869 to look at the new patch set (#3). Change subject: soc/amd/stoneyridge: Align get_cpu_count to other targets ...................................................................... soc/amd/stoneyridge: Align get_cpu_count to other targets The CPUID function to get the number of cores on a package is common across multiple generations of AMD cpus. Change-Id: I28bff875ea2df7837e4495787cf8a4c2d522d43d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/stoneyridge/cpu.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/64869/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/64869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28bff875ea2df7837e4495787cf8a4c2d522d43d Gerrit-Change-Number: 64869 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/*: Make mtrr decision based on syscfg
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64868 to look at the new patch set (#3). Change subject: soc/amd/*: Make mtrr decision based on syscfg ...................................................................... soc/amd/*: Make mtrr decision based on syscfg The syscfg has to option to automatically mark the range between 4G and TOM2, which contains DRAM, as WB. Making it generally not necessary to allocate MTRRs for memory above 4G if no PCI BARs are placed up there. Change-Id: Ifbacae28e272ab2f39f268ad034354a9c590d035 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/cezanne/cpu.c M src/soc/amd/picasso/cpu.c M src/soc/amd/sabrina/cpu.c M src/soc/amd/stoneyridge/cpu.c 4 files changed, 41 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/64868/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/64868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbacae28e272ab2f39f268ad034354a9c590d035 Gerrit-Change-Number: 64868 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/*: Move apm call out of MP init code
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64867 to look at the new patch set (#3). Change subject: soc/amd/*: Move apm call out of MP init code ...................................................................... soc/amd/*: Move apm call out of MP init code This makes it easier to have common code for MP init on AMD systems. Change-Id: Icb6808edf96a17ec0b3073ba2486b3345a4a66ea Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/cezanne/cpu.c M src/soc/amd/picasso/cpu.c M src/soc/amd/sabrina/cpu.c 3 files changed, 17 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/64867/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/64867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb6808edf96a17ec0b3073ba2486b3345a4a66ea Gerrit-Change-Number: 64867 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/amd: Add common helpers for TSEG and SMM
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64866 to look at the new patch set (#3). Change subject: cpu/amd: Add common helpers for TSEG and SMM ...................................................................... cpu/amd: Add common helpers for TSEG and SMM Change-Id: I73174766980e0405e7b8efd4f059bb400c0c0a25 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/Kconfig M src/cpu/amd/Makefile.inc M src/cpu/amd/agesa/Kconfig M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/cpu/amd/pi/Kconfig M src/cpu/amd/smm/Makefile.inc A src/cpu/amd/smm/smm_helper.c A src/include/cpu/amd/smm.h M src/soc/amd/common/block/cpu/Kconfig M src/soc/amd/common/block/cpu/noncar/memmap.c M src/soc/amd/common/block/cpu/smm/Makefile.inc M src/soc/amd/common/block/cpu/smm/finalize.c D src/soc/amd/common/block/cpu/smm/smm_helper.c M src/soc/amd/common/block/cpu/smm/smm_relocate.c M src/soc/amd/common/block/include/amdblocks/smm.h M src/soc/amd/stoneyridge/memmap.c 19 files changed, 134 insertions(+), 91 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/64866/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/64866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73174766980e0405e7b8efd4f059bb400c0c0a25 Gerrit-Change-Number: 64866 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/smm_relocate.c: Improve TSEG programming
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64865 to look at the new patch set (#2). Change subject: soc/amd/smm_relocate.c: Improve TSEG programming ...................................................................... soc/amd/smm_relocate.c: Improve TSEG programming TSEG does not need to be aligned to 128KiB but to it's size, as the MSR work like an MTRR. 128K is a minimum TSEG size however. Change-Id: I30854111bb47f0cb14b07f71cedacd629432e0f4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/cpu/smm/smm_relocate.c M src/soc/amd/common/block/include/amdblocks/smm.h 2 files changed, 25 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/64865/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30854111bb47f0cb14b07f71cedacd629432e0f4 Gerrit-Change-Number: 64865 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Enable thermal hardware reset for MT8192 and MT8195
by Yu-Ping Wu (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Xi Chen, Hung-Te Lin, Yidi Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64861 ) Change subject: soc/mediatek: Enable thermal hardware reset for MT8192 and MT8195 ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/mt8192/bootblock.c: https://review.coreboot.org/c/coreboot/+/64861/comment/e8b63f42_a7c05c2a PS1, Line 14: mtk_wdt_preinit(); > what name do you think we should rename? Maybe `mtk_wdt_set_req()`? -- To view, visit https://review.coreboot.org/c/coreboot/+/64861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1904ff9387f7677a077068f2c3df923bd642ea3d Gerrit-Change-Number: 64861 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 13:30:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)chromium.org> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: Do SMM relocation via MSR
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64872 to look at the new patch set (#4). Change subject: soc/amd: Do SMM relocation via MSR ...................................................................... soc/amd: Do SMM relocation via MSR AMD CPUs have a convenient MSR that allows to set the SMBASE in the save state without ever entering SMM (e.g. at the default 0x30000 address). This has been a feature in all AMD CPUs since at least AMD K8. This allows to do relocation in parallel in ramstage and without setting up a relocation handler, which likely results in a speedup. The more cores the higher the speedup as relocation was happening sequentially. On a 4 core AMD picasso system this results in 33ms boot speedup. TESTED on google/vilboz (Picasso) with CONFIG_SMI_DEBUG: verify that SMM is correctly relocated with the BSP correctly entering the smihandler. Change-Id: I9729fb94ed5c18cfd57b8098c838c08a04490e4b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/smm/smm_helper.c M src/cpu/x86/Kconfig M src/cpu/x86/mp_init.c M src/soc/amd/common/Kconfig.common 4 files changed, 27 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/64872/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/64872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9729fb94ed5c18cfd57b8098c838c08a04490e4b Gerrit-Change-Number: 64872 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/corsola: Add new board 'steelix'
by Yu-Ping Wu (Code Review) 01 Jun '22

01 Jun '22

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64789 ) Change subject: mb/google/corsola: Add new board 'steelix' ...................................................................... mb/google/corsola: Add new board 'steelix' Add a new kingler follower 'steelix'. BUG=b:232195941 TEST=make # select steelix Change-Id: Idd2ed1404cde72ecdb6cc3a262e793a6272aa871 Signed-off-by: Zanxi Chen <chenzanxi(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64789 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: wen zhang <zhangwen6(a)huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/Kconfig.name 2 files changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved wen zhang: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 7b00563..194166c 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -50,6 +50,7 @@ string default "Kingler" if BOARD_GOOGLE_KINGLER default "Krabby" if BOARD_GOOGLE_KRABBY + default "Steelix" if BOARD_GOOGLE_STEELIX config BOOT_DEVICE_SPI_FLASH_BUS int diff --git a/src/mainboard/google/corsola/Kconfig.name b/src/mainboard/google/corsola/Kconfig.name index 85cb41e..b6703bd 100644 --- a/src/mainboard/google/corsola/Kconfig.name +++ b/src/mainboard/google/corsola/Kconfig.name @@ -4,6 +4,10 @@ bool "-> Kingler" select BOARD_GOOGLE_KINGLER_COMMON +config BOARD_GOOGLE_STEELIX + bool "-> Steelix" + select BOARD_GOOGLE_KINGLER_COMMON + comment "Krabby" config BOARD_GOOGLE_KRABBY 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/64789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd2ed1404cde72ecdb6cc3a262e793a6272aa871 Gerrit-Change-Number: 64789 Gerrit-PatchSet: 3 Gerrit-Owner: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Knox Chiou <knoxchiou(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wen zhang <zhangwen6(a)huaqin.corp-partner.google.com> Gerrit-CC: Yuqing Huang <huangyuqing(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: Enable thermal hardware reset for MT8192 and MT8195
by Rex-BC Chen (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Xi Chen, Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64861 ) Change subject: soc/mediatek: Enable thermal hardware reset for MT8192 and MT8195 ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/mt8192/bootblock.c: https://review.coreboot.org/c/coreboot/+/64861/comment/5a9bf86e_490d2b93 PS1, Line 14: mtk_wdt_preinit(); > We can rename mtk_wdt_preinit() to something else. what name do you think we should rename? -- To view, visit https://review.coreboot.org/c/coreboot/+/64861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1904ff9387f7677a077068f2c3df923bd642ea3d Gerrit-Change-Number: 64861 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 13:22:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)chromium.org> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2022