coreboot-gerrit June 2022

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Change in coreboot[master]: Documentation: Update index.md and add 4.18 release notes
by Felix Singer (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Martin L Roth, Julius Werner. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64843 ) Change subject: Documentation: Update index.md and add 4.18 release notes ...................................................................... Patch Set 1: (1 comment) File Documentation/releases/coreboot-4.18-relnotes.md: https://review.coreboot.org/c/coreboot/+/64843/comment/1011d3c9_5042e818 PS1, Line 17: > Would you mind adding the planned deprecation for the old libpayload API while you're here (https:// […] Do you mean the 4.17 release notes? CB:64846 -- To view, visit https://review.coreboot.org/c/coreboot/+/64843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52814ebbae804ea0ff24a7cec0618054029b8b47 Gerrit-Change-Number: 64843 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)tutanota.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)tutanota.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Jun 2022 00:57:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Improve performance by removing delays in cpucp init
by Julius Werner (Code Review) 01 Jun '22

01 Jun '22

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63085 ) Change subject: sc7280: Improve performance by removing delays in cpucp init ...................................................................... sc7280: Improve performance by removing delays in cpucp init As cpucp prepare takes 300 msec moving to before ramstage BUG=b:218406702 TEST=Validated on qualcomm sc7280 development board observed total timestamp as 1.73 sec from 1.97 sec Change-Id: I1a727514810a505cd1005ae7f52e5215e404b3bb Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad(a)quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63085 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/herobrine/romstage.c M src/soc/qualcomm/sc7280/Makefile.inc M src/soc/qualcomm/sc7280/cpucp_load_reset.c 3 files changed, 7 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c index 2ea78b8..97ce5a7 100644 --- a/src/mainboard/google/herobrine/romstage.c +++ b/src/mainboard/google/herobrine/romstage.c @@ -5,6 +5,7 @@ #include <soc/qclib_common.h> #include "board.h" #include <soc/shrm.h> +#include <soc/cpucp.h> static void prepare_usb(void) { @@ -18,6 +19,7 @@ void platform_romstage_main(void) { shrm_fw_load_reset(); + cpucp_prepare(); /* QCLib: DDR init & train */ qclib_load_and_run(); prepare_usb(); diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 85508e9..a20d49b 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -27,6 +27,7 @@ ################################################################################ romstage-y += cbmem.c romstage-y += shrm_load_reset.c +romstage-y += cpucp_load_reset.c romstage-y += ../common/qclib.c romstage-y += ../common/mmu.c romstage-y += mmu.c diff --git a/src/soc/qualcomm/sc7280/cpucp_load_reset.c b/src/soc/qualcomm/sc7280/cpucp_load_reset.c index cfb1687..6f8f51f 100644 --- a/src/soc/qualcomm/sc7280/cpucp_load_reset.c +++ b/src/soc/qualcomm/sc7280/cpucp_load_reset.c @@ -11,13 +11,11 @@ void cpucp_prepare(void) { - /* allow NS access to EPSS memory*/ + /* allow NS access to EPSS memory */ setbits32(&epss_top->access_override, 0x1); - /* Enable subsystem clock. Required for CPUCP PDMEM access*/ + /* Enable subsystem clock. Required for CPUCP PDMEM access */ setbits32(&epss_fast->epss_muc_clk_ctrl, 0x1); - if (!wait_ms(300, ((read32(&epss_fast->epss_muc_clk_ctrl) & 0x1) != 0x1))) - printk(BIOS_ERR, "%s: cannot get CPUCP PDMEM access.\n", __func__); } void cpucp_fw_load_reset(void) @@ -25,7 +23,8 @@ struct prog cpucp_fw_prog = PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); - cpucp_prepare(); + if (!wait_ms(300, (read32(&epss_fast->epss_muc_clk_ctrl) & 0x1) == 0x1)) + printk(BIOS_ERR, "%s: cannot get CPUCP PDMEM access.\n", __func__); if (!selfload(&cpucp_fw_prog)) die("SOC image: CPUCP load failed"); 24 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a727514810a505cd1005ae7f52e5215e404b3bb Gerrit-Change-Number: 63085 Gerrit-PatchSet: 26 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)tutanota.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sc7280: Improve performance by removing delays in cpucp init
by Julius Werner (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Ravi Kumar Bokka, Martin L Roth, Paul Menzel, Sudheer Amrabadi. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63085 ) Change subject: sc7280: Improve performance by removing delays in cpucp init ...................................................................... Patch Set 25: (1 comment) File src/mainboard/google/herobrine/romstage.c: https://review.coreboot.org/c/coreboot/+/63085/comment/ba66ff70_cf5cdb5c PS24, Line 22: prepare(); > Ack We don't have separate mainboard and chipset hooks for romstage on arm64, so this needs to be done here for now. We could introduce a mechanism for that if it becomes a frequent problem. Until this, our romstage hook needs have pretty much always been mainboard-specific so there hasn't really been a need yet. -- To view, visit https://review.coreboot.org/c/coreboot/+/63085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a727514810a505cd1005ae7f52e5215e404b3bb Gerrit-Change-Number: 63085 Gerrit-PatchSet: 25 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Martin L Roth <gaumless(a)tutanota.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Attention: Martin L Roth <gaumless(a)tutanota.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Wed, 01 Jun 2022 00:53:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)tutanota.com> Comment-In-Reply-To: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add CONFIG_LP_ELOG and its dependency
by Julius Werner (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Hsuan-ting Chen. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63115 ) Change subject: libpayload: Add CONFIG_LP_ELOG and its dependency ...................................................................... Patch Set 9: (1 comment) File payloads/libpayload/Makefile.inc: https://review.coreboot.org/c/coreboot/+/63115/comment/d04496f6_1e335116 PS9, Line 51: classes-$(CONFIG_LP_ELOG) += elog It seems overkill to create a Kconfig and a whole extra library for such a small file. Why not just put libc-srcs += $(coreboottop)/src/commonlib/bsd/elog.c in `libc/Makefile.inc` and call it a day? -- To view, visit https://review.coreboot.org/c/coreboot/+/63115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64d0fdd2a8eff1d89a1ac451d37b61787b5564e7 Gerrit-Change-Number: 63115 Gerrit-PatchSet: 9 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 00:48:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Makefile.inc: Add bootblock to CBFS before others
by Julius Werner (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64547 ) Change subject: Makefile.inc: Add bootblock to CBFS before others ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/64547/comment/b8ef740b_7832e818 PS2, Line 9: cbfstool > > Hrmm, should we maybe think if a different way of locating the metadata? […] The problem is that it still needs to be updated again every time a new CBFS file is added. We want images where even after the coreboot build system is done with them, you can still run `cbfstool add` to put more files in them (e.g. an out-of-tree payload) without breaking the verification chain. I think the only way that can work is if cbfstool knows how to find and update the bootblock in place, wherever it is on each platform. -- To view, visit https://review.coreboot.org/c/coreboot/+/64547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I385deb8231e44310ee139c3f69f449e75b92b2be Gerrit-Change-Number: 64547 Gerrit-PatchSet: 4 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)tutanota.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 00:40:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/nissa/var/nivviks: Enable ISH when UFS is present
by Kangheui Won (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Daniil Lunev, Reka Norman, Tim Wawrzynczak, Gwendal Grignou. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64845 ) Change subject: mb/google/nissa/var/nivviks: Enable ISH when UFS is present ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib60d44322cfbd8f82c33ecac7598881dfb1d0c3c Gerrit-Change-Number: 64845 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Daniil Lunev <dlunev(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Daniil Lunev <dlunev(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Jun 2022 00:39:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Fix a few spelling issues
by Julius Werner (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Martin L Roth. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64749 ) Change subject: Documentation: Fix a few spelling issues ...................................................................... Patch Set 2: (1 comment) File Documentation/getting_started/architecture.md: https://review.coreboot.org/c/coreboot/+/64749/comment/00a2ef5c_a4042272 PS2, Line 6: comparison_coreboot_uefi Uhh... this is great but now the link is broken. :/ You need to rename the files too. -- To view, visit https://review.coreboot.org/c/coreboot/+/64749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47add663f3021170b840203ce229acf836b7a1c4 Gerrit-Change-Number: 64749 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)tutanota.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin L Roth <gaumless(a)tutanota.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)tutanota.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 00:34:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cbfs: Add CBFS_TYPE_INTEL_FIT and exclude it from CBFS verification
by Julius Werner (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Tim Wawrzynczak. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64736 ) Change subject: cbfs: Add CBFS_TYPE_INTEL_FIT and exclude it from CBFS verification ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > This would also be needed for "bpm.bin" when using CBnT. Yeah... I don't really understand how that stuff works, I hope one of you can eventually fix it up if you ever want to combine it with CBFS verification. -- To view, visit https://review.coreboot.org/c/coreboot/+/64736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c1bb6dab0c9ccc6e78529758a42ad3194cd130c Gerrit-Change-Number: 64736 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Jun 2022 00:32:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib: Clean up compiler.h
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Patrick Georgi, Jakub Czapiga. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64737 ) Change subject: commonlib: Clean up compiler.h ...................................................................... Patch Set 2: (1 comment) File src/commonlib/bsd/include/commonlib/bsd/compiler.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150164): https://review.coreboot.org/c/coreboot/+/64737/comment/5ca3c01c_78b74f0a PS2, Line 35: #define __always_inline inline __attribute__((__always_inline__)) Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/64737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9644da594bb69133843c6b7f12ce50b2e45fd24b Gerrit-Change-Number: 64737 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 00:31:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cbfs: Add CBFS_TYPE_INTEL_FIT and exclude it from CBFS verification
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64736 ) Change subject: cbfs: Add CBFS_TYPE_INTEL_FIT and exclude it from CBFS verification ...................................................................... Patch Set 2: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c1bb6dab0c9ccc6e78529758a42ad3194cd130c Gerrit-Change-Number: 64736 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Jun 2022 00:31:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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