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Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
Patch Set 17:
(2 comments)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/63969/comment/b7f4bd8d_c82060f7
PS17, Line 1485: __weak uint8_t soc_lpi_get_constraints(void) { return 0; }
> We really try to avoid having __weak "do-nothing" functions in coreboot, but unless this is implemen […]
Another option is the weak implementation does the single device/dummy entry creation and that gets replaced with the more extensive one on the platform if it exists?
File src/soc/intel/alderlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/63969/comment/ac0054eb_cc2c15d6
PS12, Line 524: if (min_state == UNDEF)
: min_state = D0;
> Implemented in Patch set #13. I think the logic is clearer/more correct this way.
Done
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Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM
......................................................................
Patch Set 17:
(1 comment)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/63969/comment/dfd07990_defd8a50
PS17, Line 1485: __weak uint8_t soc_lpi_get_constraints(void) { return 0; }
We really try to avoid having __weak "do-nothing" functions in coreboot, but unless this is implemented first for all the SoCs that already use this (ADL, CML, CNL, EHL, JSL, SKL, TGL), the only other way around I could see would be to add a new Kconfig. anyone have any thoughts?
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Hello build bot (Jenkins), Subrata Banik, Ivy Jian, Angel Pons, Eric Lai,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/: Add PEG and initial Nvidia dGPU ASL support
......................................................................
mb/google/brya/: Add PEG and initial Nvidia dGPU ASL support
Some brya variants will use a GN20 series Nvidia GPU, which requires
quite a bit of ACPI support code to be written for it. This patch
lands a decent bit of the initial code for it on the brya platform,
including:
1) PEG RTD3 methods
2) DGPU power operations (RTD3 and GCOFF, NVJT _DSM and other Methods)
3) NVOP _DSM method
There will be more support to come later, this is all written to
specifications from the Nvidia Software Design Guide for GN20.
BUG=b:214581763
TEST=build patch train
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: Ifce1610210e9636e87dda4b55c8287334adfcc42
---
M src/mainboard/google/brya/Kconfig
A src/mainboard/google/brya/acpi/gpu_defines.h
A src/mainboard/google/brya/acpi/gpu_top.asl
A src/mainboard/google/brya/acpi/nvjt.asl
A src/mainboard/google/brya/acpi/nvop.asl
A src/mainboard/google/brya/acpi/peg.asl
A src/mainboard/google/brya/acpi/power.asl
A src/mainboard/google/brya/acpi/utility.asl
M src/mainboard/google/brya/dsdt.asl
9 files changed, 719 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/62931/6
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Hello build bot (Jenkins), Subrata Banik, Ivy Jian, Angel Pons, Nick Vaccaro, Eric Lai,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/agah: Add GPU power sequencing
......................................................................
mb/google/brya/var/agah: Add GPU power sequencing
This patch adds support for power sequencing of the Nvidia GN3050 for
agah, which uses PCH GPIOs to control the 5 power rails required for
the GPU. The GPU is power sequenced on during mainboard
initialization, then it is enumerated on the PCI bus and its resources
are assigned. This GPU will be used in a sort of "hybrid graphics"
mode, therefore during finalization, since its PCI BARs are saved into
ACPI memory and the GPU is not required upon initial boot, the GPU is
power sequenced off.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I1072be12ef58af5859e2a2d19c4a9c1adc0b0f88
---
M src/mainboard/google/brya/variants/agah/Makefile.inc
M src/mainboard/google/brya/variants/agah/gpio.c
M src/mainboard/google/brya/variants/agah/overridetree.cb
A src/mainboard/google/brya/variants/agah/variant.c
4 files changed, 192 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/62384/7
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Change subject: mb/google/brya/acpi: Add support for NBCI _DSM subfunction
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/64008/comment/4a8730ab_43c49228
PS1, Line 11: Nvidia
> Please specify which one. […]
I don't have a version number yet, this all comes from the Nvidia Software Design Guide.
https://review.coreboot.org/c/coreboot/+/64008/comment/8479793d_ffe8d195
PS1, Line 14: TEST=build
> Which proprietary Nvidia kernel driver and what Linux version are you testing with?
I do not have a device in hand yet to test with, hence compiling only is the test for the moment.
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Hello build bot (Jenkins), Subrata Banik, Eric Lai,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/google/brya/acpi: Add support for NBCI _DSM subfunction
......................................................................
mb/google/brya/acpi: Add support for NBCI _DSM subfunction
The Nvidia GPU supports another function named NBCI (NoteBook Common
Interface), which has some subfunctions which are required for the
Nvidia kernel driver to consume. The specification for this function
comes from the Nvidia GN20 Software Design Guide.
BUG=b:214581763
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I19eb9417923d297a084d6f5329682e91cd506a9e
---
M src/mainboard/google/brya/acpi/gpu_top.asl
A src/mainboard/google/brya/acpi/nbci.asl
2 files changed, 82 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/64008/2
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Change subject: mb/google/brya/acpi: Add support for NBCI _DSM subfunction
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/acpi/nbci.asl:
https://review.coreboot.org/c/coreboot/+/64008/comment/04c270f4_9600efed
PS1, Line 25: (0 << 10) | /* No 3D Hotkeys */
> Yes, just being explicit about the fields (bits that are not called out are reserved)
Thanks for the explanation Tim and Angel
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Evan Green has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64002 )
Change subject: soc/intel: Return ACPI_S4 as previous sleep state
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/64002/comment/20959f45_ea688d35
PS1, Line 8:
> Mention the problem, that suspend to disk currently does not(?) work?
Done
https://review.coreboot.org/c/coreboot/+/64002/comment/d29cea95_f76bc81b
PS1, Line 10: acpi_sleep_from_pm1()
> Nit: Fits on the line above.
Done
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Change subject: mb/google/brya/acpi: Add support for NBCI _DSM subfunction
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/acpi/nbci.asl:
https://review.coreboot.org/c/coreboot/+/64008/comment/04364453_ca095c6e
PS1, Line 25: (0 << 10) | /* No 3D Hotkeys */
> Yes
Yes, just being explicit about the fields (bits that are not called out are reserved)
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Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Eric Lai,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: soc/intel: Return ACPI_S4 as previous sleep state
......................................................................
soc/intel: Return ACPI_S4 as previous sleep state
pmc_prev_sleep_state() isn't handling the case where acpi_sleep_from_pm1()
returns ACPI_S4. Pass that value along so it can get set as a
prev_sleep_state. Without this, consumers see prev_sleep_state as 0
and always treat resume as a cold boot. With this, consumers can
correctly do behavior specific to S4 resume, like skipping the
disconnect IPC command to the PMC on Alderlake systems.
BUG=b:230031158
TEST=Resume from S4 on Primus4es
Signed-off-by: Evan Green <evgreen(a)chromium.org>
Change-Id: I3fb3dc428a749db80293e51a04a2096514a7b689
---
M src/soc/intel/common/block/pmc/pmclib.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/64002/3
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