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Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63882 )
Change subject: arch/x86/smbios.c: Add SMBIOS type 17 for empty DIMM slots
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
> You could invert `bool present` to `bool empty` or similar, so that the default value doesn't change […]
I plan to use an enum for dimm->present's value, because when a DIMM is not present but also doesn't exist on the board, setting it to false can still lead to creating an empty dimm slot table. So something like
enum dimm_present {
EMPTY_DIMM_SLOT = 1,
INSTALLED_DIMM_SLOT = 2,
/* For DIMM that are not present and doesn't exist on the board. */
IGNORED_DIMM = 0xff
};
smbios.c:
if (dimm->present == EMPTY_DIMM_SLOT) {
create empty DIMM table
} else if (dimm->present != IGNORED_DIMM) {
create normal/installed DIMM table
}
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Change subject: soc/intel/alderlake: Add missing ACPI device path names
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/alderlake/chip.c:
https://review.coreboot.org/c/coreboot/+/63984/comment/52ae01e0_88588c56
PS5, Line 78: case SA_DEVFN_DPTF: return "DPTF";
> Hi Eric. We can definitely update the naming of the defines/strings if this isn't current anymore. […]
oh, yes. sure. of course not in this one.
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Change subject: soc/intel/alderlake: Add missing ACPI device path names
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/alderlake/chip.c:
https://review.coreboot.org/c/coreboot/+/63984/comment/432bcf12_d1cc001c
PS5, Line 78: case SA_DEVFN_DPTF: return "DPTF";
> Interesting, should we change to DTT now? In EDS, Dynamica Tuning Technology (D4:F0) but pci_devs. […]
Hi Eric. We can definitely update the naming of the defines/strings if this isn't current anymore. Is it worth perhaps doing a sanity of them all? Perhaps best in a separate submission?
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Change subject: drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/64024/comment/b9496d51_12bb55fe
PS1, Line 14: One can change parameters in device tree so that the used setup can be
> Plesae add a blank line above.
Done
https://review.coreboot.org/c/coreboot/+/64024/comment/fbfe94e7_85973a0b
PS1, Line 19: https://www.marvell.com/content/dam/marvell/en/public-collateral/
: transceivers/marvell-phys-transceivers-alaska-88e151x-datasheet.pdf
> Can be in one line.
Done
File src/drivers/phy/m88e1512/chip.h:
https://review.coreboot.org/c/coreboot/+/64024/comment/df4c5276_f2174f43
PS1, Line 4: uint8_t device_index;
> Use native types?
Done
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Change subject: soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity
......................................................................
Patch Set 4:
(3 comments)
File src/soc/intel/elkhartlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/63888/comment/9813120d_e697b21d
PS2, Line 246: config EHL_TSN_PHY2MAC_IRQ_ACTIVE_HIGH
> Instead of Kconfig could that be made a devicetree option?
I will have a look at this...
File src/soc/intel/elkhartlake/tsn_gbe.c:
https://review.coreboot.org/c/coreboot/+/63888/comment/4493e111_f7f844a7
PS2, Line 38: udelay(TSN_GMII_DELAY_US);
> Do you need this udelay() here at all? Are there restrictions in how often you can read the busy bit […]
I tested it and it seems to work the same way.
https://review.coreboot.org/c/coreboot/+/63888/comment/b350eda8_b23e6a5d
PS2, Line 44: Timeout at %ld
> Maybe: […]
Done
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Hello build bot (Jenkins), Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63888
to look at the new patch set (#4).
Change subject: soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity
......................................................................
soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity
EHL MAC side expects a rising edge signal for an IRQ. Based on the
mainboard wiring it could be necessary to change the interrupt polarity.
This patch provides the functionality to invert a falling edge signal
that comes from an external PHY.
Change-Id: Ia314014c7cacbeb72629c773c8c0bb5f002a3f54
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/elkhartlake/include/soc/tsn_gbe.h
M src/soc/intel/elkhartlake/tsn_gbe.c
3 files changed, 108 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/63888/4
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Change subject: soc/intel/elkhartlake: Provide ability to update TSN GbE MAC addresses
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63863/comment/8e5c4394_fd90950d
PS3, Line 13: following patch
> next patch in the series
Done
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Uwe Poeche has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63548 )
Change subject: mb/siemens/mc_ehl: Disable RAPL
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63548/comment/55ceeeab_eea8016c
PS7, Line 9: Disable RAPL for all mainboards based on mc_ehl.
> Please add such things to the commit message.
Done
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Change subject: mb/siemens/mc_ehl2: Adjust PSE TSN settings in devicetree
......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63862/comment/c2da1169_27f85983
PS3, Line 8:
> What is the current problem? nNot all controllers showing up?
Yes, that's right. FSP-S UPD parameter must be set correctly for GbE PSE0/1 to work.
https://review.coreboot.org/c/coreboot/+/63862/comment/02bec6a8_852622b0
PS3, Line 12: This patch enables the Serial Gigabit Media Independent Interface
> Please add a blank line above to separate paragraphs.
Done
https://review.coreboot.org/c/coreboot/+/63862/comment/fc63a550_fc3140d5
PS3, Line 19: ifconfig
> New tools are `ip`. ;-) For example: `ip l` and `ip a`.
Cool. Thanks for the hint.
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Change subject: soc/intel/elkhartlake: Implement TSN GbE driver
......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63861/comment/264c6ff8_eb0ebdf1
PS3, Line 7: TSN
> Sorry, what is TSN?
Hi Paul, TSN is the abbreviation for Time Sensitive Networking.
File src/soc/intel/elkhartlake/tsn_gbe.c:
https://review.coreboot.org/c/coreboot/+/63861/comment/cff244e9_97fd40d1
PS3, Line 19: 0x4b32
> Add first to sort?
Done
https://review.coreboot.org/c/coreboot/+/63861/comment/0f174955_ee64a721
PS3, Line 24: .devices = gbe_tsn_device_ids,
> Either align or do not align the =.
Done
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