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Change subject: mb/siemens/mc_ehl: Disable RAPL
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63548/comment/2eb01d4f_2f1ab090
PS7, Line 9: Disable RAPL for all mainboards based on mc_ehl.
> For stable real time mode of the CPUs.
Please add such things to the commit message.
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Change subject: mb/google/brya/var/crota: Enable webcam power
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63955/comment/74bc0bc2_5d3ea476
PS3, Line 9: - set GPP_D16 to enable webcam power
> No bullet point needed. Maybe also mention schematics.
Done
https://review.coreboot.org/c/coreboot/+/63955/comment/4576b7b2_95059259
PS3, Line 13: TEST=build and boot into kernel v5.10
> … and notice log: …
Done
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Hello build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63955
to look at the new patch set (#4).
Change subject: mb/google/brya/var/crota: Enable webcam power
......................................................................
mb/google/brya/var/crota: Enable webcam power
Based on the schematic bernadino 14 adl-p 20220318.pdf to set
GPP_D16 to enable webcam power
BUG=b:230289857
BRANCH=none
TEST=build and notice log kernel v5.10
Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com>
Change-Id: I01c73006d24b00be348655334232bea5eeb312e4
---
M src/mainboard/google/brya/variants/crota/gpio.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/63955/4
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Change subject: soc/intel/alderlake: Call into PMC IPC to inform PCI enumeration done
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File src/soc/intel/alderlake/lockdown.c:
https://review.coreboot.org/c/coreboot/+/63954/comment/022c8ccc_6707f802
PS1, Line 41: /* Send PMC IPC to inform about PCI enumeration done */
: pmc_send_pci_enum_done();
> > should this go in the above if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) block? […]
I'd expand the comment, stating that FSP doesn't do this.
Are there any plans to fix FSP? I guess we don't care as we won't be using FSP notify on ADL anyway.
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Change subject: soc/intel/cmn/blk/pmc: API to inform PMC about PCI enumeration done
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63953/comment/09f1f27c_e5288ed2
PS3, Line 10:
> Who is going to use this API?
See CB:63954 (the other patch in the train)
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Change subject: mb/google/dedede/var/beadrix: Add a Proximity Sensor SX9324 for SAR
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/dedede/variants/beadrix/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/63652/comment/8d248e97_23f2eaee
PS4, Line 188: register "reg_gnrl_ctrl0" = "0x0a"
> Where are these values from?
Hi Paul,
Thank you for your advice.
These values are refer to the other Project https://review.coreboot.org/plugins/gitiles/coreboot/+/14a1c2778fda7e4ed25d…
Reference: https://partnerissuetracker.corp.google.com/issues/213549229#comment6
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Change subject: nb/amd/common: Move RAM calcualtion to common code
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Patch Set 6:
(1 comment)
File src/northbridge/amd/agesa/family14/northbridge.c:
https://review.coreboot.org/c/coreboot/+/61682/comment/5bf64273_a3469cb3
PS6, Line 27: static unsigned int fx_devs = 0;
> There is no perfect order. […]
I tried to clean up fx_devs stuff on f14, CB:64009 and CB:64010 (I'm not sure about the latter change, I'd like to have proper PCI drivers to avoid having to look up other PCI devices).
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Change subject: nb/amd/common: Move RAM calcualtion to common code
......................................................................
Patch Set 6:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61682/comment/32b6fa84_b273c47b
PS6, Line 7: nb/amd/common: Move RAM calcualtion to common code
calculation
File src/northbridge/amd/agesa/family14/northbridge.c:
https://review.coreboot.org/c/coreboot/+/61682/comment/908ec2f2_6726f3f9
PS6, Line 27: static unsigned int fx_devs = 0;
> I'd simplify the fx_devs stuff first.
There is no perfect order. Addressing fx_devs arrays soon extends to no longer passing nodeid and at the end of the day, majority of the code review ends up with code removals like in CB:52934.
https://review.coreboot.org/c/coreboot/+/61682/comment/80a06a93_aa220430
PS6, Line 27: static unsigned int fx_devs = 0;
> I'd simplify the fx_devs stuff first.
Ack
https://review.coreboot.org/c/coreboot/+/61682/comment/8fd08925_ace9250e
PS6, Line 100: dev = __f1_dev[i];
> dev = pcidev_on_root(DEV_CDB, 1) ?
Ack
File src/northbridge/amd/common/ram_calc.c:
https://review.coreboot.org/c/coreboot/+/61682/comment/2855a570_41d3878d
PS5, Line 28: >
> No, this is correct, and comment in line #25 is wrong. […]
Ack
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Change subject: drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/elkhartlake/tsn_gbe.c:
https://review.coreboot.org/c/coreboot/+/64024/comment/17e62108_f80c6a2a
PS1, Line 124: .ops_pci = &pci_dev_ops_pci,
> Should this be a separate patch, or at least mentioned in the commit message?
Is mentioned in the commit message:
"To be able to use the driver, it is necessary to activate
the scan bus operation in the corresponding SOC TSN GbE driver."
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