coreboot-gerrit May 2022

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Change in coreboot[master]: Allow trailing whitespaces in .md files
by Maximilian Brune (Code Review) 03 May '22

03 May '22

Attention is currently required from: Martin L Roth, Paul Menzel. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64032 ) Change subject: Allow trailing whitespaces in .md files ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/64032/comment/59635aff_7abb068a PS1, Line 10: a new line > Only two trailing spaces denote a new line, don’t they? Yes they do. Do you mean one should check for exactly two trailing whitesspaces? https://review.coreboot.org/c/coreboot/+/64032/comment/5bee6add_688d7d0b PS1, Line 9: since trailing whitesspaces have an actual meaning : in mardown files (a new line), I would allow it > Please start sentences with capital letter, and add with punctuation mark like dot/period. Ack https://review.coreboot.org/c/coreboot/+/64032/comment/32900a9d_38381e6e PS1, Line 10: mardown > Markdown Done -- To view, visit https://review.coreboot.org/c/coreboot/+/64032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdb92ee857ee4ad32b6afb84ace427b27b41bb7c Gerrit-Change-Number: 64032 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 03 May 2022 12:31:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Allow trailing whitespaces in .md files
by Maximilian Brune (Code Review) 03 May '22

03 May '22

Attention is currently required from: Martin L Roth, Maximilian Brune. Hello build bot (Jenkins), Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64032 to look at the new patch set (#2). Change subject: Allow trailing whitespaces in .md files ...................................................................... Allow trailing whitespaces in .md files Two trailing whitesspaces have an actual meaning in Markdown files (a new line). Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Ibdb92ee857ee4ad32b6afb84ace427b27b41bb7c --- M util/lint/lint-stable-003-whitespace 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/64032/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdb92ee857ee4ad32b6afb84ace427b27b41bb7c Gerrit-Change-Number: 64032 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/haswell: Add RMRR for USB devices
by Angel Pons (Code Review) 03 May '22

03 May '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43807 ) Change subject: nb/intel/haswell: Add RMRR for USB devices ...................................................................... nb/intel/haswell: Add RMRR for USB devices FIXME: Figure out which address the RMRR corresponds to. VT-d checklist verifies that there's a RMRR entry for USB devices. If said devices are enabled, add the RMRR entry. Tested on Asrock B85M Pro4, verify VT-d check about USB RMRR passes. Change-Id: I800d6d1847f457827d64b39c5b7bbfc9cb04f230 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi.c M src/southbridge/intel/lynxpoint/acpi.c M src/southbridge/intel/lynxpoint/pch.h 3 files changed, 36 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/43807/1 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 6a6a124..5e28c82 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -87,7 +87,7 @@ acpi_dmar_drhd_fixup(tmp, current); } - return current; + return acpi_create_usb_rmrr(current); } unsigned long northbridge_write_acpi_tables(const struct device *const dev, diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index 8fee16b..6a2103b 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -77,3 +77,36 @@ ssdt->length = current - (unsigned long)ssdt; ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); } + +unsigned long acpi_create_usb_rmrr(const unsigned long tmp) +{ + unsigned long current = tmp; + + struct device *const ehc1_dev = pcidev_on_root(0x1d, 0); + struct device *const ehc2_dev = pcidev_on_root(0x1a, 0); + struct device *const xhci_dev = pcidev_on_root(0x14, 0); + + const bool ehc1_enabled = ehc1_dev && ehc1_dev->enabled; + const bool ehc2_enabled = ehc2_dev && ehc2_dev->enabled; + const bool xhci_enabled = xhci_dev && xhci_dev->enabled; + + /* If no USB devices are enabled, do not generate the RMRR entry */ + if (!ehc1_enabled && !ehc2_enabled && !xhci_enabled) + return current; + + /* FIXME: This should be the address of the runtime register space instead! */ + current += acpi_create_dmar_rmrr(current, 0, 0x3e2e0000, 0x3e300000 - 1); + + if (ehc1_enabled) + current += acpi_create_dmar_ds_pci(current, 0, 0x1d, 0); + + if (ehc2_enabled) + current += acpi_create_dmar_ds_pci(current, 0, 0x1a, 0); + + if (xhci_enabled) + current += acpi_create_dmar_ds_pci(current, 0, 0x14, 0); + + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 9946944..79d9dbc 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -122,6 +122,8 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); +unsigned long acpi_create_usb_rmrr(const unsigned long tmp); + void enable_usb_bar(void); int early_pch_init(void); void pch_enable_lpc(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/43807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I800d6d1847f457827d64b39c5b7bbfc9cb04f230 Gerrit-Change-Number: 43807 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/psp/psp_gen2: move CORE_2_PSP_MSG_38 defines
by Fred Reitberger (Code Review) 03 May '22

03 May '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64011 ) Change subject: soc/amd/common/block/psp/psp_gen2: move CORE_2_PSP_MSG_38 defines ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67cc2ff63d1c0322b514521975f3ce0f9b1cf5b1 Gerrit-Change-Number: 64011 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 03 May 2022 12:01:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Allow trailing whitespaces in .md files
by Paul Menzel (Code Review) 03 May '22

03 May '22

Attention is currently required from: Martin L Roth, Maximilian Brune. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64032 ) Change subject: Allow trailing whitespaces in .md files ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/64032/comment/b7a2cd14_1bbc2eba PS1, Line 10: mardown Markdown https://review.coreboot.org/c/coreboot/+/64032/comment/bb994cd9_a30e8866 PS1, Line 10: a new line Only two trailing spaces denote a new line, don’t they? https://review.coreboot.org/c/coreboot/+/64032/comment/731ec45c_5f543584 PS1, Line 9: since trailing whitesspaces have an actual meaning : in mardown files (a new line), I would allow it Please start sentences with capital letter, and add with punctuation mark like dot/period. -- To view, visit https://review.coreboot.org/c/coreboot/+/64032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdb92ee857ee4ad32b6afb84ace427b27b41bb7c Gerrit-Change-Number: 64032 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Tue, 03 May 2022 11:46:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Allow trailing whitespaces in .md files
by Maximilian Brune (Code Review) 03 May '22

03 May '22

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64032 ) Change subject: Allow trailing whitespaces in .md files ...................................................................... Allow trailing whitespaces in .md files since trailing whitesspaces have an actual meaning in mardown files (a new line), I would allow it Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Ibdb92ee857ee4ad32b6afb84ace427b27b41bb7c --- M util/lint/lint-stable-003-whitespace 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/64032/1 diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index 6f9d788..9a6db00 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -5,7 +5,7 @@ # DESCR: Check for superfluous whitespace in the tree LC_ALL=C export LC_ALL -EXCLUDELIST='^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|COPYING|LICENSE|README|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$|\.gif$|\.ttf$|\.woff$|\.png$|\.eot$|\.vbt$|\.ico$' +EXCLUDELIST='^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|COPYING|LICENSE|README|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$|\.gif$|\.ttf$|\.woff$|\.png$|\.eot$|\.vbt$|\.ico$|\.md$' INCLUDELIST="src util payloads Makefile* toolchain.inc tests" # shellcheck disable=SC2086,SC2046 -- To view, visit https://review.coreboot.org/c/coreboot/+/64032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdb92ee857ee4ad32b6afb84ace427b27b41bb7c Gerrit-Change-Number: 64032 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/craask: Disable LTE-related GPIOs based on fw_config
by Tyler Wang (Code Review) 03 May '22

03 May '22

Attention is currently required from: Kangheui Won, Paul Menzel, Tim Wawrzynczak, Reka Norman, Nick Vaccaro. Hello build bot (Jenkins), Kangheui Won, Reka Norman, Tim Wawrzynczak, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63893 to look at the new patch set (#8). Change subject: mb/google/brya/var/craask: Disable LTE-related GPIOs based on fw_config ...................................................................... mb/google/brya/var/craask: Disable LTE-related GPIOs based on fw_config If the LTE USB DB is not connected, disable the LTE-related GPIOs. BUG=b:229938024, b:229048361 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Change-Id: I37719cee48370a04534067aa64a3aa77e453948a --- M src/mainboard/google/brya/variants/craask/Makefile.inc M src/mainboard/google/brya/variants/craask/gpio.c 2 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63893/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/63893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37719cee48370a04534067aa64a3aa77e453948a Gerrit-Change-Number: 63893 Gerrit-PatchSet: 8 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/craask: Disable LTE-related GPIOs based on fw_config
by Tyler Wang (Code Review) 03 May '22

03 May '22

Attention is currently required from: Kangheui Won, Paul Menzel, Tim Wawrzynczak, Reka Norman, Nick Vaccaro. Tyler Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63893 ) Change subject: mb/google/brya/var/craask: Disable LTE-related GPIOs based on fw_config ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/brya/variants/craask/fw_config.c: https://review.coreboot.org/c/coreboot/+/63893/comment/02ac1f3e_40269622 PS7, Line 23: if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { : printk(BIOS_DEBUG, "Disable LTE-related GPIO pins.\n"); : gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); : } : > This approach leavess a gpio interrupt line (GPP_H19) floating for a short time. […] Hi Nick, I have 2 questions would like to discuss with you: 1. This approach leavess a gpio interrupt line (GPP_H19) floating for a short time. >> We had set WWAN_RST_L to low and WWAN_EN to high in bootblock stage, but we didn't set interrupt pin. Is it the root cause of GPP_H19 be floating in a short time? 2. Override GPIO setting in gpio.c >> Reference to Nivviks, seems like we don't need to override GPIO in ramstage for enable LTE module. I will move disable LTE gpio settings to gpio.c as well. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/63893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37719cee48370a04534067aa64a3aa77e453948a Gerrit-Change-Number: 63893 Gerrit-PatchSet: 7 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 03 May 2022 11:02:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/crota: setting for codec reset pin
by Terry Chen (Code Review) 03 May '22

03 May '22

Terry Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64027 ) Change subject: mb/google/brya/var/crota: setting for codec reset pin ...................................................................... mb/google/brya/var/crota: setting for codec reset pin The audio codec of Crota360 used is Cirrus CS42L42, different from Brya (Realtek ALC5682I) There is no Reset pin on ALC5682 but CS42L42 is needed. So we use GPP_B15 for the reset pin of CS42L42 controlled that make the power sequence well. BUG=b:230074351 BRANCH=none TEST=build coreboot without error Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Change-Id: Ie942b3c553823510dfa6f6fb70a7b13881fc4c14 --- M src/mainboard/google/brya/variants/crota/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/64027/1 diff --git a/src/mainboard/google/brya/variants/crota/gpio.c b/src/mainboard/google/brya/variants/crota/gpio.c index ee8ee19..881f78d 100644 --- a/src/mainboard/google/brya/variants/crota/gpio.c +++ b/src/mainboard/google/brya/variants/crota/gpio.c @@ -22,8 +22,8 @@ PAD_NC(GPP_B2, NONE), /* B3 : PROC_GP2 ==> NC */ PAD_NC(GPP_B3, NONE), - /* B15 : TIME_SYNC0 ==> NC */ - PAD_NC(GPP_B15, NONE), + /* B15 : PROC_GP3 ==> AUD_RST_L */ + PAD_CFG_GPO(GPP_B15, 1, PWROK), /* C3 : GPP_C3 ==> SML0_SMBCLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/64027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie942b3c553823510dfa6f6fb70a7b13881fc4c14 Gerrit-Change-Number: 64027 Gerrit-PatchSet: 1 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/variants/crota: Enable Bluetooth offload support
by Terry Chen (Code Review) 03 May '22

03 May '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak. Terry Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64019 ) Change subject: mb/google/brya/variants/crota: Enable Bluetooth offload support ...................................................................... Patch Set 5: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/64019/comment/373ebecd_3853aaee PS3, Line 12: TEST=emerge-byra coreboot > Are you going to test it? Done File src/mainboard/google/brya/variants/crota/gpio.c: https://review.coreboot.org/c/coreboot/+/64019/comment/5bec7c82_9a4ad4d8 PS3, Line 102: PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */ : PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */ : PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */ : PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */ : PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */ : PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */ : PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */ : PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */ > Mention the source in the commit message. Done File src/mainboard/google/brya/variants/crota/variant.c: https://review.coreboot.org/c/coreboot/+/64019/comment/14027024_73b4c804 PS3, Line 9: config->cnvi_bt_audio_offload = 1; > Please fix the indentation. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/64019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ac54156cc4a8d824ed1c549d66fc369698a352c Gerrit-Change-Number: 64019 Gerrit-PatchSet: 5 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 03 May 2022 10:15:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit May 2022