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Change subject: soc/amd/common/block/psp/psp_gen2: use SMN access to PSP
......................................................................
Patch Set 1: Code-Review+2
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63178 )
Change subject: mb/google/brya: Consistently put void before __weak attribute
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63178/comment/77ca355a_a60e6626
PS2, Line 7: mb/google/brya: Make __weak usage consistent
> At least I had to look at the diff to understand, what is meant by this. […]
Done
Patchset:
PS2:
> I think Tim is just making sure the usage is consistent within the same file. […]
Right, the commit is prefixed with mb/google/brya, so I grepped for __weak in that directory and made what I found consistent.
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Hello build bot (Jenkins), Paul Menzel, Angel Pons, Eric Lai, Elyes Haouas,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63178
to look at the new patch set (#3).
Change subject: mb/google/brya: Consistently put void before __weak attribute
......................................................................
mb/google/brya: Consistently put void before __weak attribute
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: Ic59cccdf0fb88fc71a440170ee40b73dd8736a33
---
M src/mainboard/google/brya/mainboard.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/63178/3
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Change subject: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware
......................................................................
Patch Set 7:
(1 comment)
File src/soc/amd/common/block/lpc/spi_dma.c:
https://review.coreboot.org/c/coreboot/+/56322/comment/fcc80c86_d50a4ee8
PS7, Line 127: memset(transaction->destination, 0xFC, transaction->transfer_size);
> 0xFC magic number?
Just a poison value so the `memcmp` fill fail.
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Change subject: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware
......................................................................
Patch Set 7:
(1 comment)
File src/soc/amd/common/block/lpc/spi_dma.c:
https://review.coreboot.org/c/coreboot/+/56322/comment/a37ed068_f6b088fc
PS7, Line 127: memset(transaction->destination, 0xFC, transaction->transfer_size);
0xFC magic number?
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64024 )
Change subject: drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512
......................................................................
Patch Set 3:
(2 comments)
File src/drivers/phy/m88e1512/chip.h:
https://review.coreboot.org/c/coreboot/+/64024/comment/2a515a5d_41fed1d1
PS3, Line 4: unsigned char device_index;
What does this describe? Something functional? is it related to
coreboot devices? or just cosmetic, i.e. what is printed to the
log?
File src/soc/intel/elkhartlake/tsn_gbe.c:
https://review.coreboot.org/c/coreboot/+/64024/comment/d16998a8_33803be1
PS1, Line 124: .ops_pci = &pci_dev_ops_pci,
> Is mentioned in the commit message: […]
That EHL is a(/the?) corresponding SoC is only visible to people
who know what board you are working on. It's not covered by the
scope given in the commit summary.
And `pci_dev_ops_pci` seems to be about subsystem IDs. It's not
wrong to have it here, but looks like an unrelated bugfix.
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Change subject: soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/elkhartlake/tsn_gbe.c:
https://review.coreboot.org/c/coreboot/+/63888/comment/e076d025_123b7755
PS2, Line 38: udelay(TSN_GMII_DELAY_US);
> I tested it and it seems to work the same way.
Done
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Change subject: mb/siemens/mc_ehl2: Adjust PSE TSN settings in devicetree
......................................................................
Patch Set 4:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63862/comment/f315ff62_c24cf47a
PS2, Line 10: including
> I have expanded the sentence a little...
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/63862/comment/f5b05b0e_0c25a360
PS3, Line 9: Two
: of them reside in PCH including Intel Programmable Services Engine (PSE)
: and are controlled by these.
> Maybe: […]
Done
https://review.coreboot.org/c/coreboot/+/63862/comment/0cdd5a24_1c538a57
PS3, Line 15: And furthermore, the PCH TSN Link speed is set to 1
: Gbps.
> Please do that in a separate commit.
Done
https://review.coreboot.org/c/coreboot/+/63862/comment/b70505cd_df9390fc
PS3, Line 19: ifconfig
> Cool. Thanks for the hint.
Ack
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