coreboot-gerrit May 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI
by Werner Zeh (Code Review) 06 May '22

06 May '22

Attention is currently required from: Nico Huber, Subrata Banik, Paul Menzel, Arthur Heymans. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63982 ) Change subject: soc/intel/cmn/spi: Add ACPI SSDT extension for fast SPI ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/spi/spi.c: https://review.coreboot.org/c/coreboot/+/63982/comment/b3f40eb1_9099bbdb PS1, Line 192: .acpi_hid = spi_acpi_hid, : .acpi_name = spi_acpi_name, > Yes, that's true. Will refactor in the next version. Actually, it turned out that at least acpi_name is usefull being defined here this way. It is used deeper down in acpi_device_write_uid(). -- To view, visit https://review.coreboot.org/c/coreboot/+/63982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa89cdf41f42d4df5b46f095e22924157d9f3c3f Gerrit-Change-Number: 63982 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 06 May 2022 08:26:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Demote log level of SPMI clock calibration problem to info
by Yu-Ping Wu (Code Review) 06 May '22

06 May '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64090 ) Change subject: soc/mediatek: Demote log level of SPMI clock calibration problem to info ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I148b4aeaaeb10e1c269a8eccbb19e8d8e17e40ff Gerrit-Change-Number: 64090 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 06 May 2022 08:22:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Demote log level of SPMI clock calibration problem to info
by Rex-BC Chen (Code Review) 06 May '22

06 May '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64090 ) Change subject: soc/mediatek: Demote log level of SPMI clock calibration problem to info ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/64090/comment/db66f0ed_f52bb3a9 PS1, Line 7: soc/mediatek: Adjust log level of calibration for spmi clock > Be more specific: […] Done https://review.coreboot.org/c/coreboot/+/64090/comment/33ae917c_08ccad59 PS1, Line 9: expeted > expected Done https://review.coreboot.org/c/coreboot/+/64090/comment/f45ccb1d_202fdde5 PS1, Line 11: all data, the system will enter "die". Therefore, we adjust the log level > Please wrap lines after 72 characters per line. Done File src/soc/mediatek/common/pmif_spmi.c: https://review.coreboot.org/c/coreboot/+/64090/comment/81f84fad_b2a23d0b PS1, Line 47: printk(BIOS_WARNING, "%s next, slvid:%d rdata = 0x%x.\n", > ok, I will do this. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/64090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I148b4aeaaeb10e1c269a8eccbb19e8d8e17e40ff Gerrit-Change-Number: 64090 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 06 May 2022 08:18:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Demote log level of SPMI clock calibration problem to info
by Rex-BC Chen (Code Review) 06 May '22

06 May '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64090 to look at the new patch set (#3). Change subject: soc/mediatek: Demote log level of SPMI clock calibration problem to info ...................................................................... soc/mediatek: Demote log level of SPMI clock calibration problem to info It's expected that the mismatch logs will be shown when doing calibration for spmi clock. If it is failed to do calibration for spmi clock for all data, the system will enter "die". Therefore, we adjust the log level from BIOS_ERR to BIOS_INFO. BUG=b:231531254 TEST=emerge-cherry coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I148b4aeaaeb10e1c269a8eccbb19e8d8e17e40ff --- M src/soc/mediatek/common/pmif_spmi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/64090/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/64090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I148b4aeaaeb10e1c269a8eccbb19e8d8e17e40ff Gerrit-Change-Number: 64090 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Demote log level of SPMI clock calibration problem to w...
by Rex-BC Chen (Code Review) 06 May '22

06 May '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64090 ) Change subject: soc/mediatek: Demote log level of SPMI clock calibration problem to warning ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/common/pmif_spmi.c: https://review.coreboot.org/c/coreboot/+/64090/comment/f82f2a30_daa9840d PS1, Line 47: printk(BIOS_WARNING, "%s next, slvid:%d rdata = 0x%x.\n", > These look like debug messages. […] ok, I will do this. -- To view, visit https://review.coreboot.org/c/coreboot/+/64090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I148b4aeaaeb10e1c269a8eccbb19e8d8e17e40ff Gerrit-Change-Number: 64090 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 06 May 2022 08:15:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge
by Werner Zeh (Code Review) 06 May '22

06 May '22

Attention is currently required from: Mario Scheithauer. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63931 ) Change subject: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171 Gerrit-Change-Number: 63931 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Fri, 06 May 2022 08:13:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge
by Mario Scheithauer (Code Review) 06 May '22

06 May '22

Attention is currently required from: Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63931 ) Change subject: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63931/comment/6a64ea8a_9af6cd82 PS4, Line 10: PCI > PCIe Done https://review.coreboot.org/c/coreboot/+/63931/comment/921ba8f7_08b5e9a0 PS4, Line 10: ports are in use > clock outputs of this bridge are used. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171 Gerrit-Change-Number: 63931 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 06 May 2022 08:12:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Demote log level of SPMI clock calibration problem to w...
by Yu-Ping Wu (Code Review) 06 May '22

06 May '22

Attention is currently required from: Hung-Te Lin, Paul Menzel. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64090 ) Change subject: soc/mediatek: Demote log level of SPMI clock calibration problem to warning ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/common/pmif_spmi.c: https://review.coreboot.org/c/coreboot/+/64090/comment/c4cda763_178fff2f PS1, Line 47: printk(BIOS_WARNING, "%s next, slvid:%d rdata = 0x%x.\n", > These look like debug messages. […] If this is expected, I'd change this to BIOS_INFO. -- To view, visit https://review.coreboot.org/c/coreboot/+/64090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I148b4aeaaeb10e1c269a8eccbb19e8d8e17e40ff Gerrit-Change-Number: 64090 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 06 May 2022 08:12:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge
by Mario Scheithauer (Code Review) 06 May '22

06 May '22

Attention is currently required from: Mario Scheithauer. Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63931 to look at the new patch set (#5). Change subject: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge ...................................................................... mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge On this mainboard there are legacy PCI devices connected behind a PCIe-2-PCI bridge. Not all clock outputs of this bridge are used. This patch disables the unused PCI clock outputs on the XIO2001 bridge. Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/63931/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171 Gerrit-Change-Number: 63931 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Demote log level of SPMI clock calibration problem to w...
by Rex-BC Chen (Code Review) 06 May '22

06 May '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64090 ) Change subject: soc/mediatek: Demote log level of SPMI clock calibration problem to warning ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I148b4aeaaeb10e1c269a8eccbb19e8d8e17e40ff Gerrit-Change-Number: 64090 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 06 May 2022 08:11:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2022