coreboot-gerrit May 2022

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Change in coreboot[master]: nb/intel/gm45: Allow for PCI BARs above 4G
by Arthur Heymans (Code Review) 06 May '22

06 May '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64094 ) Change subject: nb/intel/gm45: Allow for PCI BARs above 4G ...................................................................... nb/intel/gm45: Allow for PCI BARs above 4G Linux needs to know that allocating BARs above 4G is fine so reserve a region in ACPI for that. Tested on thinkpad X200: a PCIe window gets allocated above 4G and Linux does not relocate it. Change-Id: I62a8a656481eba01add3d7d06b42e3352206df1b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/acpi/hostbridge.asl M src/northbridge/intel/gm45/northbridge.c 2 files changed, 50 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/64094/1 diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl index 2a8a137..58113dd 100644 --- a/src/northbridge/intel/gm45/acpi/hostbridge.asl +++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl @@ -188,6 +188,12 @@ 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, IO_APIC_ADDR,,, PM01) + // PCI Memory Region above 4G TOUUD -> 1 << cpu_addr_bits + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM02) + /* TPM Area (0xfed40000-0xfed44fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, @@ -195,6 +201,9 @@ 0x00005000,,, TPMR) }) +External (\A4GS, IntObj) +External (\A4GB, IntObj) + /* Current Resource Settings */ Method (_CRS, 0, Serialized) { @@ -211,5 +220,15 @@ PMIN = ^MCHC.TLUD << 20 PLEN = PMAX - PMIN + 1 + if (A4GS != 0) { + CreateQwordField(MCRS, ^PM02._MIN, MMIN) + CreateQwordField(MCRS, ^PM02._MAX, MMAX) + CreateQwordField(MCRS, ^PM02._LEN, MLEN) + /* Set 64bit MMIO resource base and length */ + MLEN = \A4GS + MMIN = \A4GB + MMAX = MMIN + MLEN - 1 + } + Return (MCRS) } diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 561c2fc..60fd635 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -1,8 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> +#include <acpi/acpigen.h> #include <cbmem.h> #include <commonlib/helpers.h> #include <console/console.h> +#include <cpu/cpu.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <stdint.h> @@ -14,6 +17,13 @@ #include "chip.h" #include "gm45.h" +static uint64_t get_touud(void) +{ + uint64_t touud = pci_read_config16(__pci_0_00_0, D0F0_TOUUD); + touud <<= 20; + return touud; +} + static void mch_domain_read_resources(struct device *dev) { u64 tom, touud; @@ -43,8 +53,7 @@ struct device *mch = pcidev_on_root(0, 0); /* Top of Upper Usable DRAM, including remap */ - touud = pci_read_config16(mch, D0F0_TOUUD); - touud <<= 20; + touud = get_touud(); /* Top of Lower Usable DRAM */ tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0; @@ -176,13 +185,32 @@ pci_write_config8(dev, D0F0_SMRAM, smram); } +static void set_above_4g_pci(const struct device *dev) +{ + const uint64_t touud = get_touud(); + const uint64_t len = POWER_OF_2(cpu_phys_address_size()) - touud; + + acpigen_write_scope("\\"); + acpigen_write_name_qword("A4GB", touud); + acpigen_write_name_qword("A4GS", len); + acpigen_pop_len(); + + printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n", touud, len); +} + +static void pci_domain_ssdt(const struct device *dev) +{ + generate_cpu_entries(dev); + set_above_4g_pci(dev); +} + static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, .init = mch_domain_init, .scan_bus = pci_domain_scan_bus, .write_acpi_tables = northbridge_write_acpi_tables, - .acpi_fill_ssdt = generate_cpu_entries, + .acpi_fill_ssdt = pci_domain_ssdt, .acpi_name = northbridge_acpi_name, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/64094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62a8a656481eba01add3d7d06b42e3352206df1b Gerrit-Change-Number: 64094 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cmn/fast-spi: Add BIOS MMIO window as reserved region
by Werner Zeh (Code Review) 06 May '22

06 May '22

Attention is currently required from: Nico Huber, Subrata Banik, Paul Menzel, Arthur Heymans. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64077 ) Change subject: soc/intel/cmn/fast-spi: Add BIOS MMIO window as reserved region ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/fast_spi/fast_spi.c: https://review.coreboot.org/c/coreboot/+/64077/comment/a2e0a805_67bb5e4b PS2, Line 528: mmio_resource(dev, 0, FLASH_BASE_ADDR / KiB, CONFIG_ROM_SIZE / KiB); > OK, looking at the APL spec it is really fixed to 16 MB. Will update. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/64077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf Gerrit-Change-Number: 64077 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 06 May 2022 10:13:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/fast-spi: Add BIOS MMIO window as reserved region
by Werner Zeh (Code Review) 06 May '22

06 May '22

Attention is currently required from: Nico Huber, Subrata Banik, Paul Menzel, Arthur Heymans. Hello build bot (Jenkins), Nico Huber, Subrata Banik, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64077 to look at the new patch set (#3). Change subject: soc/intel/cmn/fast-spi: Add BIOS MMIO window as reserved region ...................................................................... soc/intel/cmn/fast-spi: Add BIOS MMIO window as reserved region Add the boot flash MMIO window to the resources to report this region as reserved to the OS. This is done to stay consistent with the reserved memory ranges by coreboot and make the OS aware of them. As x86 systems preserves the upper 16 MiB below 4G for BIOS flash decoding use the complete window for reporting independent of the actually used SPI flash size. This will block the preserved MMIO window. Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/block/fast_spi/fast_spi.c 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/64077/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/64077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf Gerrit-Change-Number: 64077 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cmn/fast-spi: Add flash as reserved region
by Werner Zeh (Code Review) 06 May '22

06 May '22

Attention is currently required from: Nico Huber, Subrata Banik, Paul Menzel, Arthur Heymans. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64077 ) Change subject: soc/intel/cmn/fast-spi: Add flash as reserved region ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/fast_spi/fast_spi.c: https://review.coreboot.org/c/coreboot/+/64077/comment/2172dc4c_fa86f8fe PS2, Line 528: mmio_resource(dev, 0, FLASH_BASE_ADDR / KiB, CONFIG_ROM_SIZE / KiB); > > At least on APL I know that there could be a 8MB flash chip. […] OK, looking at the APL spec it is really fixed to 16 MB. Will update. -- To view, visit https://review.coreboot.org/c/coreboot/+/64077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf Gerrit-Change-Number: 64077 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 06 May 2022 10:04:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: intelblocks: Add function to enable GPE
by Maulik V Vaghela (Code Review) 06 May '22

06 May '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Eric Lai. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64089 ) Change subject: intelblocks: Add function to enable GPE ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/gpio/gpio.c: https://review.coreboot.org/c/coreboot/+/64089/comment/f64ce8b6_ca013acf PS2, Line 379: gpi_enable_smi(cfg, comm); > okay never mind. no good idea of this. […] Thank you Eric, Yes it won't be possible in single function. I'll push subsequent patch for small optimization but we would still need 3 functions. -- To view, visit https://review.coreboot.org/c/coreboot/+/64089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27e525f50c374c2cc9675e77eaa7774683a6e7c2 Gerrit-Change-Number: 64089 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 06 May 2022 09:29:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/fast-spi: Add flash as reserved region
by Arthur Heymans (Code Review) 06 May '22

06 May '22

Attention is currently required from: Nico Huber, Subrata Banik, Paul Menzel, Werner Zeh. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64077 ) Change subject: soc/intel/cmn/fast-spi: Add flash as reserved region ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/fast_spi/fast_spi.c: https://review.coreboot.org/c/coreboot/+/64077/comment/d634bcf5_7bac5138 PS2, Line 528: mmio_resource(dev, 0, FLASH_BASE_ADDR / KiB, CONFIG_ROM_SIZE / KiB); > At least on APL I know that there could be a 8MB flash chip. I find it more meaningful if we just report the used size but do not insist. The question here is: if you have an 8M flash, can you put a PCI bar below that or not? If not because the hardware is hardcoded to decode flash there then you want to report 16M, if you can put a PCI bar then only the memory mapped portion needs to be there (so not the full flash size anyway). The safest option is just to always reserve 16M. -- To view, visit https://review.coreboot.org/c/coreboot/+/64077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf Gerrit-Change-Number: 64077 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 06 May 2022 09:13:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/fast-spi: Add flash as reserved region
by Werner Zeh (Code Review) 06 May '22

06 May '22

Attention is currently required from: Nico Huber, Subrata Banik, Paul Menzel, Arthur Heymans. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64077 ) Change subject: soc/intel/cmn/fast-spi: Add flash as reserved region ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/fast_spi/fast_spi.c: https://review.coreboot.org/c/coreboot/+/64077/comment/09f93f52_0dd4f8af PS2, Line 528: mmio_resource(dev, 0, FLASH_BASE_ADDR / KiB, CONFIG_ROM_SIZE / KiB); > Always use 16M or can it decode something else than the BIOS in that region? At least on APL I know that there could be a 8MB flash chip. I find it more meaningful if we just report the used size but do not insist. -- To view, visit https://review.coreboot.org/c/coreboot/+/64077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf Gerrit-Change-Number: 64077 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 06 May 2022 09:07:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/fast-spi: Add flash as reserved region
by Arthur Heymans (Code Review) 06 May '22

06 May '22

Attention is currently required from: Nico Huber, Subrata Banik, Paul Menzel, Werner Zeh. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64077 ) Change subject: soc/intel/cmn/fast-spi: Add flash as reserved region ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/fast_spi/fast_spi.c: https://review.coreboot.org/c/coreboot/+/64077/comment/b1f6560e_9e4f4c46 PS2, Line 528: mmio_resource(dev, 0, FLASH_BASE_ADDR / KiB, CONFIG_ROM_SIZE / KiB); Always use 16M or can it decode something else than the BIOS in that region? -- To view, visit https://review.coreboot.org/c/coreboot/+/64077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf Gerrit-Change-Number: 64077 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 06 May 2022 09:04:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/fast-spi: Add flash as reserved region
by Werner Zeh (Code Review) 06 May '22

06 May '22

Attention is currently required from: Nico Huber, Subrata Banik, Paul Menzel, Arthur Heymans. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64077 ) Change subject: soc/intel/cmn/fast-spi: Add flash as reserved region ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/64077/comment/5b8b7c78_6389917e PS1, Line 11: > Maybe add some background for the change? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/64077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf Gerrit-Change-Number: 64077 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 06 May 2022 08:58:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: intelblocks: Add function to enable GPE
by Eric Lai (Code Review) 06 May '22

06 May '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64089 ) Change subject: intelblocks: Add function to enable GPE ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/gpio/gpio.c: https://review.coreboot.org/c/coreboot/+/64089/comment/0a4b56d1_55d0d45b PS2, Line 379: gpi_enable_smi(cfg, comm); > oh, sorry. Those not in the DW0. […] okay never mind. no good idea of this. we can't program the gpio pins by groups due to we can't make the gpio table in order unless we sort them... -- To view, visit https://review.coreboot.org/c/coreboot/+/64089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27e525f50c374c2cc9675e77eaa7774683a6e7c2 Gerrit-Change-Number: 64089 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 06 May 2022 08:52:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2022