coreboot-gerrit May 2022

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Change in coreboot[master]: mb/siemens/mc_ehl2: Invert PHY IRQ from falling edge to rising edge
by Mario Scheithauer (Code Review) 06 May '22

06 May '22

Attention is currently required from: Werner Zeh. Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63889 to look at the new patch set (#6). Change subject: mb/siemens/mc_ehl2: Invert PHY IRQ from falling edge to rising edge ...................................................................... mb/siemens/mc_ehl2: Invert PHY IRQ from falling edge to rising edge There are three external Marvel PHY 88E1512 on this mainboard. The PHY IRQ comes with a falling edge but the EHL MAC side needs a rising edge signal. For that reason, we need an inversion of the IRQ polarity. Change-Id: Id3caf582b4434b046779f5733e6ad9b57528ce35 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/63889/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3caf582b4434b046779f5733e6ad9b57528ce35 Gerrit-Change-Number: 63889 Gerrit-PatchSet: 6 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity
by Mario Scheithauer (Code Review) 06 May '22

06 May '22

Attention is currently required from: Paul Menzel, Mario Scheithauer. Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63888 to look at the new patch set (#6). Change subject: soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity ...................................................................... soc/intel/ehl: Provide function to change PHY-to-MAC IRQ polarity EHL MAC side expects a rising edge signal for an IRQ. Based on the mainboard wiring it could be necessary to change the interrupt polarity. This patch provides the functionality to invert a falling edge signal that comes from an external PHY. Change-Id: Ia314014c7cacbeb72629c773c8c0bb5f002a3f54 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/include/soc/tsn_gbe.h M src/soc/intel/elkhartlake/tsn_gbe.c 3 files changed, 123 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/63888/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia314014c7cacbeb72629c773c8c0bb5f002a3f54 Gerrit-Change-Number: 63888 Gerrit-PatchSet: 6 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/elkhartlake: Implement TSN GbE driver
by Mario Scheithauer (Code Review) 06 May '22

06 May '22

Attention is currently required from: Paul Menzel, Mario Scheithauer. Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63861 to look at the new patch set (#5). Change subject: soc/intel/elkhartlake: Implement TSN GbE driver ...................................................................... soc/intel/elkhartlake: Implement TSN GbE driver To be able to make EHL Ethernet GbE-TSN Controller configurable, a driver is required. Functionality comes in following patches. Change-Id: I7522914c56b74486bb088280d2686acf7027d1d3 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/Makefile.inc A src/soc/intel/elkhartlake/include/soc/tsn_gbe.h A src/soc/intel/elkhartlake/tsn_gbe.c 4 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/63861/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7522914c56b74486bb088280d2686acf7027d1d3 Gerrit-Change-Number: 63861 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/crota: enable wifi sar
by Scott Chao (Code Review) 06 May '22

06 May '22

Scott Chao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64096 ) Change subject: mb/google/brya/var/crota: enable wifi sar ...................................................................... mb/google/brya/var/crota: enable wifi sar BUG=b:216594621 BRANCH=none TEST=build pass and SAR table be changed according to tablet/ desktop mode Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: I62265e8931da48d20cf41e0c91ccb1a5b4bc1167 --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/crota/Makefile.inc A src/mainboard/google/brya/variants/crota/variant.c 3 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/64096/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index dfa8986..d475d76 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -186,6 +186,7 @@ config BOARD_GOOGLE_CROTA bool "-> Crota" select BOARD_GOOGLE_BASEBOARD_BRYA + select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_I2C_CS42L42 config BOARD_GOOGLE_MOLI diff --git a/src/mainboard/google/brya/variants/crota/Makefile.inc b/src/mainboard/google/brya/variants/crota/Makefile.inc index 7d1f886..f9d5990 100644 --- a/src/mainboard/google/brya/variants/crota/Makefile.inc +++ b/src/mainboard/google/brya/variants/crota/Makefile.inc @@ -4,3 +4,5 @@ romstage-y += memory.c ramstage-y += gpio.c + +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/crota/variant.c b/src/mainboard/google/brya/variants/crota/variant.c new file mode 100644 index 0000000..29f684aa --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/variant.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <sar.h> +#include <chip.h> +#include <fw_config.h> +#include <baseboard/variants.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/64096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62265e8931da48d20cf41e0c91ccb1a5b4bc1167 Gerrit-Change-Number: 64096 Gerrit-PatchSet: 1 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/gm45: Enable 64bit support
by Arthur Heymans (Code Review) 06 May '22

06 May '22

Attention is currently required from: Paul Menzel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64095 ) Change subject: nb/intel/gm45: Enable 64bit support ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/64095/comment/094f54cb_aadb55e4 PS1, Line 12: - Add a buildtest target in configs > Should a new 64-bit target be added? I think it's fine. Now some debug features also get buildtested in 64bit so that's bonus. -- To view, visit https://review.coreboot.org/c/coreboot/+/64095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb9c31a28ee231b87109b19c00ce2f8b48b5aefe Gerrit-Change-Number: 64095 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 06 May 2022 11:15:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: intelblocks: Add function to enable GPE
by Paul Menzel (Code Review) 06 May '22

06 May '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Eric Lai. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64089 ) Change subject: intelblocks: Add function to enable GPE ...................................................................... Patch Set 2: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/64089/comment/f0d5d3e5_69ae945f PS2, Line 9: was Present tense: is https://review.coreboot.org/c/coreboot/+/64089/comment/0870e067_aa867839 PS2, Line 18: which are capable of generating SCI. Could be shortened to: … capable of generating SCI. https://review.coreboot.org/c/coreboot/+/64089/comment/38d09919_edcf8d82 PS2, Line 20: This will help resolve issue where we don't see wake event GPIO in event : log. I always like an issue description in the beginning too. -- To view, visit https://review.coreboot.org/c/coreboot/+/64089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27e525f50c374c2cc9675e77eaa7774683a6e7c2 Gerrit-Change-Number: 64089 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 06 May 2022 10:34:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/gm45: Allow for PCI BARs above 4G
by Paul Menzel (Code Review) 06 May '22

06 May '22

Attention is currently required from: Arthur Heymans. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64094 ) Change subject: nb/intel/gm45: Allow for PCI BARs above 4G ...................................................................... Patch Set 1: (1 comment) File src/northbridge/intel/gm45/acpi/hostbridge.asl: https://review.coreboot.org/c/coreboot/+/64094/comment/6aacb5ee_5b46a78b PS1, Line 191: // PCI Memory Region above 4G TOUUD -> 1 << cpu_addr_bits Above `/* */` is used. -- To view, visit https://review.coreboot.org/c/coreboot/+/64094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62a8a656481eba01add3d7d06b42e3352206df1b Gerrit-Change-Number: 64094 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 06 May 2022 10:31:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/gm45: Enable 64bit support
by Paul Menzel (Code Review) 06 May '22

06 May '22

Attention is currently required from: Arthur Heymans. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64095 ) Change subject: nb/intel/gm45: Enable 64bit support ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/64095/comment/7ffd977a_d3d99732 PS1, Line 12: - Add a buildtest target in configs Should a new 64-bit target be added? -- To view, visit https://review.coreboot.org/c/coreboot/+/64095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb9c31a28ee231b87109b19c00ce2f8b48b5aefe Gerrit-Change-Number: 64095 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 06 May 2022 10:30:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/gm45: Enable 64bit support
by Paul Menzel (Code Review) 06 May '22

06 May '22

Attention is currently required from: Arthur Heymans. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64095 ) Change subject: nb/intel/gm45: Enable 64bit support ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb9c31a28ee231b87109b19c00ce2f8b48b5aefe Gerrit-Change-Number: 64095 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 06 May 2022 10:30:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/gm45: Enable 64bit support
by Arthur Heymans (Code Review) 06 May '22

06 May '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64095 ) Change subject: nb/intel/gm45: Enable 64bit support ...................................................................... nb/intel/gm45: Enable 64bit support This patch does the following: - Allow selecting 64bit from Kconfig - Fix up integer to pointer conversion that gcc complains about - Add a buildtest target in configs Tested on Thinkpad X200: boots fine to the payload Change-Id: Icb9c31a28ee231b87109b19c00ce2f8b48b5aefe Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M configs/config.lenovo_t400_vboot_and_debug M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/gm45/raminit_read_write_training.c M src/northbridge/intel/gm45/raminit_receive_enable_calibration.c 7 files changed, 16 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/64095/1 diff --git a/configs/config.lenovo_t400_vboot_and_debug b/configs/config.lenovo_t400_vboot_and_debug index 2923f94..39c17e6 100644 --- a/configs/config.lenovo_t400_vboot_and_debug +++ b/configs/config.lenovo_t400_vboot_and_debug @@ -12,3 +12,4 @@ CONFIG_DEBUG_ADA_CODE=y CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y CONFIG_VBOOT=y +CONFIG_USE_EXP_X86_64_SUPPORT=y diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 3f632a1..c186f01 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -12,6 +12,7 @@ select INTEL_EDID select INTEL_GMA_ACPI select INTEL_GMA_SSC_ALTERNATE_REF + select HAVE_EXP_X86_64_SUPPORT config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 4199f8b..46c8db3 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -37,7 +37,7 @@ /* setup somewhere */ pci_or_config16(igd, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - void *bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0); + void *bar = (void *)(uintptr_t)pci_read_config32(igd, PCI_BASE_ADDRESS_0); /* clear GTT, 2MB is enough (and should be safe) */ memset(bar, 0, 2<<20); diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 60fd635..315c54c 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -93,7 +93,7 @@ /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + delta_cbmem = tomk - ((uintptr_t)cbmem_top() >> 10); tomk -= delta_cbmem; uma_sizek += delta_cbmem; diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 35d71c0..4196edf 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1577,15 +1577,15 @@ const u32 rankaddr = raminit_get_rank_addr(ch, r); printk(BIOS_DEBUG, "JEDEC init @0x%08x\n", rankaddr); mchbar_clrsetbits32(DCC_MCHBAR, DCC_SET_EREG_MASK, DCC_SET_EREGx(2)); - read32((u32 *)(rankaddr | WL)); + read32p(rankaddr | WL); mchbar_clrsetbits32(DCC_MCHBAR, DCC_SET_EREG_MASK, DCC_SET_EREGx(3)); - read32((u32 *)rankaddr); + read32p(rankaddr); mchbar_clrsetbits32(DCC_MCHBAR, DCC_SET_EREG_MASK, DCC_SET_EREGx(1)); - read32((u32 *)(rankaddr | ODT_120OHMS | ODS_34OHMS)); + read32p(rankaddr | ODT_120OHMS | ODS_34OHMS); mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, DCC_SET_MREG); - read32((u32 *)(rankaddr | WR | DLL1 | CAS | INTERLEAVED)); + read32p(rankaddr | WR | DLL1 | CAS | INTERLEAVED); mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, DCC_SET_MREG); - read32((u32 *)(rankaddr | WR | CAS | INTERLEAVED)); + read32p(rankaddr | WR | CAS | INTERLEAVED); } } diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index be614ae..d3571df 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -96,7 +96,7 @@ for (i = 0; i < addresses->count; ++i) { unsigned int offset; for (offset = lane_offset; offset < 320; offset += 8) { - const u32 read = read32((u32 *)(addresses->addr[i] + offset)); + const u32 read = read32p(addresses->addr[i] + offset); const u32 good = read_training_schedule[offset >> 3]; if ((read & lane_mask) != (good & lane_mask)) return 0; @@ -211,7 +211,7 @@ /* Write test pattern. */ unsigned int offset; for (offset = 0; offset < 320; offset += 4) - write32((u32 *)(addresses.addr[i] + offset), + write32p(addresses.addr[i] + offset, read_training_schedule[offset >> 3]); } @@ -419,18 +419,18 @@ unsigned int off; for (off = 0; off < 640; off += 8) { const u32 pattern = write_training_schedule[off >> 3]; - write32((u32 *)(addr + off), pattern); - write32((u32 *)(addr + off + 4), pattern); + write32p(addr + off, pattern); + write32p(addr + off + 4, pattern); } mchbar_setbits8(0x78, 1); for (off = 0; off < 640; off += 8) { const u32 good = write_training_schedule[off >> 3]; - const u32 read1 = read32((u32 *)(addr + off)); + const u32 read1 = read32p(addr + off); if ((read1 & masks[0]) != (good & masks[0])) goto _bad_timing_out; - const u32 read2 = read32((u32 *)(addr + off + 4)); + const u32 read2 = read32p(addr + off + 4); if ((read2 & masks[1]) != (good & masks[1])) goto _bad_timing_out; } diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c index 1d20746..6ca8013 100644 --- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c +++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c @@ -128,7 +128,7 @@ mchbar_setbits32(mchbar, 1 << 9); /* Read from this channel. */ - read32((u32 *)raminit_get_rank_addr(channel, 0)); + read32p(raminit_get_rank_addr(channel, 0)); mchbar = 0x14b0 + (channel * 0x0100) + ((7 - lane) * 4); return mchbar_read32(mchbar) & (1 << 30); -- To view, visit https://review.coreboot.org/c/coreboot/+/64095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb9c31a28ee231b87109b19c00ce2f8b48b5aefe Gerrit-Change-Number: 64095 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit May 2022