coreboot-gerrit May 2022

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Change in coreboot[master]: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support
by Michał Żygowski (Code Review) 06 May '22

06 May '22

Attention is currently required from: Felix Singer, Michał Kopeć, Angel Pons, Michael Niewöhner. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 ) Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ...................................................................... Patch Set 15: (1 comment) File src/mainboard/clevo/tgl-u/mainboard.asl: https://review.coreboot.org/c/coreboot/+/62498/comment/c519655f_4e76cdb0 PS15, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ duplicated file with acpi/mainboard.asl? -- To view, visit https://review.coreboot.org/c/coreboot/+/62498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc Gerrit-Change-Number: 62498 Gerrit-PatchSet: 15 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Fri, 06 May 2022 13:56:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/crota: Change ELAN touchscreen i2c address
by Terry Chen (Code Review) 06 May '22

06 May '22

Terry Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64118 ) Change subject: mb/google/crota: Change ELAN touchscreen i2c address ...................................................................... mb/google/crota: Change ELAN touchscreen i2c address Change ELAN touchscreen i2c address to 0x16 BUG=b:231684121 TEST=local build and tested with ELAN touch screen Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Change-Id: Ide005a0681e236c3102090c1c36ab81926849000 --- M src/mainboard/google/brya/variants/crota/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/64118/1 diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb index 20820ac..d2603b5 100644 --- a/src/mainboard/google/brya/variants/crota/overridetree.cb +++ b/src/mainboard/google/brya/variants/crota/overridetree.cb @@ -155,7 +155,7 @@ end device ref i2c3 on chip drivers/i2c/hid - register "generic.hid" = ""ELAN9050"" + register "generic.hid" = ""ELAN900C"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" register "generic.probed" = "1" @@ -172,7 +172,7 @@ register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 0x10 on end + device i2c 0x16 on end end end device ref i2c5 on -- To view, visit https://review.coreboot.org/c/coreboot/+/64118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide005a0681e236c3102090c1c36ab81926849000 Gerrit-Change-Number: 64118 Gerrit-PatchSet: 1 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add missing ACPI device path names
by Felix Held (Code Review) 06 May '22

06 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63984 ) Change subject: soc/intel/alderlake: Add missing ACPI device path names ...................................................................... soc/intel/alderlake: Add missing ACPI device path names A few ACPI device path name handlers are missing. Add handling to ensure that these names are returned during acpi_device_path() calls. TEST=Built and tested on brya Signed-off-by: Tarun Tuli <taruntuli(a)google.com> Change-Id: I37d6dd5df921c931af72dd469c3f4067c61b0df3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63984 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/chip.c M src/soc/intel/common/block/uart/uart.c 2 files changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 699b39d..59f0066 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -75,6 +75,7 @@ case SA_DEVFN_TBT2: return "TRP2"; case SA_DEVFN_TBT3: return "TRP3"; case SA_DEVFN_IPU: return "IPU0"; + case SA_DEVFN_DPTF: return "DPTF"; case PCH_DEVFN_ISH: return "ISHB"; case PCH_DEVFN_XHCI: return "XHCI"; case PCH_DEVFN_I2C0: return "I2C0"; @@ -111,6 +112,9 @@ case PCH_DEVFN_HDA: return "HDAS"; case PCH_DEVFN_SMBUS: return "SBUS"; case PCH_DEVFN_GBE: return "GLAN"; + case PCH_DEVFN_SRAM: return "SRAM"; + case PCH_DEVFN_SPI: return "FSPI"; + case PCH_DEVFN_CSE: return "HEC1"; #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) case PCH_DEVFN_EMMC: return "EMMC"; #endif diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 12f2882..3e2e697 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -308,24 +308,28 @@ static const char *uart_acpi_name(const struct device *dev) { switch (dev->device) { + case PCI_DID_INTEL_ADP_P_UART0: case PCI_DID_INTEL_APL_UART0: case PCI_DID_INTEL_GLK_UART0: case PCI_DID_INTEL_SPT_UART0: case PCI_DID_INTEL_SPT_H_UART0: case PCI_DID_INTEL_CNP_H_UART0: return "UAR0"; + case PCI_DID_INTEL_ADP_P_UART1: case PCI_DID_INTEL_APL_UART1: case PCI_DID_INTEL_GLK_UART1: case PCI_DID_INTEL_SPT_UART1: case PCI_DID_INTEL_SPT_H_UART1: case PCI_DID_INTEL_CNP_H_UART1: return "UAR1"; + case PCI_DID_INTEL_ADP_P_UART2: case PCI_DID_INTEL_APL_UART2: case PCI_DID_INTEL_GLK_UART2: case PCI_DID_INTEL_SPT_UART2: case PCI_DID_INTEL_SPT_H_UART2: case PCI_DID_INTEL_CNP_H_UART2: return "UAR2"; + case PCI_DID_INTEL_ADP_P_UART3: case PCI_DID_INTEL_GLK_UART3: return "UAR3"; default: 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37d6dd5df921c931af72dd469c3f4067c61b0df3 Gerrit-Change-Number: 63984 Gerrit-PatchSet: 8 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brask/variants/moli: disable ASPM on pcie_rp 6
by Felix Held (Code Review) 06 May '22

06 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64042 ) Change subject: mb/google/brask/variants/moli: disable ASPM on pcie_rp 6 ...................................................................... mb/google/brask/variants/moli: disable ASPM on pcie_rp 6 Currently coreboot will hang on ASPM on pcie_rp 6, so disable ASPM to let it go into kernel. BUG=b:231400217 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: I79a80d97d168f40e58774e5652967d659daa323c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64042 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/brya/variants/moli/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index 2048b61..0783999 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -76,6 +76,7 @@ .clk_src = 5, .clk_req = 5, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_DISABLE, }" device pci 00.0 on end end # IntelI225V Ethernet NIC -- To view, visit https://review.coreboot.org/c/coreboot/+/64042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79a80d97d168f40e58774e5652967d659daa323c Gerrit-Change-Number: 64042 Gerrit-PatchSet: 3 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/variants/crota: Enable Bluetooth offload support
by Felix Held (Code Review) 06 May '22

06 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64019 ) Change subject: mb/google/brya/variants/crota: Enable Bluetooth offload support ...................................................................... mb/google/brya/variants/crota: Enable Bluetooth offload support Enable CnviBtAudioOffload UPD from Intel Guideline BUG=b:230418589 TEST=emerge-byra coreboot and verified pass Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Change-Id: I7ac54156cc4a8d824ed1c549d66fc369698a352c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64019 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/crota/gpio.c M src/mainboard/google/brya/variants/crota/overridetree.cb 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/crota/gpio.c b/src/mainboard/google/brya/variants/crota/gpio.c index 35803a0..a7def69 100644 --- a/src/mainboard/google/brya/variants/crota/gpio.c +++ b/src/mainboard/google/brya/variants/crota/gpio.c @@ -101,6 +101,14 @@ /* GPD11: LANPHYC ==> NC */ PAD_NC(GPD11, NONE), + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */ }; /* Early pad configuration in bootblock */ diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb index 20820ac..a8b7113 100644 --- a/src/mainboard/google/brya/variants/crota/overridetree.cb +++ b/src/mainboard/google/brya/variants/crota/overridetree.cb @@ -20,6 +20,7 @@ chip soc/intel/alderlake register "max_dram_speed_mts" = "4800" + register "cnvi_bt_audio_offload" = "1" # Acoustic settings register "acoustic_noise_mitigation" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/64019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ac54156cc4a8d824ed1c549d66fc369698a352c Gerrit-Change-Number: 64019 Gerrit-PatchSet: 7 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/include/espi: reduce visibility of IO/MMIO decode defines
by Felix Held (Code Review) 06 May '22

06 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64053 ) Change subject: soc/amd/common/include/espi: reduce visibility of IO/MMIO decode defines ...................................................................... soc/amd/common/include/espi: reduce visibility of IO/MMIO decode defines The eSPI decode range defines aren't and shouldn't be used directly from outside of the common AMD eSPI code which provides functions to abstract the register access, so move the defines from amdblocks/espi.h to espi_def.h inside the common AMD LPC/eSPI support directory to limit the visibility. The special I/O range decode bits need to stay in amdblocks/espi.h since those are used in the devicetree. Also update the indentation in espi_def.h so that the defines line up properly. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic4ea30a1a6f10e94d88bf3b29f86dee2da6b39b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64053 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/common/block/lpc/espi_def.h 2 files changed, 63 insertions(+), 60 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 45a220e..9717688 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -9,27 +9,11 @@ #define ESPI_OFFSET_FROM_BAR 0x10000 #define ESPI_DECODE 0x40 -#define ESPI_DECODE_MMIO_RANGE_EN(range) (1 << (((range) & 3) + 12)) -#define ESPI_DECODE_IO_RANGE_EN(range) (1 << (((range) & 3) + 8)) +/* more bits defined in soc/common/amd/blocks/lpc/espi_def.h */ #define ESPI_DECODE_IO_0x80_EN (1 << 2) #define ESPI_DECODE_IO_0X60_0X64_EN (1 << 1) #define ESPI_DECODE_IO_0X2E_0X2F_EN (1 << 0) -#define ESPI_IO_BASE_REG0 0x44 -#define ESPI_IO_BASE_REG1 0x48 -#define ESPI_IO_SIZE0 0x4c -#define ESPI_MMIO_BASE_REG0 0x50 -#define ESPI_MMIO_BASE_REG1 0x54 -#define ESPI_MMIO_BASE_REG2 0x58 -#define ESPI_MMIO_BASE_REG3 0x5c -#define ESPI_MMIO_SIZE_REG0 0x60 -#define ESPI_MMIO_SIZE_REG1 0x64 - -#define ESPI_IO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 2) -#define ESPI_IO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3)) -#define ESPI_MMIO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 4) -#define ESPI_MMIO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3) * 2) - #define ESPI_GENERIC_IO_WIN_COUNT 4 #define ESPI_GENERIC_IO_MAX_WIN_SIZE 0x100 #define ESPI_GENERIC_MMIO_WIN_COUNT 4 diff --git a/src/soc/amd/common/block/lpc/espi_def.h b/src/soc/amd/common/block/lpc/espi_def.h index ef61a13..dc398a9 100644 --- a/src/soc/amd/common/block/lpc/espi_def.h +++ b/src/soc/amd/common/block/lpc/espi_def.h @@ -3,53 +3,72 @@ #ifndef AMD_BLOCK_ESPI_DEF_H #define AMD_BLOCK_ESPI_DEF_H -#define ESPI_DN_TX_HDR0 0x00 -#define ESPI_DN_TX_HDR1 0x04 -#define ESPI_DN_TX_HDR2 0x08 -#define ESPI_DN_TX_DATA 0x0c +#define ESPI_DN_TX_HDR0 0x00 +#define ESPI_DN_TX_HDR1 0x04 +#define ESPI_DN_TX_HDR2 0x08 +#define ESPI_DN_TX_DATA 0x0c -#define ESPI_MASTER_CAP 0x2c -#define ESPI_VW_MAX_SIZE_SHIFT 13 -#define ESPI_VW_MAX_SIZE_MASK (0x3f << ESPI_VW_MAX_SIZE_SHIFT) +#define ESPI_MASTER_CAP 0x2c +#define ESPI_VW_MAX_SIZE_SHIFT 13 +#define ESPI_VW_MAX_SIZE_MASK (0x3f << ESPI_VW_MAX_SIZE_SHIFT) -#define ESPI_GLOBAL_CONTROL_0 0x30 -#define ESPI_WAIT_CNT_SHIFT 24 -#define ESPI_WAIT_CNT_MASK (0x3f << ESPI_WAIT_CNT_SHIFT) -#define ESPI_WDG_CNT_SHIFT 8 -#define ESPI_WDG_CNT_MASK (0xffff << ESPI_WDG_CNT_SHIFT) -#define ESPI_AL_IDLE_TIMER_SHIFT 4 -#define ESPI_AL_IDLE_TIMER_MASK (0x7 << ESPI_AL_IDLE_TIMER_SHIFT) -#define ESPI_AL_STOP_EN (1 << 3) -#define ESPI_PR_CLKGAT_EN (1 << 2) -#define ESPI_WAIT_CHKEN (1 << 1) -#define ESPI_WDG_EN (1 << 0) +#define ESPI_GLOBAL_CONTROL_0 0x30 +#define ESPI_WAIT_CNT_SHIFT 24 +#define ESPI_WAIT_CNT_MASK (0x3f << ESPI_WAIT_CNT_SHIFT) +#define ESPI_WDG_CNT_SHIFT 8 +#define ESPI_WDG_CNT_MASK (0xffff << ESPI_WDG_CNT_SHIFT) +#define ESPI_AL_IDLE_TIMER_SHIFT 4 +#define ESPI_AL_IDLE_TIMER_MASK (0x7 << ESPI_AL_IDLE_TIMER_SHIFT) +#define ESPI_AL_STOP_EN (1 << 3) +#define ESPI_PR_CLKGAT_EN (1 << 2) +#define ESPI_WAIT_CHKEN (1 << 1) +#define ESPI_WDG_EN (1 << 0) -#define ESPI_GLOBAL_CONTROL_1 0x34 -#define ESPI_ALERT_ENABLE (1 << 20) /* Sabrina and later SoCs */ -#define ESPI_RGCMD_INT_MAP_SHIFT 13 -#define ESPI_RGCMD_INT_MAP_MASK (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) -#define ESPI_RGCMD_INT(irq) ((irq) << ESPI_RGCMD_INT_MAP_SHIFT) -#define ESPI_RGCMD_INT_SMI (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) -#define ESPI_ERR_INT_MAP_SHIFT 8 -#define ESPI_ERR_INT_MAP_MASK (0x1f << ESPI_ERR_INT_MAP_SHIFT) -#define ESPI_ERR_INT(irq) ((irq) << ESPI_ERR_INT_MAP_SHIFT) -#define ESPI_ERR_INT_SMI (0x1f << ESPI_ERR_INT_MAP_SHIFT) -#define ESPI_SUB_DECODE_SLV_SHIFT 3 -#define ESPI_SUB_DECODE_SLV_MASK (0x3 << ESPI_SUB_DECODE_SLV_SHIFT) -#define ESPI_SUB_DECODE_EN (1 << 2) -#define ESPI_BUS_MASTER_EN (1 << 1) -#define ESPI_SW_RST (1 << 0) +#define ESPI_GLOBAL_CONTROL_1 0x34 +#define ESPI_ALERT_ENABLE (1 << 20) /* Sabrina and later SoCs */ +#define ESPI_RGCMD_INT_MAP_SHIFT 13 +#define ESPI_RGCMD_INT_MAP_MASK (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) +#define ESPI_RGCMD_INT(irq) ((irq) << ESPI_RGCMD_INT_MAP_SHIFT) +#define ESPI_RGCMD_INT_SMI (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) +#define ESPI_ERR_INT_MAP_SHIFT 8 +#define ESPI_ERR_INT_MAP_MASK (0x1f << ESPI_ERR_INT_MAP_SHIFT) +#define ESPI_ERR_INT(irq) ((irq) << ESPI_ERR_INT_MAP_SHIFT) +#define ESPI_ERR_INT_SMI (0x1f << ESPI_ERR_INT_MAP_SHIFT) +#define ESPI_SUB_DECODE_SLV_SHIFT 3 +#define ESPI_SUB_DECODE_SLV_MASK (0x3 << ESPI_SUB_DECODE_SLV_SHIFT) +#define ESPI_SUB_DECODE_EN (1 << 2) +#define ESPI_BUS_MASTER_EN (1 << 1) +#define ESPI_SW_RST (1 << 0) -#define ESPI_SLAVE0_INT_EN 0x6c -#define ESPI_SLAVE0_INT_STS 0x70 -#define ESPI_STATUS_DNCMD_COMPLETE (1 << 28) -#define ESPI_STATUS_NON_FATAL_ERROR (1 << 6) -#define ESPI_STATUS_FATAL_ERROR (1 << 5) -#define ESPI_STATUS_NO_RESPONSE (1 << 4) -#define ESPI_STATUS_CRC_ERR (1 << 2) -#define ESPI_STATUS_WAIT_TIMEOUT (1 << 1) -#define ESPI_STATUS_BUS_ERROR (1 << 0) +/* bits in ESPI_DECODE 0x40 */ +#define ESPI_DECODE_MMIO_RANGE_EN(range) (1 << (((range) & 3) + 12)) +#define ESPI_DECODE_IO_RANGE_EN(range) (1 << (((range) & 3) + 8)) -#define ESPI_RXVW_POLARITY 0xac +#define ESPI_IO_BASE_REG0 0x44 +#define ESPI_IO_BASE_REG1 0x48 +#define ESPI_IO_SIZE0 0x4c +#define ESPI_MMIO_BASE_REG0 0x50 +#define ESPI_MMIO_BASE_REG1 0x54 +#define ESPI_MMIO_BASE_REG2 0x58 +#define ESPI_MMIO_BASE_REG3 0x5c +#define ESPI_MMIO_SIZE_REG0 0x60 +#define ESPI_MMIO_SIZE_REG1 0x64 + +#define ESPI_SLAVE0_INT_EN 0x6c +#define ESPI_SLAVE0_INT_STS 0x70 +#define ESPI_STATUS_DNCMD_COMPLETE (1 << 28) +#define ESPI_STATUS_NON_FATAL_ERROR (1 << 6) +#define ESPI_STATUS_FATAL_ERROR (1 << 5) +#define ESPI_STATUS_NO_RESPONSE (1 << 4) +#define ESPI_STATUS_CRC_ERR (1 << 2) +#define ESPI_STATUS_WAIT_TIMEOUT (1 << 1) +#define ESPI_STATUS_BUS_ERROR (1 << 0) + +#define ESPI_RXVW_POLARITY 0xac + +#define ESPI_IO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 2) +#define ESPI_IO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3)) +#define ESPI_MMIO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 4) +#define ESPI_MMIO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3) * 2) #endif /* AMD_BLOCK_ESPI_DEF_H */ 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/64053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4ea30a1a6f10e94d88bf3b29f86dee2da6b39b5 Gerrit-Change-Number: 64053 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/include/espi: generalize IO/MMIO decode range macros
by Felix Held (Code Review) 06 May '22

06 May '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64052 ) Change subject: soc/amd/common/include/espi: generalize IO/MMIO decode range macros ...................................................................... soc/amd/common/include/espi: generalize IO/MMIO decode range macros Sabrina has more eSPI decode ranges than Picasso or Cezanne. Those registers are however not in one block where it's easy to calculate the addresses of a register from the index of the decode range. Within one group of decode range registers it's still easy to calculate the register address, so move the base address from within the macro to the instantiation of the macro as a preparation for adding the support for the additional ranges. TEST=Timeless build results in identical binary for Mandolin Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id309d955fa3558d660db37a2075240f938361e83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64052 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/common/block/lpc/espi_util.c 2 files changed, 8 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index cfba50b..45a220e 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -25,10 +25,10 @@ #define ESPI_MMIO_SIZE_REG0 0x60 #define ESPI_MMIO_SIZE_REG1 0x64 -#define ESPI_IO_RANGE_BASE(range) (ESPI_IO_BASE_REG0 + ((range) & 3) * 2) -#define ESPI_IO_RANGE_SIZE(range) (ESPI_IO_SIZE0 + ((range) & 3)) -#define ESPI_MMIO_RANGE_BASE(range) (ESPI_MMIO_BASE_REG0 + ((range) & 3) * 4) -#define ESPI_MMIO_RANGE_SIZE(range) (ESPI_MMIO_SIZE_REG0 + ((range) & 3) * 2) +#define ESPI_IO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 2) +#define ESPI_IO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3)) +#define ESPI_MMIO_RANGE_BASE_REG(base, range) ((base) + ((range) & 3) * 4) +#define ESPI_MMIO_RANGE_SIZE_REG(base, range) ((base) + ((range) & 3) * 2) #define ESPI_GENERIC_IO_WIN_COUNT 4 #define ESPI_GENERIC_IO_MAX_WIN_SIZE 0x100 diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index c4d15e4..a5f43f4 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -72,22 +72,22 @@ static inline unsigned int espi_io_range_base_reg(unsigned int idx) { - return ESPI_IO_RANGE_BASE(idx); + return ESPI_IO_RANGE_BASE_REG(ESPI_IO_BASE_REG0, idx); } static inline unsigned int espi_io_range_size_reg(unsigned int idx) { - return ESPI_IO_RANGE_SIZE(idx); + return ESPI_IO_RANGE_SIZE_REG(ESPI_IO_SIZE0, idx); } static inline unsigned int espi_mmio_range_base_reg(unsigned int idx) { - return ESPI_MMIO_RANGE_BASE(idx); + return ESPI_MMIO_RANGE_BASE_REG(ESPI_MMIO_BASE_REG0, idx); } static inline unsigned int espi_mmio_range_size_reg(unsigned int idx) { - return ESPI_MMIO_RANGE_SIZE(idx); + return ESPI_MMIO_RANGE_SIZE_REG(ESPI_MMIO_SIZE_REG0, idx); } static void espi_enable_decode(uint32_t decode_en) -- To view, visit https://review.coreboot.org/c/coreboot/+/64052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id309d955fa3558d660db37a2075240f938361e83 Gerrit-Change-Number: 64052 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: libpayload/nvme: Fix controller disablement in (de)init sequence
by Thomas Heijligen (Code Review) 06 May '22

06 May '22

Attention is currently required from: Nico Huber. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63935 ) Change subject: libpayload/nvme: Fix controller disablement in (de)init sequence ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I125de55d7f1a7c9f070437190c5a08a288b274f8 Gerrit-Change-Number: 63935 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 06 May 2022 13:34:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/nvme: Test for NVMe-command-set bit individually
by Thomas Heijligen (Code Review) 06 May '22

06 May '22

Attention is currently required from: Nico Huber. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63934 ) Change subject: libpayload/nvme: Test for NVMe-command-set bit individually ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29a693cf8cc13775e94dc671e8d0412ad86fef9c Gerrit-Change-Number: 63934 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 06 May 2022 13:27:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/nvme: Fix error paths of nvme_init()
by Thomas Heijligen (Code Review) 06 May '22

06 May '22

Attention is currently required from: Nico Huber. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63933 ) Change subject: libpayload/nvme: Fix error paths of nvme_init() ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib83c7785d6e0dc3c44fbd50a30694c74932750d6 Gerrit-Change-Number: 63933 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 06 May 2022 13:17:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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