coreboot-gerrit May 2022

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Change in coreboot[master]: vc/amd/fsp/sabrina/UsbUpd: update USB settings structure to match FSP
by Felix Held (Code Review) 06 May '22

06 May '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64129 ) Change subject: vc/amd/fsp/sabrina/UsbUpd: update USB settings structure to match FSP ...................................................................... vc/amd/fsp/sabrina/UsbUpd: update USB settings structure to match FSP This file started as a copy from Cezanne. Sabrina has less USB ports than Cezanne. Also the struct definition of fch_usb2_phy has changed and FSP_USB_STRUCT_MINOR_VERSION is also updated. TEST=None Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I1ef2b62373b178d729b3230d0d8539986cc631ae --- M src/vendorcode/amd/fsp/sabrina/FspUsb.h 1 file changed, 17 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/64129/1 diff --git a/src/vendorcode/amd/fsp/sabrina/FspUsb.h b/src/vendorcode/amd/fsp/sabrina/FspUsb.h index fea1fee..54827be 100644 --- a/src/vendorcode/amd/fsp/sabrina/FspUsb.h +++ b/src/vendorcode/amd/fsp/sabrina/FspUsb.h @@ -4,29 +4,32 @@ #include <FspUpd.h> #define FSP_USB_STRUCT_MAJOR_VERSION 0xd -#define FSP_USB_STRUCT_MINOR_VERSION 0x6 +#define FSP_USB_STRUCT_MINOR_VERSION 0xe #define USB2_PORT_COUNT 8 #define USB3_PORT_COUNT 4 #define USBC_COMBO_PHY_COUNT 2 struct fch_usb2_phy { - uint8_t compdstune; ///< COMPDSTUNE - uint8_t sqrxtune; ///< SQRXTUNE - uint8_t txfslstune; ///< TXFSLSTUNE - uint8_t txpreempamptune; ///< TXPREEMPAMPTUNE - uint8_t txpreemppulsetune; ///< TXPREEMPPULSETUNE - uint8_t txrisetune; ///< TXRISETUNE - uint8_t txvreftune; ///< TXVREFTUNE - uint8_t txhsxvtune; ///< TXHSXVTUNE - uint8_t txrestune; ///< TXRESTUNE + uint8_t compdistune; ///< COMPDISTUNE + uint8_t pllbtune; ///< PLLBTUNE + uint8_t pllitune; ///< PLLITUNE + uint8_t pllptune; ///< PLLPTUNE + uint8_t sqrxtune; ///< SQRXTUNE + uint8_t txfslstune; ///< TXFSLSTUNE + uint8_t txpreempamptune; ///< TXPREEMPAMPTUNE + uint8_t txpreemppulsetune; ///< TXPREEMPPULSETUNE + uint8_t txrisetune; ///< TXRISETUNE + uint8_t txvreftune; ///< TXVREFTUNE + uint8_t txhsxvtune; ///< TXHSXVTUNE + uint8_t txrestune; ///< TXRESTUNE } __packed; struct fch_usb3_phy { - uint8_t tx_term_ctrl; ///< tx_term_ctrl - uint8_t rx_term_ctrl; ///< rx_term_ctrl - uint8_t tx_vboost_lvl_en; ///< TX_VBOOST_LVL_EN - uint8_t tx_vboost_lvl; ///< TX_VBOOST_LVL + uint8_t tx_term_ctrl; ///< tx_term_ctrl + uint8_t rx_term_ctrl; ///< rx_term_ctrl + uint8_t tx_vboost_lvl_en; ///< TX_VBOOST_LVL_EN + uint8_t tx_vboost_lvl; ///< TX_VBOOST_LVL } __packed; #define USB0_PORT0 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/64129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ef2b62373b178d729b3230d0d8539986cc631ae Gerrit-Change-Number: 64129 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/sabrina/fsp_m_params: add defines for FSP USB struct version
by Felix Held (Code Review) 06 May '22

06 May '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64128 ) Change subject: soc/amd/sabrina/fsp_m_params: add defines for FSP USB struct version ...................................................................... soc/amd/sabrina/fsp_m_params: add defines for FSP USB struct version Add and use defines instead of magic values in fsp_m_params.c. The values will be updated to match the Sabrina FSP in a follow-up commit. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I91da9e9d2b95e169dd73153766f24cf8afbfa4ef --- M src/soc/amd/sabrina/fsp_m_params.c M src/vendorcode/amd/fsp/sabrina/FspUsb.h 2 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/64128/1 diff --git a/src/soc/amd/sabrina/fsp_m_params.c b/src/soc/amd/sabrina/fsp_m_params.c index cf3278f..18de29a 100644 --- a/src/soc/amd/sabrina/fsp_m_params.c +++ b/src/soc/amd/sabrina/fsp_m_params.c @@ -143,8 +143,8 @@ if (config->usb_phy_custom) { mcfg->usb_phy = (struct usb_phy_config *)&config->usb_phy; - mcfg->usb_phy->Version_Major = 0xd; - mcfg->usb_phy->Version_Minor = 0x6; + mcfg->usb_phy->Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; + mcfg->usb_phy->Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; mcfg->usb_phy->TableLength = sizeof(usb_phy_config); } else { mcfg->usb_phy = NULL; diff --git a/src/vendorcode/amd/fsp/sabrina/FspUsb.h b/src/vendorcode/amd/fsp/sabrina/FspUsb.h index 6563cac..fea1fee 100644 --- a/src/vendorcode/amd/fsp/sabrina/FspUsb.h +++ b/src/vendorcode/amd/fsp/sabrina/FspUsb.h @@ -3,6 +3,9 @@ #include <FspUpd.h> +#define FSP_USB_STRUCT_MAJOR_VERSION 0xd +#define FSP_USB_STRUCT_MINOR_VERSION 0x6 + #define USB2_PORT_COUNT 8 #define USB3_PORT_COUNT 4 #define USBC_COMBO_PHY_COUNT 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91da9e9d2b95e169dd73153766f24cf8afbfa4ef Gerrit-Change-Number: 64128 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/sabrina/fsp_m_params: don't hard-code USB PHY config table size
by Felix Held (Code Review) 06 May '22

06 May '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64127 ) Change subject: soc/amd/sabrina/fsp_m_params: don't hard-code USB PHY config table size ...................................................................... soc/amd/sabrina/fsp_m_params: don't hard-code USB PHY config table size Use sizeof instead of having a hard-coded struct length. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3c39d770a7719e30572e71b6a6c24fa2ad4a9426 --- M src/soc/amd/sabrina/fsp_m_params.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/64127/1 diff --git a/src/soc/amd/sabrina/fsp_m_params.c b/src/soc/amd/sabrina/fsp_m_params.c index 8a83008..cf3278f 100644 --- a/src/soc/amd/sabrina/fsp_m_params.c +++ b/src/soc/amd/sabrina/fsp_m_params.c @@ -145,7 +145,7 @@ mcfg->usb_phy = (struct usb_phy_config *)&config->usb_phy; mcfg->usb_phy->Version_Major = 0xd; mcfg->usb_phy->Version_Minor = 0x6; - mcfg->usb_phy->TableLength = 100; + mcfg->usb_phy->TableLength = sizeof(usb_phy_config); } else { mcfg->usb_phy = NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/64127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c39d770a7719e30572e71b6a6c24fa2ad4a9426 Gerrit-Change-Number: 64127 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne/fsp_m_params: add defines for FSP USB struct version
by Raul Rangel (Code Review) 06 May '22

06 May '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Fred Reitberger, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64126 ) Change subject: soc/amd/cezanne/fsp_m_params: add defines for FSP USB struct version ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0e33eb0af5310ab4610ea8951688464c4960260 Gerrit-Change-Number: 64126 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 06 May 2022 15:56:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/fsp_m_params: add defines for FSP USB struct version
by Felix Held (Code Review) 06 May '22

06 May '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64126 ) Change subject: soc/amd/cezanne/fsp_m_params: add defines for FSP USB struct version ...................................................................... soc/amd/cezanne/fsp_m_params: add defines for FSP USB struct version Add and use defines instead of magic values in fsp_m_params.c. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie0e33eb0af5310ab4610ea8951688464c4960260 --- M src/soc/amd/cezanne/fsp_m_params.c M src/vendorcode/amd/fsp/cezanne/FspUsb.h 2 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/64126/1 diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 0c423ea..7105cfb 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -150,8 +150,8 @@ if (config->usb_phy_custom) { mcfg->usb_phy = (struct usb_phy_config *)&config->usb_phy; - mcfg->usb_phy->Version_Major = 0xd; - mcfg->usb_phy->Version_Minor = 0x6; + mcfg->usb_phy->Version_Major = FSP_USB_STRUCT_MAJOR_VERSION; + mcfg->usb_phy->Version_Minor = FSP_USB_STRUCT_MINOR_VERSION; mcfg->usb_phy->TableLength = sizeof(usb_phy_config); } else { mcfg->usb_phy = NULL; diff --git a/src/vendorcode/amd/fsp/cezanne/FspUsb.h b/src/vendorcode/amd/fsp/cezanne/FspUsb.h index 6563cac..fea1fee 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspUsb.h +++ b/src/vendorcode/amd/fsp/cezanne/FspUsb.h @@ -3,6 +3,9 @@ #include <FspUpd.h> +#define FSP_USB_STRUCT_MAJOR_VERSION 0xd +#define FSP_USB_STRUCT_MINOR_VERSION 0x6 + #define USB2_PORT_COUNT 8 #define USB3_PORT_COUNT 4 #define USBC_COMBO_PHY_COUNT 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0e33eb0af5310ab4610ea8951688464c4960260 Gerrit-Change-Number: 64126 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush/devicetree: use defines for ComboPhyStaticConfig
by Raul Rangel (Code Review) 06 May '22

06 May '22

Attention is currently required from: Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64124 ) Change subject: mb/google/guybrush/devicetree: use defines for ComboPhyStaticConfig ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2707d017909b7516e5d8711c8f4e2914165ed10d Gerrit-Change-Number: 64124 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 06 May 2022 15:50:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: provide a list of D-states to enter LPM
by Tim Wawrzynczak (Code Review) 06 May '22

06 May '22

Attention is currently required from: Lance Zhao, Tarun Tuli, Subrata Banik, Angel Pons. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63969 ) Change subject: soc/intel/alderlake: provide a list of D-states to enter LPM ...................................................................... Patch Set 21: Code-Review+2 (1 comment) Patchset: PS21: Thanks Tarun! What this allows the Linux kernel to do is display any discrepancies between the actual D state and the D states listed in this table during the S0ix entry flow (https://github.com/torvalds/linux/blob/master/drivers/acpi/x86/s2idle.c#L292) (when PM debug message are enabled via sysfs) -- To view, visit https://review.coreboot.org/c/coreboot/+/63969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437 Gerrit-Change-Number: 63969 Gerrit-PatchSet: 21 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 06 May 2022 15:47:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/fsp_m_params: don't hard-code USB PHY config table size
by Felix Held (Code Review) 06 May '22

06 May '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64125 ) Change subject: soc/amd/cezanne/fsp_m_params: don't hard-code USB PHY config table size ...................................................................... soc/amd/cezanne/fsp_m_params: don't hard-code USB PHY config table size Use sizeof instead of having a hard-coded struct length. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I85dc2fce11d9a670b2037d8a6a694177cfaa2177 --- M src/soc/amd/cezanne/fsp_m_params.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/64125/1 diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 8c9e5a1..0c423ea 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -152,7 +152,7 @@ mcfg->usb_phy = (struct usb_phy_config *)&config->usb_phy; mcfg->usb_phy->Version_Major = 0xd; mcfg->usb_phy->Version_Minor = 0x6; - mcfg->usb_phy->TableLength = 100; + mcfg->usb_phy->TableLength = sizeof(usb_phy_config); } else { mcfg->usb_phy = NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/64125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85dc2fce11d9a670b2037d8a6a694177cfaa2177 Gerrit-Change-Number: 64125 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush/devicetree: use defines for ComboPhyStaticConfig
by Felix Held (Code Review) 06 May '22

06 May '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64124 ) Change subject: mb/google/guybrush/devicetree: use defines for ComboPhyStaticConfig ...................................................................... mb/google/guybrush/devicetree: use defines for ComboPhyStaticConfig Use the existing definitions from FspUsb.h instead of magic values for the ComboPhyStaticConfig settings in the mainboard's devicetree. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2707d017909b7516e5d8711c8f4e2914165ed10d --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/64124/1 diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 696e16d..0b69af9 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -217,8 +217,8 @@ .tx_vboost_lvl_en=1, .tx_vboost_lvl=5, }, - .ComboPhyStaticConfig[0] = 0, - .ComboPhyStaticConfig[1] = 0, + .ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C, + .ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C, .BatteryChargerEnable = 0, .PhyP3CpmP4Support = 0, }" diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index 85581d2..8270b14 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -154,8 +154,8 @@ .tx_vboost_lvl_en=1, .tx_vboost_lvl=5, }, - .ComboPhyStaticConfig[0] = 0, - .ComboPhyStaticConfig[1] = 0, + .ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C, + .ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C, .BatteryChargerEnable = 0, .PhyP3CpmP4Support = 0, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/64124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2707d017909b7516e5d8711c8f4e2914165ed10d Gerrit-Change-Number: 64124 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/kinox: Disable thunderbolt interface
by Tim Wawrzynczak (Code Review) 06 May '22

06 May '22

Attention is currently required from: Dtrain Hsu, Zhuohao Lee, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64087 ) Change subject: mb/google/brya/var/kinox: Disable thunderbolt interface ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I944680dd1f41ac6f375015a3a138eb00c41b58a7 Gerrit-Change-Number: 64087 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 06 May 2022 15:38:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2022