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Change subject: intelblocks: Add function to enable GPE
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/64089/comment/e50a91b8_65f7879b
PS2, Line 379: gpi_enable_smi(cfg, comm);
> My idea is config all DW0 in one time. Just add up all the BITs. […]
oh, sorry. Those not in the DW0. In the case probably we can use the static to store them and write in one time?
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Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64089 )
Change subject: intelblocks: Add function to enable GPE
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/64089/comment/11ef2235_8c31c812
PS2, Line 379: gpi_enable_smi(cfg, comm);
> Hi Eric, […]
My idea is config all DW0 in one time. Just add up all the BITs. So all the function just return the bits, probably like below:
DW0_Val |= gpio_configure_owner;
DW0_Val |= gpi_enable_smi;
DW0_Val |= gpi_enable_nmi;
DW0_Val |= gpi_enable_gpe;
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63763 )
Change subject: device/Kconfig: Change ON_DEVICE_ROM_LOAD default
......................................................................
Patch Set 1:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63763/comment/5621d5ea_fb1ccd75
PS1, Line 9: is not a good
: idea in an open source project
> > Why? I understand the security perspective, and would only mention that. […]
Done
Patchset:
PS1:
> Should we add something to configs/ to keep the path build tested?
> Currently there are Galileo configs enabling it, but they might be
> gone soon.
Done
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/63763/comment/77f0a56e_a22a19bd
PS1, Line 180: If you are concerned about security, you might want to
: disable this option, but it might leave your system in a state of
: degraded functionality.
> This would need to be updated.
Done
https://review.coreboot.org/c/coreboot/+/63763/comment/51d105ed_27f19b21
PS1, Line 180: If you are concerned about security, you might want to
: disable this option, but it might leave your system in a state of
: degraded functionality.
> This would need to be updated.
Done
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Change subject: intelblocks: Add function to enable GPE
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/64089/comment/c6f1daf4_783b13c0
PS2, Line 379: gpi_enable_smi(cfg, comm);
> Can we "or" all the configs and set it once? In this case, we don't have to read/write many times. […]
Hi Eric,
If I understand correctly, you mean we should do all SMI, NMI and GPE setting in single function?
Only issue is, we have 3 different register offset for all 3 but we can move common part of getting bit value and community to common function.
Let me know your thoughts :)
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Hello build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63763
to look at the new patch set (#4).
Change subject: device/Kconfig: Change ON_DEVICE_ROM_LOAD default
......................................................................
device/Kconfig: Change ON_DEVICE_ROM_LOAD default
Defaulting to 'y' to load optional blobs from PCI cards is not a good
idea in an open source project: optional blobs should be opt-in and
not opt-out. On top of that PCI option roms are a security issue.
This would affect desktop use cases that expect graphic output in the
payload on an external GPU.
To keep buildtesting this option add it to one of the configs.
Change-Id: I70b4ca6bf83f2d2fa591e30967e481d67e1b9f87
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M configs/config.lenovo_t400_vboot_and_debug
M src/device/Kconfig
2 files changed, 4 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/63763/4
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Hello build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63763
to look at the new patch set (#3).
Change subject: device/Kconfig: Change ON_DEVICE_ROM_LOAD default
......................................................................
device/Kconfig: Change ON_DEVICE_ROM_LOAD default
Defaulting to 'y' to load optional blobs from PCI cards is not a good
idea in an open source project. On top of that PCI option roms are a
security issue.
This would affect desktop use cases that expect graphic output in the
payload on an external GPU.
To keep buildtesting this option add it to one of the configs.
Change-Id: I70b4ca6bf83f2d2fa591e30967e481d67e1b9f87
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M configs/config.lenovo_t400_vboot_and_debug
M src/device/Kconfig
2 files changed, 4 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/63763/3
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Hello build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63763
to look at the new patch set (#2).
Change subject: device/Kconfig: Change ON_DEVICE_ROM_LOAD default
......................................................................
device/Kconfig: Change ON_DEVICE_ROM_LOAD default
Defaulting to 'y' to load optional blobs from PCI cards is not a good
idea in an open source project. On top of that PCI option roms are a
security issue.
This would affect desktop use cases that expect graphic output in the
payload on an external GPU.
To keep buildtesting this option add it to one of the configs.
Change-Id: I70b4ca6bf83f2d2fa591e30967e481d67e1b9f87
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M configs/config.lenovo_t400_vboot_and_debug
M src/device/Kconfig
2 files changed, 2 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/63763/2
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Hello build bot (Jenkins), Nico Huber, Subrata Banik, Arthur Heymans,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/cmn/fast-spi: Add flash as reserved region
......................................................................
soc/intel/cmn/fast-spi: Add flash as reserved region
Add the boot flash MMIO window to the resources to report this region as
reserved to the OS. This is done to stay consistent with the reserved
memory ranges by coreboot and make the OS aware of them.
Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
1 file changed, 12 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/64077/2
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Change subject: src/soc/intel/cmn/fast-spi: Add SSDT extension to fast SPI driver
......................................................................
src/soc/intel/cmn/fast-spi: Add SSDT extension to fast SPI driver
If the SPI controller is hidden from the OS (which is default on Apollo
Lake) then OS has no chance to probe the device and therefore can not be
aware of the resources this PCI device occupies. If the OS needs to move
some resources for a reason it can happen that the new allocated window
will be shadowed by the hidden PCI device resource and hence causing a
conflict. As a result this MMIO window will be inaccessible from the OS
which will cause issues in applications. For instance on Apollo Lake
this causes flashrom to stop working.
This patch adds a SSDT extension for the PCI device if it is hidden from
the OS and reports the occupied resource via ACPI to the OS. Since there
is no defined ACPI ID for the fast SPI controller available now, the
generic one (PNP0C02) is used.
Test: Boot mc_apl4 and make sure flashrom works again.
Change-Id: Ia16dfe6e001188aad26418afe0f04c53ecfd56f1
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
1 file changed, 65 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/64076/2
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