coreboot-gerrit May 2022

coreboot-gerrit@coreboot.org

1 participants
6166 discussions

Change in coreboot[master]: mb/google/nissa/var/nivviks: Update pen detect gpio
by Eric Lai (Code Review) 06 May '22

06 May '22

Attention is currently required from: Subrata Banik, Kangheui Won, Reka Norman, Tim Wawrzynczak. Hello Subrata Banik, Kangheui Won, Reka Norman, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64091 to look at the new patch set (#2). Change subject: mb/google/nissa/var/nivviks: Update pen detect gpio ...................................................................... mb/google/nissa/var/nivviks: Update pen detect gpio If use GPIO_DRIVER_LOCK will cause kernel driver can't change to IRQ. Thus, we need to set it as INT in coreboot to make the IRQ work. BUG=b:223476974 TEST=evtest work as expected. Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 0 Properties: Testing ... (interrupt to exit) Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: -------------- SYN_REPORT ------------ Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I5f9fdfb2622b4b955da216119e74c6f7d5795d36 --- M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/64091/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f9fdfb2622b4b955da216119e74c6f7d5795d36 Gerrit-Change-Number: 64091 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/nissa/var/nivviks: Update pen detect gpio
by Eric Lai (Code Review) 06 May '22

06 May '22

Eric Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64091 ) Change subject: mb/google/nissa/var/nivviks: Update pen detect gpio ...................................................................... mb/google/nissa/var/nivviks: Update pen detect gpio If use GPIO_DRIVER_LOCK will cause kernel driver can't change to IRQ. Thus, we need to set it as INT in coreboot to make the IRQ work. BUG=b:223476974 TEST=evtest work as expected. Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 0 Properties: Testing ... (interrupt to exit) Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: -------------- SYN_REPORT ------------ Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I5f9fdfb2622b4b955da216119e74c6f7d5795d36 --- M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/64091/1 diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c index ba3c8c5..53ec244 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c @@ -234,7 +234,7 @@ /* F12 : GSXDOUT ==> WWAN_RST_L */ PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), /* F13 : GSXSLOAD ==> SOC_PEN_DETECT_R_ODL */ - PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_F13, NONE, LOCK_CONFIG), + PAD_CFG_GPI_INT_LOCK(GPP_F13, NONE, EDGE_BOTH, LOCK_CONFIG), /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG), /* F15 : GSXSRESET# ==> SOC_PEN_DETECT_ODL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/64091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f9fdfb2622b4b955da216119e74c6f7d5795d36 Gerrit-Change-Number: 64091 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge
by Werner Zeh (Code Review) 06 May '22

06 May '22

Attention is currently required from: Mario Scheithauer. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63931 ) Change subject: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge ...................................................................... Patch Set 4: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63931/comment/fa2a9635_f81ddb64 PS2, Line 9: On this mainboard there are legacy PCI device, which are connected to > I have reworded the statement. Ack Commit Message: https://review.coreboot.org/c/coreboot/+/63931/comment/740074bf_743d8417 PS4, Line 10: PCI PCIe https://review.coreboot.org/c/coreboot/+/63931/comment/fd8c8db5_b617e5ae PS4, Line 10: ports are in use clock outputs of this bridge are used. -- To view, visit https://review.coreboot.org/c/coreboot/+/63931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171 Gerrit-Change-Number: 63931 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Fri, 06 May 2022 07:19:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Adjust log level of calibration for spmi clock
by Rex-BC Chen (Code Review) 06 May '22

06 May '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64090 ) Change subject: soc/mediatek: Adjust log level of calibration for spmi clock ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I148b4aeaaeb10e1c269a8eccbb19e8d8e17e40ff Gerrit-Change-Number: 64090 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 06 May 2022 07:18:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Adjust log level of calibration for spmi clock
by Rex-BC Chen (Code Review) 06 May '22

06 May '22

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64090 ) Change subject: soc/mediatek: Adjust log level of calibration for spmi clock ...................................................................... soc/mediatek: Adjust log level of calibration for spmi clock It's expeted that the mismatch logs will be shown when doing calibration for spmi clock. If it is failed to do calibration for spmi clock for all data, the system will enter "die". Therefore, we adjust the log level from BIOS_ERR to BIOS_WARNING. BUG=b:231531254 TEST=emerge-cherry coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I148b4aeaaeb10e1c269a8eccbb19e8d8e17e40ff --- M src/soc/mediatek/common/pmif_spmi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/64090/1 diff --git a/src/soc/mediatek/common/pmif_spmi.c b/src/soc/mediatek/common/pmif_spmi.c index 5f68c23..55c3f36 100644 --- a/src/soc/mediatek/common/pmif_spmi.c +++ b/src/soc/mediatek/common/pmif_spmi.c @@ -44,14 +44,14 @@ pmif_arb->read(pmif_arb, slvid, MT6315_READ_TEST, &rdata); if (rdata != MT6315_DEFAULT_VALUE_READ) { - printk(BIOS_ERR, "%s next, slvid:%d rdata = 0x%x.\n", + printk(BIOS_WARNING, "%s next, slvid:%d rdata = 0x%x.\n", __func__, slvid, rdata); return -E_NODEV; } pmif_arb->read(pmif_arb, slvid, MT6315_READ_TEST_1, &rdata); if (rdata != MT6315_DEFAULT_VALUE_READ) { - printk(BIOS_ERR, "%s next, slvid:%d rdata = 0x%x.\n", + printk(BIOS_WARNING, "%s next, slvid:%d rdata = 0x%x.\n", __func__, slvid, rdata); return -E_NODEV; } -- To view, visit https://review.coreboot.org/c/coreboot/+/64090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I148b4aeaaeb10e1c269a8eccbb19e8d8e17e40ff Gerrit-Change-Number: 64090 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: intelblocks: Add function to enable GPE
by Eric Lai (Code Review) 06 May '22

06 May '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64089 ) Change subject: intelblocks: Add function to enable GPE ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27e525f50c374c2cc9675e77eaa7774683a6e7c2 Gerrit-Change-Number: 64089 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 06 May 2022 07:15:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: intelblocks: Add function to enable GPE
by Eric Lai (Code Review) 06 May '22

06 May '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64089 ) Change subject: intelblocks: Add function to enable GPE ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/gpio/gpio.c: https://review.coreboot.org/c/coreboot/+/64089/comment/98adaef2_861e1f87 PS2, Line 379: gpi_enable_smi(cfg, comm); Can we "or" all the configs and set it once? In this case, we don't have to read/write many times. Put the all DW0 setting together. We can do it in the follow patch for sure. -- To view, visit https://review.coreboot.org/c/coreboot/+/64089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27e525f50c374c2cc9675e77eaa7774683a6e7c2 Gerrit-Change-Number: 64089 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 06 May 2022 07:15:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/inte/*/gpio; Add GPE_EN and GPE_STS register definition
by Eric Lai (Code Review) 06 May '22

06 May '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64088 ) Change subject: soc/inte/*/gpio; Add GPE_EN and GPE_STS register definition ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b813b30b8b360f8eccbf539b57387310e380560 Gerrit-Change-Number: 64088 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 06 May 2022 07:11:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/inte/*/gpio; Add GPE_EN and GPE_STS register definition
by Maulik V Vaghela (Code Review) 06 May '22

06 May '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64088 ) Change subject: soc/inte/*/gpio; Add GPE_EN and GPE_STS register definition ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/include/intelblocks/gpio.h: https://review.coreboot.org/c/coreboot/+/64088/comment/33d97de0_eac862e2 PS1, Line 129: > tab? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/64088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b813b30b8b360f8eccbf539b57387310e380560 Gerrit-Change-Number: 64088 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 06 May 2022 07:07:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: intelblocks: Add function to enable GPE
by Maulik V Vaghela (Code Review) 06 May '22

06 May '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64089 ) Change subject: intelblocks: Add function to enable GPE ...................................................................... Patch Set 1: (3 comments) Patchset: PS1: > Thanks Maulik for fixing this in proper. Thank you Subrata :) File src/soc/intel/common/block/gpio/gpio.c: https://review.coreboot.org/c/coreboot/+/64089/comment/206e9674_b8fd8722 PS1, Line 173: > tabs ? Ack. Done https://review.coreboot.org/c/coreboot/+/64089/comment/de9db84d_8c65e486 PS1, Line 193: if( > if ( Ack. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/64089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27e525f50c374c2cc9675e77eaa7774683a6e7c2 Gerrit-Change-Number: 64089 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 06 May 2022 07:07:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2022