coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/alderlake: Add HID for DPTF Power Participant
by Paul Fagerburg (Code Review) 01 Apr '22

01 Apr '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63202 ) Change subject: soc/intel/alderlake: Add HID for DPTF Power Participant ...................................................................... soc/intel/alderlake: Add HID for DPTF Power Participant BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check TPWR device HID Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I82507a3c0a521adbb8dec5520fd6d2ea3782c60e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63202 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/alderlake/dptf.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/dptf.c b/src/soc/intel/alderlake/dptf.c index 37754db..59243ba 100644 --- a/src/soc/intel/alderlake/dptf.c +++ b/src/soc/intel/alderlake/dptf.c @@ -12,6 +12,8 @@ .fan_hid = "INTC1048", /* _HID for the toplevel TPCH device, typically \_SB.TPCH */ .tpch_device_hid = "INTC1049", + /* _HID for the toplevel TPWR device, typically \_SB.DPTF.TPWR */ + .tpwr_device_hid = "INTC1060", .tpch_method_names = { .set_fivr_low_clock_method = "RFC0", -- To view, visit https://review.coreboot.org/c/coreboot/+/63202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82507a3c0a521adbb8dec5520fd6d2ea3782c60e Gerrit-Change-Number: 63202 Gerrit-PatchSet: 6 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/dptf: Add support for Power participant
by Paul Fagerburg (Code Review) 01 Apr '22

01 Apr '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62944 ) Change subject: drivers/intel/dptf: Add support for Power participant ...................................................................... drivers/intel/dptf: Add support for Power participant As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) Add support for TPWR device under \_SB.DPTF BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check TPWR device Device (TPWR) { Name (_HID, "INTC1060") // _HID: Hardware ID Name (_UID, "TPWR") // _UID: Unique ID Name (_STR, "Power Participant") // _STR: Description String Name (PTYP, 0x11) Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62944 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/acpi/acpigen_dptf.c M src/drivers/intel/dptf/Kconfig M src/drivers/intel/dptf/dptf.c M src/drivers/intel/dptf/dptf.h M src/include/acpi/acpigen_dptf.h 5 files changed, 34 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/acpi/acpigen_dptf.c b/src/acpi/acpigen_dptf.c index f2ae769..4a5bd09 100644 --- a/src/acpi/acpigen_dptf.c +++ b/src/acpi/acpigen_dptf.c @@ -74,6 +74,8 @@ return "TSR4"; case DPTF_TPCH: return "TPCH"; + case DPTF_POWER: + return "TPWR"; default: return ""; } diff --git a/src/drivers/intel/dptf/Kconfig b/src/drivers/intel/dptf/Kconfig index 6f590b9..a7a5760 100644 --- a/src/drivers/intel/dptf/Kconfig +++ b/src/drivers/intel/dptf/Kconfig @@ -12,3 +12,10 @@ help When enabled, chip driver/intel/dptf will publish information to the SSDT for the TPCH device. + +config DRIVERS_INTEL_DPTF_SUPPORTS_TPWR + def_bool n + depends on DRIVERS_INTEL_DPTF + help + When enabled, chip driver/intel/dptf will publish information to the + SSDT for TPWR device. diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index 71a25b6..ecb338b 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -14,10 +14,12 @@ DPTF_GENERIC_PARTICIPANT_TYPE_TSR = 0x3, DPTF_GENERIC_PARTICIPANT_TYPE_TPCH = 0x5, DPTF_GENERIC_PARTICIPANT_TYPE_CHARGER = 0xB, + DPTF_GENERIC_PARTICIPANT_TYPE_POWER = 0x11, }; #define DEFAULT_CHARGER_STR "Battery Charger" #define DEFAULT_TPCH_STR "Intel PCH FIVR Participant" +#define DEFAULT_POWER_STR "Power Participant" #define PMC_IPC_COMMAND_FIVR_SIZE 0x8 @@ -368,6 +370,24 @@ acpigen_write_device_end(); /* TPCH Device */ } +static void write_create_tpwr(const struct dptf_platform_info *platform_info) +{ + acpigen_write_device("TPWR"); + acpigen_write_name("_HID"); + if (platform_info->tpwr_device_hid != NULL) + dptf_write_hid(platform_info->use_eisa_hids, platform_info->tpwr_device_hid); + acpigen_write_name_string("_UID", "TPWR"); + acpigen_write_name_string("_STR", DEFAULT_POWER_STR); + acpigen_write_name_integer("PTYP", DPTF_GENERIC_PARTICIPANT_TYPE_POWER); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_write_device_end(); /* TPWR Power Participant Device */ +} + +static void write_tpwr_methods(const struct dptf_platform_info *platform_info) +{ + write_create_tpwr(platform_info); +} + /* \_SB.DPTF - note: leaves the Scope open for child devices */ static void write_open_dptf_device(const struct device *dev, const struct dptf_platform_info *platform_info) @@ -406,6 +426,9 @@ if (CONFIG(DRIVERS_INTEL_DPTF_SUPPORTS_TPCH)) write_tpch_methods(platform_info); + if (CONFIG(DRIVERS_INTEL_DPTF_SUPPORTS_TPWR)) + write_tpwr_methods(platform_info); + acpigen_pop_len(); /* DPTF Device (write_open_dptf_device) */ acpigen_pop_len(); /* Scope */ } diff --git a/src/drivers/intel/dptf/dptf.h b/src/drivers/intel/dptf/dptf.h index 877aad9..c80e64a 100644 --- a/src/drivers/intel/dptf/dptf.h +++ b/src/drivers/intel/dptf/dptf.h @@ -15,6 +15,7 @@ const char *generic_hid; const char *fan_hid; const char *tpch_device_hid; + const char *tpwr_device_hid; struct { const char *set_fivr_low_clock_method; const char *set_fivr_high_clock_method; diff --git a/src/include/acpi/acpigen_dptf.h b/src/include/acpi/acpigen_dptf.h index 758398d..0d49452 100644 --- a/src/include/acpi/acpigen_dptf.h +++ b/src/include/acpi/acpigen_dptf.h @@ -26,6 +26,7 @@ DPTF_TEMP_SENSOR_3, DPTF_TEMP_SENSOR_4, DPTF_TPCH, + DPTF_POWER, DPTF_PARTICIPANT_COUNT, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/62944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 Gerrit-Change-Number: 62944 Gerrit-PatchSet: 9 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ix
by Paul Fagerburg (Code Review) 01 Apr '22

01 Apr '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63191 ) Change subject: mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ix ...................................................................... mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ix Turn off the NFC power which is controlled by GPP_D3 to save power in S0ix states. For an USB device, the S0ix hook is needed for the on/off operations to take place. BUG=b:202737385 BRANCH=firmware-brya-14505.B TEST=measure the voltage of GPP_D3 in S0ix states Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: I69588c82dfde1744c45c7aff3ac05b80bb16a8f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63191 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/brask/include/variant/gpio.h M src/mainboard/google/brya/variants/brask/variant.c 2 files changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brask/include/variant/gpio.h b/src/mainboard/google/brya/variants/brask/include/variant/gpio.h index 27c87b3..4c28cc9 100644 --- a/src/mainboard/google/brya/variants/brask/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/brask/include/variant/gpio.h @@ -5,4 +5,6 @@ #include <baseboard/gpio.h> +#define NFC_POWER GPP_D3 + #endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/brya/variants/brask/variant.c b/src/mainboard/google/brya/variants/brask/variant.c index 04105db..3f1796e 100644 --- a/src/mainboard/google/brya/variants/brask/variant.c +++ b/src/mainboard/google/brya/variants/brask/variant.c @@ -3,9 +3,19 @@ #include <chip.h> #include <fw_config.h> #include <baseboard/variants.h> +#include <variant/gpio.h> +#include <acpi/acpigen.h> void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, NAU88L25B_I2S)); } + +void variant_generate_s0ix_hook(enum s0ix_entry entry) +{ + if (entry == S0IX_ENTRY) + acpigen_soc_clear_tx_gpio(NFC_POWER); + else if (entry == S0IX_EXIT) + acpigen_soc_set_tx_gpio(NFC_POWER); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/63191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69588c82dfde1744c45c7aff3ac05b80bb16a8f3 Gerrit-Change-Number: 63191 Gerrit-PatchSet: 4 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86/Kconfig: Drop obsolete fixed ramstage symbols
by Paul Fagerburg (Code Review) 01 Apr '22

01 Apr '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63215 ) Change subject: arch/x86/Kconfig: Drop obsolete fixed ramstage symbols ...................................................................... arch/x86/Kconfig: Drop obsolete fixed ramstage symbols On x86 ramstage is always relocated at runtime in cbmem so there is no need to have this configurable in Kconfig. Change-Id: I01b2335d0b82bea8f885ee5ca9814351bbf2aa3c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63215 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/Kconfig M src/arch/x86/include/arch/memlayout.h M src/arch/x86/memlayout.ld M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld M src/soc/amd/picasso/Kconfig M src/soc/amd/sabrina/Kconfig 7 files changed, 4 insertions(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 4052b2e..e9fce50 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -118,22 +118,6 @@ default n depends on ARCH_X86 -# Set the rambase for systems that still need it, only 5 chipsets as of -# Sep 2018. This value was 0x100000, chosen to match the entry point -# of Linux 2.2 in 1999. The new value, 14 MiB, makes a lot more sense -# for as long as we need it; with luck, that won't be much longer. -# In the long term, both RAMBASE and RAMTOP should be removed. -# This value leaves more than 1 MiB which is required for fam10 -# and broadwell_de. -config RAMBASE - hex - default 0xe00000 - -config RAMTOP - hex - default 0x1000000 - depends on ARCH_X86 - # Traditionally BIOS region on SPI flash boot media was memory mapped right below # 4G and it was the last region in the IFD. This way translation between CPU # address space to flash address was trivial. However some IFDs on newer SoCs diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index aea5a7d..4f5d21a 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -3,10 +3,6 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H -#if (CONFIG_RAMTOP == 0) -# error "CONFIG_RAMTOP not configured" -#endif - /* Intel386 psABI requires a 16 byte aligned stack. */ #define ARCH_STACK_ALIGN_SIZE 16 diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index a0b0f53..bbd5450 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -13,7 +13,8 @@ * conditionalize with macros. */ #if ENV_RAMSTAGE - RAMSTAGE(CONFIG_RAMBASE, 8M) + /* Relocated at runtime in cbmem so the address does not matter. */ + RAMSTAGE(64M, 8M) #elif ENV_ROMSTAGE /* The 1M size is not allocated. It's just for basic size checking. diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 48944c8..8522d3f 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -217,10 +217,6 @@ hex default 0x40000 if CBFS_PRELOAD -config RAMBASE - hex - default 0x10000000 - config RO_REGION_ONLY string depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index f17043b..4c2a740 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -111,7 +111,8 @@ EARLY_RESERVED_DRAM_END(.) - RAMSTAGE(CONFIG_RAMBASE, 8M) + /* Relocated at runtime in cbmem so the address does not matter. */ + RAMSTAGE(64M, 8M) } #if ENV_BOOTBLOCK diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 84af18c..b005f9b 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -207,10 +207,6 @@ Sets the size of DRAM allocation for verstage in linker script if running as a separate stage on x86. -config RAMBASE - hex - default 0x10000000 - config ECAM_MMCONF_BASE_ADDRESS default 0xF8000000 diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 3df7a4b..66719a6 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -222,10 +222,6 @@ hex default 0x40000 if CBFS_PRELOAD -config RAMBASE - hex - default 0x10000000 - config RO_REGION_ONLY string depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A -- To view, visit https://review.coreboot.org/c/coreboot/+/63215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01b2335d0b82bea8f885ee5ca9814351bbf2aa3c Gerrit-Change-Number: 63215 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/primus{4es}: Decrease touchscreen T3 timing to 200ms
by Paul Fagerburg (Code Review) 01 Apr '22

01 Apr '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63201 ) Change subject: mb/google/brya/var/primus{4es}: Decrease touchscreen T3 timing to 200ms ...................................................................... mb/google/brya/var/primus{4es}: Decrease touchscreen T3 timing to 200ms We set T3 as 300ms to meet Elan's spec, but the resume/suspend times are greater than 500ms, which is the spec for Chromebooks. The actual kernel timing has been measured, and given the ACPI delay after deasserting reset in addition to the delay until the kernel driver accesses the device, delaying only 200ms in the ACPI method is also sufficient to meet the 300ms requirement. BUG=b:223936777 BRANCH=none TEST=build and test touchscreen function on DUT. TEST=suspend, wake DUT and check touchscreen function. Change-Id: I6b04cf6392d924aed01ca36b720f889b88d92311 Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63201 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index c01516c..8fc1f14 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -221,7 +221,7 @@ register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "300" + register "generic.reset_delay_ms" = "200" register "generic.reset_off_delay_ms" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb index e2b8d02..d56cc06 100644 --- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb @@ -208,7 +208,7 @@ register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "300" + register "generic.reset_delay_ms" = "200" register "generic.reset_off_delay_ms" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" -- To view, visit https://review.coreboot.org/c/coreboot/+/63201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b04cf6392d924aed01ca36b720f889b88d92311 Gerrit-Change-Number: 63201 Gerrit-PatchSet: 2 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/nereid: Enable AUX DC biasing on C0 and C1
by Paul Fagerburg (Code Review) 01 Apr '22

01 Apr '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63199 ) Change subject: mb/google/brya/var/nereid: Enable AUX DC biasing on C0 and C1 ...................................................................... mb/google/brya/var/nereid: Enable AUX DC biasing on C0 and C1 C0 has no redriver, so enable SBU muxing in the SoC. C1 has a redriver which does SBU muxing, so disable SBU muxing in the SoC. However, this also disables AUX biasing when the pins are configured as NF6. So instead configure the C1 AUX bias pins as GPO. BUG=b:227259673 TEST=Voltages are correct on the C0 and C1 AUX bias pins Change-Id: Ic0af662ecc1c6cee15b4ae98cb02deeefc93a71e Signed-off-by: Reka Norman <rekanorman(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63199 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sam McNally <sammc(a)google.com> --- M src/mainboard/google/brya/variants/nereid/gpio.c M src/mainboard/google/brya/variants/nereid/overridetree.cb 2 files changed, 9 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/nereid/gpio.c b/src/mainboard/google/brya/variants/nereid/gpio.c index 0f68ecf..f9ef8c9 100644 --- a/src/mainboard/google/brya/variants/nereid/gpio.c +++ b/src/mainboard/google/brya/variants/nereid/gpio.c @@ -9,6 +9,10 @@ static const struct pad_config override_gpio_table[] = { /* A8 : WWAN_RF_DISABLE_ODL */ PAD_NC(GPP_A8, NONE), + /* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), + /* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), /* B5 : SOC_I2C_SUB_SDA */ PAD_NC(GPP_B5, NONE), diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb index 50c98ce..806c74d 100644 --- a/src/mainboard/google/brya/variants/nereid/overridetree.cb +++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb @@ -9,8 +9,12 @@ chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" + # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC. + # Bit 2 - C1 has a redriver which does SBU muxing. + # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1. + register "tcss_aux_ori" = "1" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" - register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0af662ecc1c6cee15b4ae98cb02deeefc93a71e Gerrit-Change-Number: 63199 Gerrit-PatchSet: 4 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/fsp1_1: Reduce scope of functions
by Paul Fagerburg (Code Review) 01 Apr '22

01 Apr '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63203 ) Change subject: drivers/intel/fsp1_1: Reduce scope of functions ...................................................................... drivers/intel/fsp1_1: Reduce scope of functions Reduce scope of get_next_hob and drop unused functions. Change-Id: I81007295ed2d1592c4d829cbb277c0726d89ea4b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63203 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/drivers/intel/fsp1_1/hob.c M src/drivers/intel/fsp1_1/include/fsp/util.h 2 files changed, 1 insertion(+), 30 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index 076dd5f..bba32d1 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -24,7 +24,7 @@ } /* Returns the next instance of a HOB type from the starting HOB. */ -void *get_next_hob(uint16_t type, const void *hob_start) +static void *get_next_hob(uint16_t type, const void *hob_start) { EFI_PEI_HOB_POINTERS hob; @@ -44,12 +44,6 @@ return NULL; } -/* Returns the first instance of a HOB type among the whole HOB list. */ -void *get_first_hob(uint16_t type) -{ - return get_next_hob(type, get_hob_list()); -} - /* Returns the next instance of the matched GUID HOB from the starting HOB. */ void *get_next_guid_hob(const EFI_GUID *guid, const void *hob_start) { @@ -66,14 +60,6 @@ } /* - * Returns the first instance of the matched GUID HOB among the whole HOB list. - */ -void *get_first_guid_hob(const EFI_GUID *guid) -{ - return get_next_guid_hob(guid, get_hob_list()); -} - -/* * Returns the next instance of the matching resource HOB from the starting HOB. */ void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start) @@ -90,15 +76,6 @@ return hob.Raw; } -/* - * Returns the first instance of the matching resource HOB among the whole HOB - * list. - */ -void *get_first_resource_hob(const EFI_GUID *guid) -{ - return get_next_resource_hob(guid, get_hob_list()); -} - static void print_hob_mem_attributes(void *hob_ptr) { EFI_MEMORY_TYPE hob_mem_type; diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index e1fb596..0c9a1fa 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -24,10 +24,7 @@ void fsp_notify(u32 phase); void print_hob_type_structure(u16 hob_type, void *hob_list_ptr); void print_fsp_info(FSP_INFO_HEADER *fsp_header); -void *get_next_type_guid_hob(UINT16 type, const EFI_GUID *guid, - const void *hob_start); void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start); -void *get_first_resource_hob(const EFI_GUID *guid); void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old, uint64_t new); void report_fsp_output(void); @@ -80,10 +77,7 @@ #endif void *get_hob_list(void); -void *get_next_hob(uint16_t type, const void *hob_start); -void *get_first_hob(uint16_t type); void *get_next_guid_hob(const EFI_GUID *guid, const void *hob_start); -void *get_first_guid_hob(const EFI_GUID *guid); asmlinkage void chipset_teardown_car_main(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/63203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81007295ed2d1592c4d829cbb277c0726d89ea4b Gerrit-Change-Number: 63203 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/clevo/tgl-u: add new board L14xMU
by 9elements QA (Code Review) 01 Apr '22

01 Apr '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59548 ) Change subject: mb/clevo/tgl-u: add new board L14xMU ...................................................................... Patch Set 20: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/98674 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/98673 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/98672 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/98671 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/98670 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/98669 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/98668 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/98667 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/98666 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/98665 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/98664 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/98663 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/98662 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/98661 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/98660 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/98659 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/59548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Gerrit-Change-Number: 59548 Gerrit-PatchSet: 20 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 12:52:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/tgl-u: add new board L14xMU
by Michael Niewöhner (Code Review) 01 Apr '22

01 Apr '22

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59548 ) Change subject: mb/clevo/tgl-u: add new board L14xMU ...................................................................... mb/clevo/tgl-u: add new board L14xMU Add new board Clevo L14xMU (TGL). GPIOs were configured based on schematics. Tested and working: - On-board RAM (M471A1G44AB0-CWE) - DIMM slot (tested Crucial CT16G4SFD8266.16FJ1 / MTA16ATF2G64HZ-2G6J1) - Graphics (GOP driver), including HDMI - Keyboard - I2C touchpad (including interrupt) - TPM (with interrupt on Windows, only polling on Linux [1]) - microSD Card reader - both NVME ports - Speakers - Microphone - Camera - WLAN/BT (CNVi) - All USB2/3 ports including Type-C - Thunderbolt detects my work laptop in TB Control Center (I couldn't test anything more due to security policy.) - TianoCore - internal flashing with flashrom on vendor firmware Note on TPM: The vendor sets Intel PTT to default-on in newer CSME images, which conflicts with the dTPM. Currently, there are two ways to make it work: 1) Boot vendor firmware once to let it disable PTT via CSME firmware feature override. 2) Use Intel Flash Image Tool (FIT) to set "initial power-up state" to disabled. Boots fine: - Debian testing, unstable (Linux 5.16.14, 5.17.0-rc6) - Windows 10 21H2 (Build 19044.1586) Untested: - Thunderbolt (see above) - Type-C DisplayPort - S-ATA Doesn't work: - TPM interrupt on Linux [1] - All EC related functions - EC driver is WIP - WLAN/BT (PCIe) - gets detected but can't be enabled - 3G/LTE (not powered without EC driver) - Fn-Keys - S0ix - UCSI - Fan control - Battery info [1] https://lkml.org/lkml/2021/5/1/103 Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59548 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/clevo/tgl-u/Kconfig A src/mainboard/clevo/tgl-u/Kconfig.name A src/mainboard/clevo/tgl-u/Makefile.inc A src/mainboard/clevo/tgl-u/board_info.txt A src/mainboard/clevo/tgl-u/bootblock.c A src/mainboard/clevo/tgl-u/cmos.default A src/mainboard/clevo/tgl-u/cmos.layout A src/mainboard/clevo/tgl-u/dsdt.asl A src/mainboard/clevo/tgl-u/include/variant/gpio.h A src/mainboard/clevo/tgl-u/include/variant/ramstage.h A src/mainboard/clevo/tgl-u/include/variant/romstage.h A src/mainboard/clevo/tgl-u/ramstage.c A src/mainboard/clevo/tgl-u/romstage.c A src/mainboard/clevo/tgl-u/spd/samsung-M471A1G44AB0-CWE.spd.hex A src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.inc A src/mainboard/clevo/tgl-u/variants/l140mu/board_info.txt A src/mainboard/clevo/tgl-u/variants/l140mu/data.vbt A src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb A src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c A src/mainboard/clevo/tgl-u/variants/l140mu/gpio_early.c A src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c A src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c A src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c 23 files changed, 888 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/clevo/tgl-u/Kconfig b/src/mainboard/clevo/tgl-u/Kconfig new file mode 100644 index 0000000..a97d3d8 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/Kconfig @@ -0,0 +1,63 @@ +config BOARD_CLEVO_TGLU_COMMON + def_bool n + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_HID + select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SOC_INTEL_TIGERLAKE + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config BOARD_CLEVO_L140MU + select BOARD_CLEVO_TGLU_COMMON + select HAVE_SPD_IN_CBFS + +if BOARD_CLEVO_TGLU_COMMON + +config MAINBOARD_DIR + default "clevo/tgl-u" + +config VARIANT_DIR + default "l140mu" if BOARD_CLEVO_L140MU + +config MAINBOARD_PART_NUMBER + default "L140MU" if BOARD_CLEVO_L140MU + +config MAINBOARD_VERSION + default "2.2A" if BOARD_CLEVO_L140MU + +config DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config CBFS_SIZE + default 0xb00000 if BOARD_CLEVO_L140MU + +config CONSOLE_POST + default y + +config UART_FOR_CONSOLE + default 2 + +config TPM_PIRQ + default 0x77 if BOARD_CLEVO_L140MU # GPP_C9_IRQ + +config POST_DEVICE + default n + +config SEABIOS_PS2_TIMEOUT + default 500 + +config USE_PM_ACPI_TIMER + default n + +endif diff --git a/src/mainboard/clevo/tgl-u/Kconfig.name b/src/mainboard/clevo/tgl-u/Kconfig.name new file mode 100644 index 0000000..97d2874 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/Kconfig.name @@ -0,0 +1,4 @@ +comment "Tiger Lake U" + +config BOARD_CLEVO_L140MU + bool "L140MU / L141MU / L142MU" diff --git a/src/mainboard/clevo/tgl-u/Makefile.inc b/src/mainboard/clevo/tgl-u/Makefile.inc new file mode 100644 index 0000000..2909300 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/Makefile.inc @@ -0,0 +1,14 @@ +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c + +romstage-y += romstage.c +romstage-y += variants/$(VARIANT_DIR)/romstage.c + +ramstage-y += ramstage.c +ramstage-y += variants/$(VARIANT_DIR)/ramstage.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/clevo/tgl-u/board_info.txt b/src/mainboard/clevo/tgl-u/board_info.txt new file mode 100644 index 0000000..6710993 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Clevo +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/clevo/tgl-u/bootblock.c b/src/mainboard/clevo/tgl-u/bootblock.c new file mode 100644 index 0000000..b351fbd --- /dev/null +++ b/src/mainboard/clevo/tgl-u/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <variant/gpio.h> + +void bootblock_mainboard_early_init(void) +{ + variant_configure_early_gpios(); +} diff --git a/src/mainboard/clevo/tgl-u/cmos.default b/src/mainboard/clevo/tgl-u/cmos.default new file mode 100644 index 0000000..f3330e5 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/cmos.default @@ -0,0 +1,3 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable diff --git a/src/mainboard/clevo/tgl-u/cmos.layout b/src/mainboard/clevo/tgl-u/cmos.layout new file mode 100644 index 0000000..4f76221 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/cmos.layout @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# start-bit length config config-ID name +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: southbridge +410 2 e 7 power_on_after_fail + +# ----------------------------------------------------------------- +# vboot nv area +800 128 r 0 vbnv + +# ----------------------------------------------------------------- +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep + +# ----------------------------------------------------------------- +checksums + +checksum 392 799 984 diff --git a/src/mainboard/clevo/tgl-u/dsdt.asl b/src/mainboard/clevo/tgl-u/dsdt.asl new file mode 100644 index 0000000..ac02fe9 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/dsdt.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/tigerlake/acpi/southbridge.asl> + #include <soc/intel/tigerlake/acpi/tcss.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + + Scope (\_SB.PCI0.LPCB) + { + #include <drivers/pc80/pc/ps2_controller.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/clevo/tgl-u/include/variant/gpio.h b/src/mainboard/clevo/tgl-u/include/variant/gpio.h new file mode 100644 index 0000000..95d5762 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/include/variant/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); + +#endif diff --git a/src/mainboard/clevo/tgl-u/include/variant/ramstage.h b/src/mainboard/clevo/tgl-u/include/variant/ramstage.h new file mode 100644 index 0000000..4b5b29d --- /dev/null +++ b/src/mainboard/clevo/tgl-u/include/variant/ramstage.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_RAMSTAGE_H +#define VARIANT_RAMSTAGE_H + +void variant_configure_fsps(FSP_S_CONFIG *params); + +#endif diff --git a/src/mainboard/clevo/tgl-u/include/variant/romstage.h b/src/mainboard/clevo/tgl-u/include/variant/romstage.h new file mode 100644 index 0000000..cfcc6ab --- /dev/null +++ b/src/mainboard/clevo/tgl-u/include/variant/romstage.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_ROMSTAGE_H +#define VARIANT_ROMSTAGE_H + +void variant_configure_fspm(FSPM_UPD *memupd); + +#endif diff --git a/src/mainboard/clevo/tgl-u/ramstage.c b/src/mainboard/clevo/tgl-u/ramstage.c new file mode 100644 index 0000000..0768e51 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/ramstage.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <soc/ramstage.h> +#include <variant/gpio.h> +#include <variant/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + variant_configure_fsps(params); +} + +static void init_mainboard(void *chip_info) +{ + variant_configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; diff --git a/src/mainboard/clevo/tgl-u/romstage.c b/src/mainboard/clevo/tgl-u/romstage.c new file mode 100644 index 0000000..5ba6c56 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/romstage.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/romstage.h> +#include <variant/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + variant_configure_fspm(memupd); +} diff --git a/src/mainboard/clevo/tgl-u/spd/samsung-M471A1G44AB0-CWE.spd.hex b/src/mainboard/clevo/tgl-u/spd/samsung-M471A1G44AB0-CWE.spd.hex new file mode 100644 index 0000000..91442ca --- /dev/null +++ b/src/mainboard/clevo/tgl-u/spd/samsung-M471A1G44AB0-CWE.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 E8 F5 +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 31 47 +34 34 41 42 30 2D 43 57 45 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.inc b/src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.inc new file mode 100644 index 0000000..10cb4fb --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.inc @@ -0,0 +1 @@ +SPD_SOURCES = samsung-M471A1G44AB0-CWE diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/board_info.txt b/src/mainboard/clevo/tgl-u/variants/l140mu/board_info.txt new file mode 100644 index 0000000..764bb68 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/board_info.txt @@ -0,0 +1,2 @@ +Board name: L140MU +Release year: 2021 diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/data.vbt b/src/mainboard/clevo/tgl-u/variants/l140mu/data.vbt new file mode 100644 index 0000000..f8c0444 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/data.vbt Binary files differ diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb new file mode 100644 index 0000000..3809754 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb @@ -0,0 +1,249 @@ +chip soc/intel/tigerlake + device cpu_cluster 0 on + register "tcc_offset" = "12" + register "eist_enable" = "true" + device lapic 0 on end + end + device domain 0 on + subsystemid 0x1558 0x14a1 inherit + device ref system_agent on + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 30, + .psys_pmax = 65, + }" + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 30, + .psys_pmax = 65, + }" + register "SaGv" = "SaGv_Enabled" + register "enable_c6dram" = "true" + end + device ref igpu on + register "gfx" = "GMA_DEFAULT_PANEL(0)" + # eDP + register "DdiPortAConfig" = "1" + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "0" + # HDMI + register "DdiPortBConfig" = "0" + register "DdiPortBHpd" = "1" + register "DdiPortBDdc" = "1" + end + device ref dptf on end + device ref tbt_pcie_rp0 on end + device ref tbt_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref north_xhci on + register "UsbTcPortEn" = "true" + register "TcssXhciEn" = "true" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 J_TYPEC1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref south_xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, left (J_USB3_1) + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, right (J_USB3_2) + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C (J_TYPEC1) + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE + register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left (J_USB3_1) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, right (J_USB3_2) + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE + # ACPI + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB3_1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB3_2"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_TYPEC1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 3G/LTE"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB3_1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB3_2"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 3G/LTE"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port4 on end + end + end + end + end + device ref i2c0 on + register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + register "common_soc_config.i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 0x13b, + .scl_hcnt = 0xc8, + .sda_hold = 0x5a, + } + }" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN040D"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.probed" = "true" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device ref i2c1 on # Retimer ROM + register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref cnvi_wifi on + register "CnviBtCore" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref pcie_rp3 on + register "PcieRpEnable[2]" = "true" + register "PcieRpLtrEnable[2]" = "true" + register "PcieClkSrcUsage[1]" = "2" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieRpSlotImplemented[2]" = "true" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + chip drivers/wifi/generic + device pci 00.0 on end + end + end + device ref pcie_rp6 on + # Card reader + device pci 00.0 on end + register "PcieRpEnable[5]" = "true" + register "PcieRpLtrEnable[5]" = "true" + register "PcieClkSrcUsage[2]" = "5" + register "PcieClkSrcClkReq[2]" = "2" + end + device ref pcie_rp9 on + # SSD2 - PCIe mode + register "PcieRpEnable[8]" = "true" + register "PcieRpLtrEnable[8]" = "true" + register "PcieClkSrcUsage[0]" = "8" + register "PcieClkSrcClkReq[0]" = "0" + register "PcieRpSlotImplemented[8]" = "true" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" + chip soc/intel/common/block/pcie/rtd3 + device generic 0 on end + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D9)" + register "srcclk_pin" = "0" + end + end + device ref peg on + # SSD1 - PCIe4 + register "PcieClkSrcUsage[3]" = "0x40" + register "PcieClkSrcClkReq[3]" = "3" + #register "CpuPcieRpLtrEnable[0]" = "true" # currently set in ramstage.c + #register "CpuPcieRpSlotImplemented[0]" = "true" # currently set in ramstage.c + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + chip soc/intel/common/block/pcie/rtd3 + device generic 0 on end + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" + register "srcclk_pin" = "3" + end + end + device ref pch_espi on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref sata on + # SSD2 - SATA mode + register "SataPortsEnable[1]" = "true" + register "SataPortsDevSlp[1]" = "true" + register "SataPortsEnableDitoConfig[1]" = "true" + register "SataSalpSupport" = "true" + end + device ref pmc hidden + register "AcousticNoiseMitigation" = "true" + register "SlowSlewRate" = "SLEW_FAST_4" + register "FastPkgCRampDisable" = "true" + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpAMinAssert" = "4" # 2s + register "PchPmSlpSusMinAssert" = "4" # 4s + register "PchPmPwrCycDur" = "0" # 4-5s + register "s0ix_enable" = "true" + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref hda on + register "PchHdaAudioLinkHdaEnable" = "true" + end + device ref uart2 on + register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" + end + device ref heci1 on end + device ref smbus on end + device ref shared_ram on end + device ref p2sb hidden end + device ref fast_spi on end + end +end diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c b/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c new file mode 100644 index 0000000..6919baf --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c @@ -0,0 +1,235 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpe.h> +#include <soc/gpio.h> +#include <variant/gpio.h> + +/* Name format: <pad name> / <net/pin name in schematics> */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_NC(GPD0, NONE), + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), /* ACPRESENT / AC_PRESENT */ + PAD_NC(GPD2, NONE), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PWRBTN# / PWR_BTN# */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S3# / SUSB#_PCH */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SLP_S4# / SUSC#_PCH */ + PAD_NC(GPD6, NONE), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK / SUS_CLK */ + PAD_NC(GPD9, NONE), + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), /* ESPI_IO0 / ESPI_IO_0 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), /* ESPI_IO1 / ESPI_IO_1 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), /* ESPI_IO2 / ESPI_IO_2 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), /* ESPI_IO3 / ESPI_IO_3 */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* ESPI_CS# / ESPI_CS_N */ + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), /* ESPI_CLK */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* ESPI_RESET# / ESPI_RESET_N */ + PAD_NC(GPP_A7, NONE), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), /* CNV_RF_RESET# / CNVI_RST# */ + PAD_CFG_NF(GPP_A9, UP_20K, DEEP, NF2), /* MODEM_CLKREQ / CNVI_CLKREQ */ + PAD_NC(GPP_A10, NONE), + PAD_NC(GPP_A11, NONE), + PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), /* SATAXPCIE1 / SATAGP1 (wrong name!) */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), /* GPP_A13 / PCH_BT_EN */ + PAD_NC(GPP_A14, NONE), + PAD_NC(GPP_A15, NONE), + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* DDSP_HPDB / HDMI_HPD */ + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_CFG_GPO(GPP_A23, 0, PLTRST), /* GPP_A23 / TC_RETIMER_FORCE_PWR */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 / VCCIN_AUX_VID0 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 / VCCIN_AUX_VID1 */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* VRALERT# */ + PAD_CFG_GPI_APIC_LOW(GPP_B3, NONE, DEEP), /* GPP_B3 (touchpad interrupt) */ + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* GPP_B11 / TBTA_I2C_INT */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLT_RST# */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR / PCH_SPKR */ + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_NC(GPP_B23, NONE), + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK / SMB_CLK_DDR */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA / SMB_DAT_DDR */ + PAD_NC(GPP_C2, NONE), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0CLK */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */ + PAD_NC(GPP_C5, NONE), + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1CLK / TBT_I2C_SCL */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_DATA / TBT_I2C_SDA */ + PAD_NC(GPP_C8, NONE), + PAD_CFG_GPI_APIC_LOW(GPP_C9, NONE, DEEP), /* GPP_C9 / TPM_PIRQ# */ + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_CFG_GPO(GPP_C13, 1, DEEP), /* GPP_C13 / SSD1_PWR_DN# */ + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA / T_SDA (touchpad) */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL / T_SCL (touchpad) */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA / PCH_I2C_SDA (retimer rom) */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCL / PCH_I2C_SCL (retimer rom) */ + PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), /* UART2_TXD */ + PAD_CFG_GPO(GPP_C22, 1, DEEP), /* GPP_C22 / GPP_C12_RTD3 (SSD1) */ + PAD_NC(GPP_C23, UP_20K), /* GPP_C23 / PCH_GPP_C23 (WLAN_WAKEUP#) */ + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), /* GPP_D0 / SB_BLON */ + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), /* LEDKB_DET# (unused; not sold w/o KBLED) */ + PAD_NC(GPP_D3, NONE), /* BOARD_ID (unused; always high) */ + PAD_NC(GPP_D4, NONE), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* SRCCLKREQ0# / SSD1_CLKREQ# (for SSD2!) */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* SRCCLKREQ1# / WLAN_CLKREQ# */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* SRCCLKREQ2# / CARD_CLKREQ# */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* SRCCLKREQ3# / SSD2_CLKREQ# (for SSD1!) */ + PAD_CFG_GPO(GPP_D9, 1, DEEP), /* GPP_D9 / GPP_D13_RTD3 (SSD2) */ + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_CFG_GPO(GPP_D14, 1, DEEP), /* GPP_D14 / SSD2_PWR_DN# */ + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), + PAD_CFG_GPO(GPP_E1, 0, DEEP), /* GPP_E1 / ROM_I2C_EN */ + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), /* SB_KBCRST# (eSPI Virtual Wire) */ + PAD_NC(GPP_E4, NONE), + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1 */ + PAD_NC(GPP_E6, NONE), + PAD_NC(GPP_E7, NONE), + PAD_NC(GPP_E8, NONE), + PAD_NC(GPP_E9, NONE), + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E13, NONE), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDSP_HPDA / EDP_HPD */ + PAD_NC(GPP_E15, NONE), /* SCI# (eSPI Virtual Wire) */ + PAD_NC(GPP_E16, NONE), /* SMI# (eSPI Virtual Wire) */ + PAD_NC(GPP_E17, NONE), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF2), /* TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF2), /* TBT_LSX0_RXD */ + PAD_NC(GPP_E20, NONE), /* SWI# (eSPI Virtual Wire) */ + PAD_NC(GPP_E21, NONE), + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_BRI_DT / CNVI_BRI_DT */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), /* CNV_BRI_RSP / CNVI_BRI_RSP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* CNV_RGI_DT / CNVI_RGI_DT */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), /* CNV_RGI_RSP / CNVI_RGI_RSP */ + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_NC(GPP_F7, NONE), + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_CFG_GPI(GPP_F17, UP_20K, DEEP), /* GPP_F17 / TPM_DET# */ + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_H ------- */ + PAD_NC(GPP_H0, NONE), + PAD_NC(GPP_H1, NONE), + PAD_NC(GPP_H2, NONE), + PAD_NC(GPP_H3, NONE), + PAD_NC(GPP_H4, NONE), + PAD_NC(GPP_H5, NONE), + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), /* DDPB_CTRLCLK / HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDPB_CTRLDATA / HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* CPU_C10_GATE# */ + PAD_NC(GPP_H19, NONE), /* GPP_H19 / CNVI_WAKE# + (UART_WAKE# in M.2 spec; unused) + */ + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), /* HDA_BCLK / HDA_BITCLK */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), /* HDA_SYNC */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), /* HDA_SDO / HDA_SDOUT */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* HDA_SDI0 / HDA_SDIN0 */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), /* HDA_RST# / AZ_RST#_R */ + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_T ------- */ + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), + + /* ------- GPIO Group GPP_U ------- */ + PAD_NC(GPP_U4, NONE), + PAD_NC(GPP_U5, NONE), +}; + +void variant_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/gpio_early.c b/src/mainboard/clevo/tgl-u/variants/l140mu/gpio_early.c new file mode 100644 index 0000000..79da92d --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/gpio_early.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include <variant/gpio.h> + +/* Name format: <pad name> / <net/pin name in schematics> */ +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ +}; + +void variant_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c b/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c new file mode 100644 index 0000000..ebe499d --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x155814a1, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x155814a1), + + /* Microphone (display lid), vendor value: 0x90a60130 */ + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( + INTEGRATED, + LOCATION_OTHER, /* vendor: SEPARATE_CHASSIS */ + SPECIAL7, /* lid, vendor: NA */ + MIC_IN, + OTHER_DIGITAL, + COLOR_UNKNOWN, + 1, /* no presence detect */ + 3, 0) + ), + + /* Integrated speakers, vendor value: 0x90170110 */ + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( + INTEGRATED, + LOCATION_OTHER, /* vendor: SEPARATE_CHASSIS */ + BOTTOM, /* vendor: NA */ + SPEAKER, + OTHER_ANALOG, + COLOR_UNKNOWN, + 1, /* no presence detect */ + 1, 0) + ), + + /* Headphones, vendor value: 0x02211020 */ + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC( + JACK, + EXTERNAL_PRIMARY_CHASSIS, + RIGHT, /* vendor: FRONT */ + HP_OUT, + STEREO_MONO_1_8, + BLACK, + 0, /* has presence detect */ + 2, 0) + ), + + /* ext. Microphone, vendor value: 0x411111f0, linux override: 0x01a1913c */ + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC( + JACK, + EXTERNAL_PRIMARY_CHASSIS, + RIGHT, /* vendor: REAR */ + MIC_IN, + STEREO_MONO_1_8, + BLACK, /* vendor: PINK */ + 1, /* no separate presence detect */ + 3, 12) + ), + + /* PCBEEP, vendor value: 0x41748245 */ + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_DESC( + INTEGRATED, /* vendor: NC */ + INTERNAL, /* vendor: EXTERNAL_PRIMARY_CHASSIS */ + NA, /* vendor: REAR */ + DEVICE_OTHER, /* vendor: MODEM_HANDSET_SIDE */ + OTHER_ANALOG, /* vendor: RCA */ + COLOR_UNKNOWN, /* vendor: PURPLE */ + 1, /* no presence detect, vendor: 2 */ + 4, 5) + ), + + AZALIA_PIN_CFG(0, 0x13, 0x40000000), /* NC, but different from 0x411111f0 */ + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c b/src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c new file mode 100644 index 0000000..6933e99 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> +#include <variant/ramstage.h> + +void variant_configure_fsps(FSP_S_CONFIG *params) +{ + /* SSD1 - PCIe4 */ + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpSlotImplemented[0] = 1; +} diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c b/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c new file mode 100644 index 0000000..14e81fe --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/meminit.h> +#include <variant/romstage.h> + +void variant_configure_fspm(FSPM_UPD *memupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR4, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_MIXED, + .cbfs_index = 0, + .smbus[1] = { .addr_dimm[0] = 0x52, }, + }; + const bool half_populated = false; + + memcfg_init(memupd, &board_cfg, &spd_info, half_populated); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Gerrit-Change-Number: 59548 Gerrit-PatchSet: 20 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/clevo/tgl-u: add new board L14xMU
by Arthur Heymans (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Felix Singer, Nico Huber, Michał Żygowski, Matt DeVillier, Michał Kopeć, Paul Menzel, Subrata Banik, Angel Pons, Michael Niewöhner, Patrick Rudolph, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59548 ) Change subject: mb/clevo/tgl-u: add new board L14xMU ...................................................................... Patch Set 19: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620 Gerrit-Change-Number: 59548 Gerrit-PatchSet: 19 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 01 Apr 2022 12:11:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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