coreboot-gerrit April 2022

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Change in coreboot[master]: mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD device
by Felix Held (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Jon Murphy, Chris Wang, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63295 ) Change subject: mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD device ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: code looks good to me and matches the dxio descriptors. on the commit message i agree with Paul -- To view, visit https://review.coreboot.org/c/coreboot/+/63295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21fb912b69f59717eb4e84c379f706a0257a9ed1 Gerrit-Change-Number: 63295 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 14:47:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/sabrina/makefile: drop multilevel option in amdfwtool calls
by Felix Held (Code Review) 01 Apr '22

01 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63235 ) Change subject: soc/amd/sabrina/makefile: drop multilevel option in amdfwtool calls ...................................................................... soc/amd/sabrina/makefile: drop multilevel option in amdfwtool calls Since Sabrina uses the image slot header (ISH) that depends on the AMD A/B recovery scheme that depends on the multi-level PSP directory support, the multi-level support gets automatically selected by passing Sabrina as SoC name to amdfwtool, so passing the --multilevel command line switch to amdfwtool isn't needed. TEST=Timeless build results in identical binary for chausie Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I98154d5b47daca6ae7952ffd3175d98ea3e01845 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63235 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/soc/amd/sabrina/Makefile.inc 1 file changed, 0 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/sabrina/Makefile.inc b/src/soc/amd/sabrina/Makefile.inc index b504589..b7b538e 100644 --- a/src/soc/amd/sabrina/Makefile.inc +++ b/src/soc/amd/sabrina/Makefile.inc @@ -232,7 +232,6 @@ $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ --location $(shell printf "%#x" $(SABRINA_FWM_POSITION)) \ - --multilevel \ --output $@ $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) @@ -250,7 +249,6 @@ $(OPT_APOB_NV_BASE) \ --location $(shell printf "%#x" $(SABRINA_FW_A_POSITION)) \ --anywhere \ - --multilevel \ --output $@ $(obj)/amdfw_b.rom: $(obj)/amdfw.rom @@ -262,7 +260,6 @@ $(OPT_APOB_NV_BASE) \ --location $(shell printf "%#x" $(SABRINA_FW_B_POSITION)) \ --anywhere \ - --multilevel \ --output $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/63235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98154d5b47daca6ae7952ffd3175d98ea3e01845 Gerrit-Change-Number: 63235 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/i2c/i23c_pad_ctrl: only configure mode and voltage
by Felix Held (Code Review) 01 Apr '22

01 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63234 ) Change subject: soc/amd/common/block/i2c/i23c_pad_ctrl: only configure mode and voltage ...................................................................... soc/amd/common/block/i2c/i23c_pad_ctrl: only configure mode and voltage The fch_i23c_pad_init implementation was written without looking at any reference code and turned out to not work properly on hardware. Before this function writes to the MISC_I23C_PAD_CTRL registers, the value read back is 0x3000003c which results in the I2C bus communication to work while the 0x300003fc the code writes to the register breaks the I2C communication. Removing the code that sets bits 6..9 fixes the I2C bus communication. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Ie6758b3d13c59b20ce810225fca8a365713b7a2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63234 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/i2c/i23c_pad_ctrl.c 1 file changed, 0 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c b/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c index 2439054..bff6223 100644 --- a/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c +++ b/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c @@ -44,12 +44,5 @@ break; } - pad_ctrl &= ~I23C_PAD_CTRL_FALLSLEW_SEL_MASK; - pad_ctrl |= speed == I2C_SPEED_STANDARD ? - I23C_PAD_CTRL_FALLSLEW_SEL_STD : I23C_PAD_CTRL_FALLSLEW_SEL_LOW; - - pad_ctrl &= ~I23C_PAD_CTRL_SLEW_N_MASK; - pad_ctrl |= I23C_PAD_CTRL_SLEW_N_FAST; - misc_write32(MISC_I23C_PAD_CTRL(bus), pad_ctrl); } -- To view, visit https://review.coreboot.org/c/coreboot/+/63234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6758b3d13c59b20ce810225fca8a365713b7a2b Gerrit-Change-Number: 63234 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/sabrina/i2c: handle all I2C pads as I23C pad type
by Felix Held (Code Review) 01 Apr '22

01 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63233 ) Change subject: soc/amd/sabrina/i2c: handle all I2C pads as I23C pad type ...................................................................... soc/amd/sabrina/i2c: handle all I2C pads as I23C pad type Contradicting the PPR #57243 version 1.56, the I2C3 pad control register in the MISC ACPIMMIO region is the same new I23C pad type as the corresponding registers for I2C0..2 and not the older I2C pad control register type used on Picasso and Cezanne. All I2C pads being of the new I23C type is in line with the GPIOMUX settings for the pins used by I2C0..3 that can alternatively connect the pins to an I3C controller. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I51b0ddf8ba2ccfee823e3d4d26a77b11825b1029 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63233 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/sabrina/Kconfig M src/soc/amd/sabrina/i2c.c 2 files changed, 1 insertion(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 66719a6..6924ce4 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -53,7 +53,6 @@ select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_I2C - select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC # TODO: Check if this is still correct diff --git a/src/soc/amd/sabrina/i2c.c b/src/soc/amd/sabrina/i2c.c index 1008f56..e805eff 100644 --- a/src/soc/amd/sabrina/i2c.c +++ b/src/soc/amd/sabrina/i2c.c @@ -39,12 +39,7 @@ if (bus >= ARRAY_SIZE(config->i2c_pad)) return; - /* The I/O pads of I2C0..2 are the new I23C pads and the I/O pads of I2C3 still are the - same I2C pads as in Picasso and Cezanne. */ - if (bus <= 2) - fch_i23c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]); - else - fch_i2c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]); + fch_i23c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]); } const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) -- To view, visit https://review.coreboot.org/c/coreboot/+/63233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51b0ddf8ba2ccfee823e3d4d26a77b11825b1029 Gerrit-Change-Number: 63233 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/sabrina/include/gpio: add I3C3 IOMUX definitions
by Felix Held (Code Review) 01 Apr '22

01 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63232 ) Change subject: soc/amd/sabrina/include/gpio: add I3C3 IOMUX definitions ...................................................................... soc/amd/sabrina/include/gpio: add I3C3 IOMUX definitions According to PPR #57243 version 1.56, the IOMUX setting 2 of the pins 19 and 20 is the I3C3 controller and not the I2C3 controller. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9688f1816aa840c64441495ed451997a474b306f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63232 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/sabrina/include/soc/gpio.h 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/sabrina/include/soc/gpio.h b/src/soc/amd/sabrina/include/soc/gpio.h index fbb19cd..1cd72cd 100644 --- a/src/soc/amd/sabrina/include/soc/gpio.h +++ b/src/soc/amd/sabrina/include/soc/gpio.h @@ -148,11 +148,11 @@ #define GPIO_18_IOMUX_GPIOxx 1 #define GPIO_19_IOMUX_SMBUS1_SCL 0 #define GPIO_19_IOMUX_I2C3_SCL 1 -/* GPIO 19 IOMUX == 2 is also I2C3_SCL */ +#define GPIO_19_IOMUX_I3C3_SCL 2 #define GPIO_19_IOMUX_GPIOxx 3 #define GPIO_20_IOMUX_SMBUS1_SDA 0 #define GPIO_20_IOMUX_I2C3_SDA 1 -/* GPIO 19 IOMUX == 2 is also I2C3_SDA */ +#define GPIO_20_IOMUX_I3C3_SDA 2 #define GPIO_20_IOMUX_GPIOxx 3 #define GPIO_21_IOMUX_ESPI_RESET_L 0 #define GPIO_21_IOMUX_KBRST_L 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9688f1816aa840c64441495ed451997a474b306f Gerrit-Change-Number: 63232 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/i2c/i23c_pad_ctrl: invert and mask
by Felix Held (Code Review) 01 Apr '22

01 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63222 ) Change subject: soc/amd/common/block/i2c/i23c_pad_ctrl: invert and mask ...................................................................... soc/amd/common/block/i2c/i23c_pad_ctrl: invert and mask When masking out bits with an and mask, the bit mask needs to be inverted. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9739d7150e230fbbe6523413de9c07d7340f3c61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63222 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/i2c/i23c_pad_ctrl.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c b/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c index 36211a3..2439054 100644 --- a/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c +++ b/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c @@ -48,7 +48,7 @@ pad_ctrl |= speed == I2C_SPEED_STANDARD ? I23C_PAD_CTRL_FALLSLEW_SEL_STD : I23C_PAD_CTRL_FALLSLEW_SEL_LOW; - pad_ctrl &= I23C_PAD_CTRL_SLEW_N_MASK; + pad_ctrl &= ~I23C_PAD_CTRL_SLEW_N_MASK; pad_ctrl |= I23C_PAD_CTRL_SLEW_N_FAST; misc_write32(MISC_I23C_PAD_CTRL(bus), pad_ctrl); -- To view, visit https://review.coreboot.org/c/coreboot/+/63222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9739d7150e230fbbe6523413de9c07d7340f3c61 Gerrit-Change-Number: 63222 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/i2c/i23c_pad_def.h: fix off by one in define
by Felix Held (Code Review) 01 Apr '22

01 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63216 ) Change subject: soc/amd/common/block/i2c/i23c_pad_def.h: fix off by one in define ...................................................................... soc/amd/common/block/i2c/i23c_pad_def.h: fix off by one in define I23C_PAD_CTRL_SLEW_N_SHIFT is 6 and not 7 which matches both with the PPR #57243 revision 1.53 and with I23C_PAD_CTRL_SLEW_N_MASK which covers both bits 6 and 7. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I622717bebaffe34b6df5e578b082dc10e2a98256 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63216 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/i2c/i23c_pad_def.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/i2c/i23c_pad_def.h b/src/soc/amd/common/block/i2c/i23c_pad_def.h index 8973a0c..ae7f3d6 100644 --- a/src/soc/amd/common/block/i2c/i23c_pad_def.h +++ b/src/soc/amd/common/block/i2c/i23c_pad_def.h @@ -17,7 +17,7 @@ #define I23C_PAD_CTRL_RX_SEL_OFF (0 << I23C_PAD_CTRL_RX_SHIFT) #define I23C_PAD_CTRL_RX_SEL_ON (3 << I23C_PAD_CTRL_RX_SHIFT) #define I23C_PAD_CTRL_SLEW_N_MASK (BIT(6) | BIT(7)) -#define I23C_PAD_CTRL_SLEW_N_SHIFT 7 +#define I23C_PAD_CTRL_SLEW_N_SHIFT 6 #define I23C_PAD_CTRL_SLEW_N_DIS (0 << I23C_PAD_CTRL_SLEW_N_SHIFT) #define I23C_PAD_CTRL_SLEW_N_FAST (3 << I23C_PAD_CTRL_SLEW_N_SHIFT) #define I23C_PAD_CTRL_FALLSLEW_SEL_MASK (BIT(8) | BIT(9)) -- To view, visit https://review.coreboot.org/c/coreboot/+/63216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I622717bebaffe34b6df5e578b082dc10e2a98256 Gerrit-Change-Number: 63216 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/skyrim: Fix ESPI communication issues
by Raul Rangel (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63286 ) Change subject: mb/google/skyrim: Fix ESPI communication issues ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I951afdada8ee4f917cdeba8e287e5a2ae77c97ee Gerrit-Change-Number: 63286 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 01 Apr 2022 14:30:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Allow retrieving FSP timestamp information
by Tim Wawrzynczak (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62943 ) Change subject: soc/intel/alderlake: Allow retrieving FSP timestamp information ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/62943/comment/f017b9a7_9417b24b PS5, Line 39: DISPLAY_FSP_TIMESTAMPS I kinda think this should be mainboard specific, as not necessarily all users of an SoC will have this PCD enabled -- To view, visit https://review.coreboot.org/c/coreboot/+/62943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I568f18c6bc4f54e87f8763a331796f4a72d4c976 Gerrit-Change-Number: 62943 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 14:26:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/tcss: Check conn device enabled in tcss_get_port_info
by Tim Wawrzynczak (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Maulik V Vaghela, Reka Norman, Rizwan Qureshi. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63237 ) Change subject: soc/intel/common/tcss: Check conn device enabled in tcss_get_port_info ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > So basically you want to switch from finding the conn devices using their path to finding them based […] That's it, thanks! 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/63237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I487f3ca4be4ead0c5dfb46e9eb19de5ae9b9bda9 Gerrit-Change-Number: 63237 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 14:20:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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