coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

Change in coreboot[master]: mb/intel/adlrvp: Set half_populated true for ADL-N
by Usha P (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: V Sowmya, Paul Menzel, Rizwan Qureshi, Balaji Manigandan, Krishna P Bhat D. Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62913 ) Change subject: mb/intel/adlrvp: Set half_populated true for ADL-N ...................................................................... Patch Set 5: (2 comments) File src/mainboard/intel/adlrvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/62913/comment/3ba0b174_86475fbe PS4, Line 51: #if CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N) > Please use C instead of CPP statements. Ack https://review.coreboot.org/c/coreboot/+/62913/comment/895caf34_924aec39 PS4, Line 51: #if CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N) : const bool half_populated = true; : #else : const bool half_populated = false; : #endif > Ternary operator can also be used. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/62913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ecc3018a1ab039990ba47898ff0e0e2ede695cc Gerrit-Change-Number: 62913 Gerrit-PatchSet: 5 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kangheui Won <khwon(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 09:59:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/intel/adlrvp: Set half_populated true for ADL-N
by Usha P (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: V Sowmya, Rizwan Qureshi, Balaji Manigandan, Krishna P Bhat D, Usha P. Hello V Sowmya, build bot (Jenkins), Reka Norman, Rizwan Qureshi, Balaji Manigandan, Krishna P Bhat D, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62913 to look at the new patch set (#5). Change subject: mb/intel/adlrvp: Set half_populated true for ADL-N ...................................................................... mb/intel/adlrvp: Set half_populated true for ADL-N Alder Lake N has single memory controller with 64-bit bus width. Alder Lake common meminit block driver considers bus width to be 128-bit and populates the meminit data accordingly. By setting half_populated to true, only the bottom half is populated. Ideally, half_populated is used in platforms with multiple channels to enable only one half of the channel. Alder Lake N has single channel, and it would require for new structures to be defined in meminit block driver for LPx memory configurations. In order to avoid adding new structures, set half_populated to true. This has the same effect as having single channel with 64-bit width. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I2ecc3018a1ab039990ba47898ff0e0e2ede695cc --- M src/mainboard/intel/adlrvp/romstage_fsp_params.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/62913/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ecc3018a1ab039990ba47898ff0e0e2ede695cc Gerrit-Change-Number: 62913 Gerrit-PatchSet: 5 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kangheui Won <khwon(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/mediatek: Fill coreboot table with PCIe info
by Yu-Ping Wu (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Hung-Te Lin, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63252 ) Change subject: soc/mediatek: Fill coreboot table with PCIe info ...................................................................... Patch Set 6: Code-Review+2 (1 comment) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/63252/comment/f369ea9c_2763c7b4 PS6, Line 216: pci_root_bus > This will be NULL when the PCIe domain not defined in device tree. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406 Gerrit-Change-Number: 63252 Gerrit-PatchSet: 6 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 09:48:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table
by Yu-Ping Wu (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot tables: Add PCIe info to coreboot table ...................................................................... Patch Set 5: (1 comment) File payloads/libpayload/include/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/0057924b_9a0cd295 PS4, Line 276: config_base > I'm not sure if I understand correctly, maybe we can remove config_base? TBH I'm not that familiar with PCIe, so I'm also not sure if your ctrl_base is the same as qualcomm's config_base. Could you take a look at qualcomm's CL [1]? Are you able to tell if these 2 fields mean the same thing? [1] https://review.coreboot.org/c/coreboot/+/57615/42/payloads/libpayload/drive… -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 5 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 09:46:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Fill coreboot table with PCIe info
by Jianjun Wang (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63252 ) Change subject: soc/mediatek: Fill coreboot table with PCIe info ...................................................................... Patch Set 6: (1 comment) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/63252/comment/b6e6a3be_e99ebec0 PS6, Line 216: pci_root_bus > Will this be NULL on devices without NVMe? This will be NULL when the PCIe domain not defined in device tree. -- To view, visit https://review.coreboot.org/c/coreboot/+/63252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406 Gerrit-Change-Number: 63252 Gerrit-PatchSet: 6 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 09:40:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table
by Jianjun Wang (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot tables: Add PCIe info to coreboot table ...................................................................... Patch Set 5: (1 comment) File payloads/libpayload/include/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/5f0b9454_510beef8 PS4, Line 276: config_base > I thought this is the same as `ctrl_base`, but it's not? I'm not sure if I understand correctly, maybe we can remove config_base? -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 5 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 09:39:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: libpayload/pci: Add PCIe interfaces for MediaTek platform
by Yu-Ping Wu (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Angel Pons, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56794 ) Change subject: libpayload/pci: Add PCIe interfaces for MediaTek platform ...................................................................... Patch Set 51: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 Gerrit-Change-Number: 56794 Gerrit-PatchSet: 51 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 09:38:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Fill coreboot table with PCIe info
by Yu-Ping Wu (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Hung-Te Lin, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63252 ) Change subject: soc/mediatek: Fill coreboot table with PCIe info ...................................................................... Patch Set 6: Code-Review+1 (1 comment) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/63252/comment/3f690cff_c881cb16 PS6, Line 216: pci_root_bus Will this be NULL on devices without NVMe? -- To view, visit https://review.coreboot.org/c/coreboot/+/63252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406 Gerrit-Change-Number: 63252 Gerrit-PatchSet: 6 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 09:37:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: Update CSE sub partition update
by Sridhar Siricilla (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Paul Menzel, Kane Chen. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Kane Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63169 to look at the new patch set (#5). Change subject: soc/intel/common: Update CSE sub partition update ...................................................................... soc/intel/common: Update CSE sub partition update The patch adds support in the CSE Sub partition update procedure to use GET_BOOT_PARTITION_INFO HECI command output to create the region device for CSE RO and CSE RW. The GET_BOOT_PARTITION_INFO HECI command provides CSE's RO and RW boot partition information. Existing code relies on FMD file to get the CSE's boot partition's (CSE RO and CSE RW) start and size details. This change make independent of FMD file declaration with respect to CSE RO and CSE RW. TEST=Build and verify the CSE RO and CSE RW region device information through code instrumentation. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 34 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63169/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629 Gerrit-Change-Number: 63169 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: libpayload/pci: Add support for bus mapping
by Yu-Ping Wu (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Angel Pons, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 ) Change subject: libpayload/pci: Add support for bus mapping ...................................................................... Patch Set 50: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 50 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 09:35:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2022