coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/brya: Disable PCH USB2 phy power gating
by Sridhar Siricilla (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Subrata Banik, Paul Menzel, Tim Wawrzynczak. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63294 ) Change subject: mb/google/brya: Disable PCH USB2 phy power gating ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63294/comment/904a60db_70b7024d PS1, Line 9: The patch disables PCH USB2 Phy power gating. > Please add a motivation. For example: […] Added the motivation details. -- To view, visit https://review.coreboot.org/c/coreboot/+/63294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb Gerrit-Change-Number: 63294 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Apr 2022 06:37:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
by Sridhar Siricilla (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Subrata Banik, Paul Menzel, Tim Wawrzynczak, Kane Chen. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 ) Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating ...................................................................... Patch Set 2: (3 comments) Patchset: PS2: > I believe we need to default disable USB2 PHY power gating for all ADL-P devices irrespective of int […] @subrata, as per Intel doc#723158, when extern VR is used, then reported issue may not occur. So, I expect developer should enable the UPD if USB2 phy power gating to be disabled. File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/63293/comment/585baf45_1b453fdb PS2, Line 572: orderto > order to Ack https://review.coreboot.org/c/coreboot/+/63293/comment/de69f197_f38775c7 PS2, Line 572: > One space. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d Gerrit-Change-Number: 63293 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 06:37:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Disable PCH USB2 phy power gating
by Sridhar Siricilla (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63294 to look at the new patch set (#3). Change subject: mb/google/brya: Disable PCH USB2 phy power gating ...................................................................... mb/google/brya: Disable PCH USB2 phy power gating The patch disables PCH USB2 Phy power gating. This change is required to prevent possible display flicker issue. Please refer Intel doc#723158 for more information. BUG=b:221461379 TEST=Build and boot Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb --- M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/63294/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb Gerrit-Change-Number: 63294 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
by Sridhar Siricilla (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Kane Chen. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Kane Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63293 to look at the new patch set (#3). Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating ...................................................................... soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating The patch adds mechanism in the Alder Lake SoC code to control PCH USB2 Phy power gating from devicetree. Please refer Intel doc#723158 for more informatrion. BUG=b:221461379 TEST=Build and boot Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63293/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d Gerrit-Change-Number: 63293 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: Use command line option use-combo to decide if use combo
by build bot (Jenkins) (Code Review) 01 Apr '22

01 Apr '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55455 ) Change subject: amdfwtool: Use command line option use-combo to decide if use combo ...................................................................... Patch Set 25: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426 Gerrit-Change-Number: 55455 Gerrit-PatchSet: 25 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 01 Apr 2022 06:34:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/pci: Add PCIe interfaces for MediaTek platform
by Jianjun Wang (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Angel Pons, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56794 ) Change subject: libpayload/pci: Add PCIe interfaces for MediaTek platform ...................................................................... Patch Set 49: (6 comments) File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/56794/comment/6cad1b74_5a3971aa PS48, Line 417: Support > Support for Done https://review.coreboot.org/c/coreboot/+/56794/comment/91e9aa7c_07e94457 PS48, Line 417: platform > platforms Done File payloads/libpayload/drivers/pcie_mediatek.c: https://review.coreboot.org/c/coreboot/+/56794/comment/5329f1bc_8983e127 PS48, Line 19: devfn > u32 devfn Done https://review.coreboot.org/c/coreboot/+/56794/comment/2763f920_02163eec PS48, Line 20: > Remove blank line. Done https://review.coreboot.org/c/coreboot/+/56794/comment/698f50b8_8509e29f PS48, Line 21: val > u32 val Done https://review.coreboot.org/c/coreboot/+/56794/comment/f5121033_d68e0bd4 PS48, Line 22: > Remove blank line. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 Gerrit-Change-Number: 56794 Gerrit-PatchSet: 49 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 06:31:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/pci: Add support for bus mapping
by Jianjun Wang (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Angel Pons, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 ) Change subject: libpayload/pci: Add support for bus mapping ...................................................................... Patch Set 48: (2 comments) File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/56789/comment/3a9f1a9e_cd89b9ba PS47, Line 406: bool "Support for PCI devices" > No need to change the description. Done https://review.coreboot.org/c/coreboot/+/56789/comment/6447549c_57a4f34f PS47, Line 411: on x86 platform > with port IO Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 48 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 06:30:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Fill coreboot table with PCIe info
by Jianjun Wang (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63252 ) Change subject: soc/mediatek: Fill coreboot table with PCIe info ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63252/comment/cb1b88be_827ab1bc PS3, Line 9: F > In order to pass PCIe base address to payloads, implement pcie_fill_lb() to fill coreboot ... Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406 Gerrit-Change-Number: 63252 Gerrit-PatchSet: 4 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 06:30:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table
by Jianjun Wang (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot tables: Add PCIe info to coreboot table ...................................................................... Patch Set 4: (5 comments) File payloads/libpayload/include/sysinfo.h: https://review.coreboot.org/c/coreboot/+/63251/comment/2a2eac0b_d1fc031c PS2, Line 87: uintptr_t pcie_ctrl_base; /* PCIe controller base address */ > Can we use a struct here, because qualcomm will need to store 3 fields: config_base, config_size and […] Done File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/c54020da_26cd963b PS3, Line 95: LB_TAG_PCIE = 0x00cd, > Move this to line 89. Done File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/c30d268d_e6a3a129 PS2, Line 173: reg_base > "config_base", or "conf_base", or "mmconf_base". […] Done, I also keep the ctrl_base since our driver need its controller base address. https://review.coreboot.org/c/coreboot/+/63251/comment/f57dc906_d19d14c7 PS2, Line 173: uintptr_t > uint64_t Done File src/include/boot/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/8919e11b_75ab727e PS2, Line 24: pcie > pci or pcie? Same for other names. I think pcie is sufficient, new device may not support pci device anymore. -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 4 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 06:30:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/pci: Add PCIe interfaces for MediaTek platform
by Jianjun Wang (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Angel Pons, Jianjun Wang. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56794 to look at the new patch set (#49). Change subject: libpayload/pci: Add PCIe interfaces for MediaTek platform ...................................................................... libpayload/pci: Add PCIe interfaces for MediaTek platform Add PCIe configuration interfaces for MediaTek platform. The register base address of PCIe hardware might be different when it's a non-x86 platform, add 'pci_update_hw_base()' interface for users to update its base address to access PCIe hardware correctly. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 --- M payloads/libpayload/Kconfig M payloads/libpayload/drivers/Makefile.inc A payloads/libpayload/drivers/pcie_mediatek.c 3 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/56794/49 -- To view, visit https://review.coreboot.org/c/coreboot/+/56794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 Gerrit-Change-Number: 56794 Gerrit-PatchSet: 49 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2022