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Change subject: amdfwtool: Add more detailed description and note in comment
......................................................................
Patch Set 11: Verified+1
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Change subject: amdfwtool: Change the name of macros for 'BHD'
......................................................................
Patch Set 25:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55411/comment/c18a0895_d2f7e4a6
PS25, Line 9: BHD
… instead of BDT
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Change subject: mb/google/brya: Disable PCH USB2 phy power gating
......................................................................
mb/google/brya: Disable PCH USB2 phy power gating
The patch disables PCH USB2 Phy power gating.
BUG=b:221461379
TEST=Build and boot Gimble board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb
---
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)
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Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
......................................................................
soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
The patch adds mechanism in the Alder Lake SoC code to control PCH
USB2 Phy power gating from devicetree.
BUG=b:221461379
TEST=Build and boot Gimble board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63293/2
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Change subject: amdfwtool: Use command line option use-combo to decide if use combo
......................................................................
Patch Set 24: Verified+1
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Change subject: amdfwtool: Change the name of macros for 'BHD'
......................................................................
Patch Set 25: Verified+1
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Change subject: amdfwtool: Fix some blanks
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58320/comment/d411e7dd_3e9672e5
PS5, Line 7: amdfwtool: Fix some blanks
Fix indentation and remove blank line
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/qualcomm/common: Add strict flag to clock_configure()
......................................................................
soc/qualcomm/common: Add strict flag to clock_configure()
When strict parameter is set to true, clock_configure() will try to
find an exact match to the clock frequency given. If exact match
cannot be found, then will throw an assertion error.
BUG=b:198627043
BRANCH=None
TEST=build herobrine image and try to set SPI frequency to number not
supported. Ensure device doesn't boot.
Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/soc/qualcomm/common/clock.c
M src/soc/qualcomm/common/include/soc/clock_common.h
M src/soc/qualcomm/sc7180/clock.c
M src/soc/qualcomm/sc7280/clock.c
4 files changed, 30 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/63289/4
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Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63279 )
Change subject: crossgcc: Upgrade IASL from 20211217 to 20220331
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63279/comment/140a7d43_6be94a52
PS2, Line 7: crossgcc: Upgrade IASL to 20220331 version
> Maybe: […]
Done
Patchset:
PS3:
Thx
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