Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table
Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot tables: Add PCIe info to coreboot table ...................................................................... Patch Set 4: (5 comments) File payloads/libpayload/include/sysinfo.h: https://review.coreboot.org/c/coreboot/+/63251/comment/2a2eac0b_d1fc031c PS2, Line 87: uintptr_t pcie_ctrl_base; /* PCIe controller base address */
Can we use a struct here, because qualcomm will need to store 3 fields: config_base, config_size and […] Done
File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/c54020da_26cd963b PS3, Line 95: LB_TAG_PCIE = 0x00cd,
Move this to line 89. Done
File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/c30d268d_e6a3a129 PS2, Line 173: reg_base
"config_base", or "conf_base", or "mmconf_base". […] Done, I also keep the ctrl_base since our driver need its controller base address.
https://review.coreboot.org/c/coreboot/+/63251/comment/f57dc906_d19d14c7 PS2, Line 173: uintptr_t
uint64_t Done
File src/include/boot/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/8919e11b_75ab727e PS2, Line 24: pcie
pci or pcie? Same for other names. I think pcie is sufficient, new device may not support pci device anymore.
-- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 4 Gerrit-Owner: Jianjun Wang <jianjun.wang@mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte@chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen@mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso@google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Julius Werner <jwerner@chromium.org> Gerrit-Attention: Hung-Te Lin <hungte@chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen@mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso@google.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 06:30:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso@google.com> Gerrit-MessageType: comment
participants (1)
-
Jianjun Wang (Code Review)