coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table
by Jianjun Wang (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot tables: Add PCIe info to coreboot table ...................................................................... Patch Set 5: (1 comment) File payloads/libpayload/include/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/8f0fcca6_fe4be9ab PS4, Line 276: config_base > TBH I'm not that familiar with PCIe, so I'm also not sure if your ctrl_base is the same as qualcomm' […] It seems that config_base and ctrl_base are not the same thing, config_base is more like the register address to access the PCIe device's configuration space, but the ctrl_base is the register address for the PCIe hardware module. -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 5 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 11:55:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data
by Michael Niewöhner (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro, Andrey Petrov. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62942 ) Change subject: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data ...................................................................... Patch Set 7: Code-Review+2 (1 comment) File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/62942/comment/eaf4b80b_00ab2297 PS7, Line 248: if (CONFIG(DISPLAY_FSP_TIMESTAMPS)) : fsp_display_timestamp(); : > > Ok, then let's keep it after whole silicon init. […] Great, thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/62942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3 Gerrit-Change-Number: 62942 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 11:17:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data
by Subrata Banik (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro, Michael Niewöhner, Andrey Petrov. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62942 ) Change subject: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data ...................................................................... Patch Set 7: (1 comment) File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/62942/comment/ed5fb974_70b99f19 PS7, Line 248: if (CONFIG(DISPLAY_FSP_TIMESTAMPS)) : fsp_display_timestamp(); : > Ok, then let's keep it after whole silicon init. Is multi-phase init surely finished after do_silicon_init, or does it continue asynchronously? yes, when you see "FspSiliconInitApi() - [Status: 0x00000000] - End" prints, both FSP_S and MultiPhaseSiInit are done. -- To view, visit https://review.coreboot.org/c/coreboot/+/62942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3 Gerrit-Change-Number: 62942 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 10:46:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] ChromeOS: Move watchdog_tombstone and TPM reset triggers
by Kyösti Mälkki (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Hung-Te Lin. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50879 ) Change subject: [WIP] ChromeOS: Move watchdog_tombstone and TPM reset triggers ...................................................................... Patch Set 9: (1 comment) Patchset: PS8: > > no changes for almost a week, probably abandon this? […] Why abandon it when something should be done, and no respective bug is filed with as good commentary as Julius provided above? -- To view, visit https://review.coreboot.org/c/coreboot/+/50879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40b72cd63b051a2649ff450f50946e5a0a00ed4f Gerrit-Change-Number: 50879 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Apr 2022 10:45:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ELOG: Refactor watchdog_tombstone
by Kyösti Mälkki (Code Review) 01 Apr '22

01 Apr '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63300 ) Change subject: ELOG: Refactor watchdog_tombstone ...................................................................... ELOG: Refactor watchdog_tombstone The symbol watchdog_tombstone is not really about ChromeOS but ELOG instead. This prepares for furher move of the watchdog_tombstone implementation. Change-Id: I8446fa1a395b2d17912a23b87b83277c80828874 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/symbols.h M src/vendorcode/google/chromeos/chromeos.h D src/vendorcode/google/chromeos/symbols.h M src/vendorcode/google/chromeos/watchdog.c 4 files changed, 13 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/63300/1 diff --git a/src/include/symbols.h b/src/include/symbols.h index 3e4694b..ee7c503 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -76,6 +76,7 @@ DECLARE_OPTIONAL_REGION(opensbi) DECLARE_OPTIONAL_REGION(bl31) DECLARE_REGION(transfer_buffer) +DECLARE_OPTIONAL_REGION(watchdog_tombstone) /* Returns true when pre-RAM symbols are known to the linker. * (Does not necessarily mean that the memory is accessible.) */ diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index abdd6c2..8efcc20 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -11,6 +11,7 @@ /* functions implemented in watchdog.c */ void mark_watchdog_tombstone(void); void reboot_from_watchdog(void); +bool reset_watchdog_tombstone(void); #else static inline void mark_watchdog_tombstone(void) { return; } static inline void reboot_from_watchdog(void) { return; } diff --git a/src/vendorcode/google/chromeos/symbols.h b/src/vendorcode/google/chromeos/symbols.h deleted file mode 100644 index 45f9c3e..0000000 --- a/src/vendorcode/google/chromeos/symbols.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __CHROMEOS_SYMBOLS_H -#define __CHROMEOS_SYMBOLS_H - -#include <symbols.h> - -DECLARE_OPTIONAL_REGION(watchdog_tombstone) - -#endif /* __CHROMEOS_SYMBOLS_H */ diff --git a/src/vendorcode/google/chromeos/watchdog.c b/src/vendorcode/google/chromeos/watchdog.c index d3273cb..0aa1762 100644 --- a/src/vendorcode/google/chromeos/watchdog.c +++ b/src/vendorcode/google/chromeos/watchdog.c @@ -10,7 +10,6 @@ #include <symbols.h> #include "chromeos.h" -#include "symbols.h" #define WATCHDOG_TOMBSTONE_MAGIC 0x9d2f41a7 @@ -21,11 +20,7 @@ if (CONFIG(CHROMEOS_USE_EC_WATCHDOG_FLAG)) flag |= google_chromeec_get_ap_watchdog_flag(); - if (REGION_SIZE(watchdog_tombstone)) { - flag |= (read32(_watchdog_tombstone) == - WATCHDOG_TOMBSTONE_MAGIC); - write32(_watchdog_tombstone, 0); - } + flag |= reset_watchdog_tombstone(); if (flag) elog_add_event(ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED); @@ -34,6 +29,16 @@ BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, elog_handle_watchdog_tombstone, NULL); +bool reset_watchdog_tombstone(void) +{ + if (!REGION_SIZE(watchdog_tombstone)) + return false; + + bool flag = (read32(_watchdog_tombstone) == WATCHDOG_TOMBSTONE_MAGIC); + write32(_watchdog_tombstone, 0); + return flag; +} + void mark_watchdog_tombstone(void) { assert(REGION_SIZE(watchdog_tombstone)); -- To view, visit https://review.coreboot.org/c/coreboot/+/63300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8446fa1a395b2d17912a23b87b83277c80828874 Gerrit-Change-Number: 63300 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] ChromeOS: Move watchdog_tombstone and TPM reset triggers
by Kyösti Mälkki (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Kyösti Mälkki. Hello build bot (Jenkins), Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50879 to look at the new patch set (#9). Change subject: [WIP] ChromeOS: Move watchdog_tombstone and TPM reset triggers ...................................................................... [WIP] ChromeOS: Move watchdog_tombstone and TPM reset triggers Change-Id: I40b72cd63b051a2649ff450f50946e5a0a00ed4f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/elog/elog.c R src/lib/watchdog.c M src/mainboard/google/gru/bootblock.c M src/mainboard/google/nyan_blaze/romstage.c M src/mainboard/google/veyron/bootblock.c M src/mainboard/google/veyron_mickey/bootblock.c M src/mainboard/google/veyron_rialto/bootblock.c M src/soc/mediatek/common/wdt.c M src/soc/nvidia/tegra124/bootblock.c M src/soc/nvidia/tegra210/romstage.c M src/soc/qualcomm/sc7180/watchdog.c M src/vendorcode/google/chromeos/Makefile.inc M src/vendorcode/google/chromeos/chromeos.h 13 files changed, 22 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/50879/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/50879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40b72cd63b051a2649ff450f50946e5a0a00ed4f Gerrit-Change-Number: 50879 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data
by Michael Niewöhner (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro, Andrey Petrov. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62942 ) Change subject: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data ...................................................................... Patch Set 7: (1 comment) File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/62942/comment/4eb795f3_02e8ccce PS7, Line 248: if (CONFIG(DISPLAY_FSP_TIMESTAMPS)) : fsp_display_timestamp(); : > > I wonder if that call might fit better in debug.c:fsp_debug_after_silicon_init(). […] Ok, then let's keep it after whole silicon init. Is multi-phase init surely finished after do_silicon_init, or does it continue asynchronously? -- To view, visit https://review.coreboot.org/c/coreboot/+/62942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3 Gerrit-Change-Number: 62942 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 10:37:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Update CPU IDs with correct steppings
by Subrata Banik (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Meera Ravindranath, Lean Sheng Tan. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63299 ) Change subject: soc/intel/alderlake: Update CPU IDs with correct steppings ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Can I request you to split this into 2 CL 1. Add relevant stepping macro and text 2. Add new ID for L0. -- To view, visit https://review.coreboot.org/c/coreboot/+/63299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I722043c493b8c3de8965bcaa13f33c907d51f284 Gerrit-Change-Number: 63299 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 10:27:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Set half_populated true for ADL-N
by build bot (Jenkins) (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: V Sowmya, Paul Menzel, Rizwan Qureshi, Balaji Manigandan, Krishna P Bhat D. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62913 ) Change subject: mb/intel/adlrvp: Set half_populated true for ADL-N ...................................................................... Patch Set 6: (2 comments) File src/mainboard/intel/adlrvp/romstage_fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145244): https://review.coreboot.org/c/coreboot/+/62913/comment/2c6df2b2_42a90ddd PS6, Line 51: /* AlderLake common meminit block driver considers bus width to be 128-bit and populates trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145244): https://review.coreboot.org/c/coreboot/+/62913/comment/2ca0816d_0092f2b3 PS6, Line 53: * width. By setting half_populated to true, only the bottom half is populated. trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/62913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ecc3018a1ab039990ba47898ff0e0e2ede695cc Gerrit-Change-Number: 62913 Gerrit-PatchSet: 6 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kangheui Won <khwon(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 10:20:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Update CPU IDs with correct steppings
by Lean Sheng Tan (Code Review) 01 Apr '22

01 Apr '22

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63299 ) Change subject: soc/intel/alderlake: Update CPU IDs with correct steppings ...................................................................... soc/intel/alderlake: Update CPU IDs with correct steppings Update ADL CPU IDs per correct steppings and add new CPU ID 0x906A3 (L0 stepping). Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I722043c493b8c3de8965bcaa13f33c907d51f284 --- M src/include/cpu/intel/cpu_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c 3 files changed, 15 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/63299/1 diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 07e359a..6d36851 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -51,10 +51,11 @@ #define CPUID_ELKHARTLAKE_A0 0x90660 #define CPUID_ELKHARTLAKE_B0 0x90661 #define CPUID_ALDERLAKE_S_A0 0x90670 -#define CPUID_ALDERLAKE_A0 0x906a0 -#define CPUID_ALDERLAKE_A1 0x906a1 -#define CPUID_ALDERLAKE_A2 0x906a2 -#define CPUID_ALDERLAKE_A3 0x906a4 +#define CPUID_ALDERLAKE_J0 0x906a0 +#define CPUID_ALDERLAKE_Q0 0x906a1 +#define CPUID_ALDERLAKE_K0 0x906a2 +#define CPUID_ALDERLAKE_L0 0x906a3 +#define CPUID_ALDERLAKE_R0 0x906a4 #define CPUID_ALDERLAKE_N_A0 0xb06e0 #define CPUID_METEORLAKE_A0_1 0xa06a0 #define CPUID_METEORLAKE_A0_2 0xa06a1 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 3342e4b..bdce2b7 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -23,10 +23,11 @@ u32 cpuid; const char *name; } cpu_table[] = { - { CPUID_ALDERLAKE_A0, "Alderlake Platform" }, - { CPUID_ALDERLAKE_A1, "Alderlake Platform" }, - { CPUID_ALDERLAKE_A2, "Alderlake Platform" }, - { CPUID_ALDERLAKE_A3, "Alderlake Platform" }, + { CPUID_ALDERLAKE_J0, "Alderlake J0 Platform" }, + { CPUID_ALDERLAKE_K0, "Alderlake K0 Platform" }, + { CPUID_ALDERLAKE_L0, "Alderlake L0 Platform" }, + { CPUID_ALDERLAKE_Q0, "Alderlake Q0 Platform" }, + { CPUID_ALDERLAKE_R0, "Alderlake R0 Platform" }, { CPUID_ALDERLAKE_N_A0, "Alderlake-N Platform" }, }; diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 2d838c5..823f23e 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -70,10 +70,11 @@ { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_B0 }, { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_S_A0 }, - { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A0 }, - { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A1 }, - { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A2 }, - { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A3 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_J0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_K0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_L0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_Q0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_R0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0 }, { 0, 0 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/63299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I722043c493b8c3de8965bcaa13f33c907d51f284 Gerrit-Change-Number: 63299 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2022