coreboot-gerrit April 2022

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Change in coreboot[master]: mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ix
by 9elements QA (Code Review) 01 Apr '22

01 Apr '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63191 ) Change subject: mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ix ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 13 / 1 / 14 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/98790 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/98789 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/98788 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/98787 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/98786 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/98785 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/98784 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/98783 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/98782 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/98781 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/98780 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/98779 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/98778 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/98777 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/63191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69588c82dfde1744c45c7aff3ac05b80bb16a8f3 Gerrit-Change-Number: 63191 Gerrit-PatchSet: 4 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 01 Apr 2022 16:14:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add HID for DPTF Power Participant
by 9elements QA (Code Review) 01 Apr '22

01 Apr '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63202 ) Change subject: soc/intel/alderlake: Add HID for DPTF Power Participant ...................................................................... Patch Set 6: Automatic boot test returned (PASS/FAIL/TOTAL): 13 / 1 / 14 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/98775 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/98774 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/98773 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/98772 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/98771 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/98770 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/98769 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/98768 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/98767 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/98766 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/98765 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/98764 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/98763 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/98762 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/63202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82507a3c0a521adbb8dec5520fd6d2ea3782c60e Gerrit-Change-Number: 63202 Gerrit-PatchSet: 6 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 01 Apr 2022 16:00:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device/i2c_bus: Add detect function pointer in i2c_bus_ops
by Tim Wawrzynczak (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Subrata Banik, Matt DeVillier, Julius Werner, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63209 ) Change subject: device/i2c_bus: Add detect function pointer in i2c_bus_ops ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > regardless if a new function is used, the new pointer in the ops struct is still needed, no? For at least the DW i2c driver, a 0-byte transfer just immediately returns -1, https://review.coreboot.org/c/coreboot/+/63210/2/src/drivers/i2c/designware…, and the transfer function would need a few tweaks.... but maybe that can be accommodated, let me hack something up. Matt, then the i2c/generic driver code wouldn't call detect(), it would call transfer() but passing 0 for the size, it's not quite as descriptive that way, but I think that's what Julius means. -- To view, visit https://review.coreboot.org/c/coreboot/+/63209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8ddfb187eabec966c253b6cc8526491c99151fc Gerrit-Change-Number: 63209 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 15:38:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: tpm: Accept Google Ti50 TPM DID:VID
by Jett Rink (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Jes Klinke, Tim Wawrzynczak, Christian Walter. Jett Rink has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63158 ) Change subject: tpm: Accept Google Ti50 TPM DID:VID ...................................................................... Patch Set 11: (3 comments) File src/drivers/spi/tpm/tpm.c: https://review.coreboot.org/c/coreboot/+/63158/comment/8c7a8a4a_245e57b6 PS11, Line 422: H1D3 nit: H1D3C File src/drivers/tpm/cr50.c: https://review.coreboot.org/c/coreboot/+/63158/comment/8fc1aeb0_c5b1828e PS11, Line 109: if (!CONFIG(TPM_CR50)) : return 0; let's add a comment to why we are skipping here (e.g. // if we get here and we aren't cr50, then we must be ti50 which does not currentlt need to support board_cfg register read) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/63158/comment/408d3b75_376f1565 PS11, Line 58: BOARD_GOOGLE_BASEBOARD_NISSA shouldn't we add `MAINBOARD_HAS_I2C_TPM_TI50` to this list if we are removing the workaround? -- To view, visit https://review.coreboot.org/c/coreboot/+/63158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Gerrit-Change-Number: 63158 Gerrit-PatchSet: 11 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jett Rink <jettrink(a)chromium.org> Gerrit-CC: Jett Rink <jettrink(a)google.com> Gerrit-Attention: Jes Klinke <jbk(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 15:17:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/octopus: Implement touchscreen, digitizer power sequencing
by Matt DeVillier (Code Review) 01 Apr '22

01 Apr '22

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Change in coreboot[master]: mb/google/octopus: Implement touchscreen, digitizer power sequencing
by Matt DeVillier (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Raul Rangel, Paul Menzel, Tim Wawrzynczak, Karthik Ramasubramanian. Hello build bot (Jenkins), Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63212 to look at the new patch set (#3). Change subject: mb/google/octopus: Implement touchscreen, digitizer power sequencing ...................................................................... mb/google/octopus: Implement touchscreen, digitizer power sequencing For touchscreens/digitizers on octopus variants, drive the enable GPIO high starting in bootblock, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens/ digitizers during ACPI SSDT generation. Change-Id: Ia725b4054069c0a4f60afd7e0bca6e2fd5fdcbba Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/octopus/variants/ampton/gpio.c M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/octopus/variants/bloog/gpio.c M src/mainboard/google/octopus/variants/bobba/gpio.c M src/mainboard/google/octopus/variants/dood/gpio.c M src/mainboard/google/octopus/variants/fleex/gpio.c M src/mainboard/google/octopus/variants/foob/gpio.c M src/mainboard/google/octopus/variants/garg/gpio.c M src/mainboard/google/octopus/variants/meep/gpio.c M src/mainboard/google/octopus/variants/phaser/gpio.c M src/mainboard/google/octopus/variants/yorp/gpio.c 11 files changed, 77 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/63212/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia725b4054069c0a4f60afd7e0bca6e2fd5fdcbba Gerrit-Change-Number: 63212 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/octopus: Implement touchscreen,digitizer power sequencing
by Matt DeVillier (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Raul Rangel, Paul Menzel, Tim Wawrzynczak, Karthik Ramasubramanian. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63212 ) Change subject: mb/google/octopus: Implement touchscreen,digitizer power sequencing ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63212/comment/e53ae34e_9b961aa0 PS2, Line 13: > So there is a problem with stock Chrome OS firmware? depends on your perspective - it does work properly, with ChromeOS. Currently, many ChromeOS devices in the coreboot tree have multiple I2C touchpad/touchscreen devices listed in the devicetree/overridetree. ACPI entries are generated for all of them, with a status value of 0xF (present and functional). This is wrong/violates spec, since it requires the OS to probe for each device to determine if it is actually there, rather than relying on the ACPI status being correct. Upstream Linux handles this somewhat; Windows completely craps out, since it believes that multiple devices are using the same resources (IRQ, GPIO, memory range). The correct way to handle the multiple component issue is to have coreboot only generate ACPI entries for the components which are present (or at the least, set the status to 0x0 for those that are not) -- To view, visit https://review.coreboot.org/c/coreboot/+/63212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia725b4054069c0a4f60afd7e0bca6e2fd5fdcbba Gerrit-Change-Number: 63212 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 15:01:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
by Sridhar Siricilla (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Kane Chen. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Kane Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63293 to look at the new patch set (#4). Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating ...................................................................... soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating The patch adds mechanism in the Alder Lake SoC code to control PCH USB2 Phy power gating from devicetree. Please refer Intel doc#723158 for more information. BUG=b:221461379 TEST=Build and boot Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63293/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d Gerrit-Change-Number: 63293 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/amd/chausie/port_descriptors: clean up variable names
by Felix Held (Code Review) 01 Apr '22

01 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63259 ) Change subject: mb/amd/chausie/port_descriptors: clean up variable names ...................................................................... mb/amd/chausie/port_descriptors: clean up variable names Remove "czn" from the variable names since chausie does not use cezanne. TEST=Timeless build Change-Id: I8cc854f4c60707c7fec5cd7fef1c4550883cd45a Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63259 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/chausie/port_descriptors.c 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/chausie/port_descriptors.c b/src/mainboard/amd/chausie/port_descriptors.c index 2609961..4a8a0fd 100644 --- a/src/mainboard/amd/chausie/port_descriptors.c +++ b/src/mainboard/amd/chausie/port_descriptors.c @@ -4,7 +4,7 @@ #include <soc/platform_descriptors.h> #include <types.h> -static const fsp_dxio_descriptor chausie_czn_dxio_descriptors[] = { +static const fsp_dxio_descriptor chausie_dxio_descriptors[] = { { /* GBE*/ .engine_type = PCIE_ENGINE, .port_present = true, @@ -47,7 +47,7 @@ }, }; -static const fsp_ddi_descriptor chausie_czn_ddi_descriptors[] = { +static const fsp_ddi_descriptor chausie_ddi_descriptors[] = { { /* DDI0 - eDP */ .connector_type = DDI_EDP, .aux_index = DDI_AUX1, @@ -79,8 +79,8 @@ const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - *dxio_descs = chausie_czn_dxio_descriptors; - *dxio_num = ARRAY_SIZE(chausie_czn_dxio_descriptors); - *ddi_descs = chausie_czn_ddi_descriptors; - *ddi_num = ARRAY_SIZE(chausie_czn_ddi_descriptors); + *dxio_descs = chausie_dxio_descriptors; + *dxio_num = ARRAY_SIZE(chausie_dxio_descriptors); + *ddi_descs = chausie_ddi_descriptors; + *ddi_num = ARRAY_SIZE(chausie_ddi_descriptors); } -- To view, visit https://review.coreboot.org/c/coreboot/+/63259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cc854f4c60707c7fec5cd7fef1c4550883cd45a Gerrit-Change-Number: 63259 Gerrit-PatchSet: 3 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/skyrim: Fix ESPI communication issues
by Felix Held (Code Review) 01 Apr '22

01 Apr '22

Attention is currently required from: Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63286 ) Change subject: mb/google/skyrim: Fix ESPI communication issues ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I951afdada8ee4f917cdeba8e287e5a2ae77c97ee Gerrit-Change-Number: 63286 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 01 Apr 2022 14:48:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2022