coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/hp/z220_series: Convert z220_sff_workstation into variant
by Angel Pons (Code Review) 03 Apr '22

03 Apr '22

Attention is currently required from: Felix Singer, Damien Zammit, Edward O'Callaghan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62808 ) Change subject: mb/hp/z220_series: Convert z220_sff_workstation into variant ...................................................................... Patch Set 3: (1 comment) File src/mainboard/hp/z220_series/variants/z220_sff_workstation/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62808/comment/35487efc_073f22f9 PS2, Line 5: subsystemid 0x103c 0x1791 inherit > Yes, without this line, the overridetree stops the devicetree from inheriting it because of it being […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/62808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aaac75216b2d7c8bb48801454ce616ace3b1422 Gerrit-Change-Number: 62808 Gerrit-PatchSet: 3 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Damien Zammit Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Sun, 03 Apr 2022 18:59:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Damien Zammit Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add support to control coreboot and Intel SoC features
by Sridhar Siricilla (Code Review) 03 Apr '22

03 Apr '22

Attention is currently required from: Nico Huber, Subrata Banik, Arthur Heymans, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/intel/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 17: (1 comment) File src/soc/intel/common/basecode/debug/debug_feature.c: https://review.coreboot.org/c/coreboot/+/61380/comment/29c306d1_eee9b36d PS16, Line 25: CONFIG_SI_DESC_REGION > Ack Ping for *code-review* vote if you have no other concern. -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 17 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 03 Apr 2022 18:02:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/fw.cfg: provide default SPL table binary
by 9elements QA (Code Review) 03 Apr '22

03 Apr '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61896 ) Change subject: soc/amd/cezanne/fw.cfg: provide default SPL table binary ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/99314 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/99313 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/99312 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/99311 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/99310 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/99309 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/99308 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/99307 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/99306 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/99305 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/99304 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/99303 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/99302 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/99301 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/99300 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/99299 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/61896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica960e5422da50899a2d9c192863188174e0bcff Gerrit-Change-Number: 61896 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 03 Apr 2022 17:55:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Add a macro to set explicitly second gen for old SOCs
by Felix Held (Code Review) 03 Apr '22

03 Apr '22

Attention is currently required from: Bao Zheng, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63319 ) Change subject: amdfwtool: Add a macro to set explicitly second gen for old SOCs ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: looks good to me File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/63319/comment/cc0ebf7c_34d90dbf PS1, Line 1808: amd_romsig->efs_gen.reserved = 0; i wonder if this should also be moved inside the set_efs_table function and if that should also be set in the case where efs_gen.gen is set to EFS_BEFORE_SECOND_GEN -- To view, visit https://review.coreboot.org/c/coreboot/+/63319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65caa11e835d2ff52bec4b8904057bbced434891 Gerrit-Change-Number: 63319 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Sun, 03 Apr 2022 17:15:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/fw.cfg: provide default SPL table binary
by Felix Held (Code Review) 03 Apr '22

03 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61896 ) Change subject: soc/amd/cezanne/fw.cfg: provide default SPL table binary ...................................................................... soc/amd/cezanne/fw.cfg: provide default SPL table binary Chause doesn't get to x86 bootblock without the SPL table binary in the PSP directory table, so I assume that Majolica won't get to x86 bootblock either, since the Cezanne SoC default is not to include any SPL table binary. This was caused by a combination of commit 6c5ec8e31ccbe3d9bbf201c956fc3b54703a9767 (amdfwtool: Add options to support mainboard specific SPL table) that caused a regression in amdfwtool and commit c5b912f788765560c1db08f3341826b9c548b865 (soc/amd/cezanne: Allow to specify SPL table path in Kconfig) that removed the default for the Cezanne SoC. Fix this by adding the default SPL table file back to the fw.cfg file which will get ignored by amdfwtool when a mainboard selects SPL_TABLE_FILE and specifies another SPL table binary. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ica960e5422da50899a2d9c192863188174e0bcff Reviewed-on: https://review.coreboot.org/c/coreboot/+/61896 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/fw.cfg 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/fw.cfg b/src/soc/amd/cezanne/fw.cfg index b733c45..372d371 100644 --- a/src/soc/amd/cezanne/fw.cfg +++ b/src/soc/amd/cezanne/fw.cfg @@ -29,6 +29,7 @@ DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin KEYDBBL_FILE TypeId0x50_KeyDbBl_CZN.sbin KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin +SPL_TABLE_FILE TypeId0x55_SplTableBl_CZN.sbin DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica960e5422da50899a2d9c192863188174e0bcff Gerrit-Change-Number: 61896 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/amdfwtool/data_parse: fix SPL table handling regression
by Felix Held (Code Review) 03 Apr '22

03 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63314 ) Change subject: util/amdfwtool/data_parse: fix SPL table handling regression ...................................................................... util/amdfwtool/data_parse: fix SPL table handling regression Use the SPL table binary from the config file if no override is specified via the spl-table command line argument. This fixes a regression caused by commit 6c5ec8e31ccbe3d9bbf201c956fc3b54703a9767 (amdfwtool: Add options to support mainboard specific SPL table). Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I93419a878b41b1dfcbf58d930740aaae553120f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63314 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M util/amdfwtool/data_parse.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 09b975d..a080eec 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -295,10 +295,10 @@ subprog = 0; } else if (strcmp(fw_name, "SPL_TABLE_FILE") == 0) { if (cb_config->have_mb_spl) { + fw_type = AMD_FW_SKIP; + } else { fw_type = AMD_FW_SPL; subprog = 0; - } else { - fw_type = AMD_FW_SKIP; } } else if (strcmp(fw_name, "DMCUERAMDCN21_FILE") == 0) { fw_type = AMD_FW_DMCU_ERAM; 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93419a878b41b1dfcbf58d930740aaae553120f6 Gerrit-Change-Number: 63314 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Enable UFS for ADL-N RVP
by Angel Pons (Code Review) 03 Apr '22

03 Apr '22

Attention is currently required from: Subrata Banik, Wonkyu Kim, Rizwan Qureshi, Tim Wawrzynczak, Meera Ravindranath, Patrick Rudolph, Gwendal Grignou. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62662 ) Change subject: mb/intel/adlrvp: Enable UFS for ADL-N RVP ...................................................................... Patch Set 4: Code-Review+1 (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62662/comment/0511bbd9_04b30030 PS4, Line 10: also needs to be enabled. Hence, enable ISH as well. How about: The PCI Local Bus Specification Revision 3.0 requires that multi-function devices always implement function 0. Because of this, enabling UFS (PCI device 12.7) requires ISH (PCI device 12.0) to be enabled as well. File src/mainboard/intel/adlrvp/devicetree_n.cb: https://review.coreboot.org/c/coreboot/+/62662/comment/afc98165_c35de692 PS1, Line 283: device ref ish on end > Is ish part of this CL? Yes, PCI spec requires that multi-function devices always implement function 0. Because of this, enabling the UFS PCI device (device pci 12.7) requires that the ISH PCI device (device pci 12.0) be enabled as well. File src/mainboard/intel/adlrvp/devicetree_n.cb: https://review.coreboot.org/c/coreboot/+/62662/comment/6ea2ed8e_aa387378 PS3, Line 283: on > then how pcie_rp7 is working here https://github. […] See the code in pcie_rp.c, the `struct pcie_rp_group` arrays in particular. After FSP does RP function swap, coreboot figures out which RPs have been function swapped and adjusts the devicetree accordingly at runtime (somewhere in ramstage). File src/mainboard/intel/adlrvp/devicetree_n.cb: https://review.coreboot.org/c/coreboot/+/62662/comment/39c936b1_3bd176a6 PS4, Line 287: device ref ish on end > Can you split patch? enabling ish is not related to enabling UFS PCI spec requires that multi-function devices always implement function 0. Because of this, enabling the UFS PCI device (device pci 12.7) requires that the ISH PCI device (device pci 12.0) be enabled as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/62662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If15bcaffc8fd3bbbe4b181820993ab2d882bbbe1 Gerrit-Change-Number: 62662 Gerrit-PatchSet: 4 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Comment-Date: Sun, 03 Apr 2022 12:45:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add support for UFS controller
by Angel Pons (Code Review) 03 Apr '22

03 Apr '22

Attention is currently required from: Wonkyu Kim, Subrata Banik, Kangheui Won, Paul Menzel, Rizwan Qureshi, Tim Wawrzynczak, Meera Ravindranath, Lean Sheng Tan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62856 ) Change subject: soc/intel/alderlake: Add support for UFS controller ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/62856/comment/7d12b433_f952adf6 PS2, Line 620: /* UFS */ > > Can you use is_devfn_enabled function like below? […] For reference, I got the device/function numbers from a header in slimbootloader: https://github.com/slimbootloader/slimbootloader/blob/master/Silicon/Alderl… // // SCS UFS Controller PCI config // #define PCI_DEVICE_NUMBER_PCH_SCS_UFS0 18 #define PCI_FUNCTION_NUMBER_PCH_SCS_UFS0 5 #define PCI_DEVICE_NUMBER_PCH_SCS_UFS1 18 #define PCI_FUNCTION_NUMBER_PCH_SCS_UFS1 7 -- To view, visit https://review.coreboot.org/c/coreboot/+/62856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4 Gerrit-Change-Number: 62856 Gerrit-PatchSet: 2 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sun, 03 Apr 2022 12:26:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add support for UFS controller
by Angel Pons (Code Review) 03 Apr '22

03 Apr '22

Attention is currently required from: Wonkyu Kim, Subrata Banik, Kangheui Won, Paul Menzel, Rizwan Qureshi, Tim Wawrzynczak, Meera Ravindranath. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62856 ) Change subject: soc/intel/alderlake: Add support for UFS controller ...................................................................... Patch Set 2: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62856/comment/b0846c1b_b6fc1a01 PS1, Line 8: > Add an introduction saying what UFS controller does, and where it’s documented? AIUI, UFS is the successor of eMMC File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/62856/comment/e460fc17_29af6021 PS2, Line 620: /* UFS */ > Can you use is_devfn_enabled function like below? > s_cfg->UfsEnable[1] = is_devfn_enabled(PCH_DEVFN_UFS); This would also work, yes. > s_cfg->UfsEnable[0] is not used? I think UFS-0 is PCI D18:F5 (0:12.5 in hex) and UFS-1 is PCI D18:F7 (0:12.7 in hex). I have no idea why UFS-0 is unused. I only see balls for one UFS controller in the datasheet. BTW, looks like document 691222-001 has a typo, it says UFS is PCI D18:F0, but that's actually ISH: https://imgur.com/AiA2TL8.png -- To view, visit https://review.coreboot.org/c/coreboot/+/62856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4 Gerrit-Change-Number: 62856 Gerrit-PatchSet: 2 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Sun, 03 Apr 2022 12:24:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/ironlake: Define CxJEDEC MCHBAR register
by build bot (Jenkins) (Code Review) 03 Apr '22

03 Apr '22

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61940 ) Change subject: nb/intel/ironlake: Define CxJEDEC MCHBAR register ...................................................................... Patch Set 2: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4196ffb85c6d32b62be0a80e8327bda6d102e49 Gerrit-Change-Number: 61940 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 03 Apr 2022 12:13:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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