coreboot-gerrit April 2022

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Change in coreboot[master]: mb/starlabs/lite: Add Lite Mk IV variant
by Sean Rhodes (Code Review) 03 Apr '22

03 Apr '22

Attention is currently required from: Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62706 ) Change subject: mb/starlabs/lite: Add Lite Mk IV variant ...................................................................... Patch Set 19: (4 comments) File src/mainboard/starlabs/lite/variants/glkr/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62706/comment/cef6cef3_e41d36a1 PS18, Line 6: # Graphics : # TODO: : # register "panel_cfg" = "{ : # .up_delay_ms = 0, // T3 : # .backlight_on_delay_ms = 0, // T7 : # .backlight_off_delay_ms = 0, // T9 : # .down_delay_ms = 0, // T10 : # .cycle_delay_ms = 500, // T12 : # .backlight_pwm_hz = 200, // PWM : # }" > Anything to do? Make libgfxinit work with GLK(R). Seeing as they all use the Broxton vbt, should be easy. https://review.coreboot.org/c/coreboot/+/62706/comment/ecdf694b_fe61ba56 PS18, Line 23: register "dptf_enable" = "0" > Can be omitted Done https://review.coreboot.org/c/coreboot/+/62706/comment/a2679b94_b317be48 PS18, Line 36: : register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" : register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" : register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" : register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" : register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" : register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" : : register "pcie_rp_deemphasis_enable[0]" = "1" : register "pcie_rp_deemphasis_enable[1]" = "1" : register "pcie_rp_deemphasis_enable[2]" = "1" : register "pcie_rp_deemphasis_enable[3]" = "1" : register "pcie_rp_deemphasis_enable[4]" = "1" : register "pcie_rp_deemphasis_enable[5]" = "1" > Hmmm, but all PCIe ports are off? According to FSP debug, still needed. File src/mainboard/starlabs/lite/variants/glkr/romstage.c: https://review.coreboot.org/c/coreboot/+/62706/comment/178738fd_473d6dd5 PS18, Line 52: void mainboard_memory_init_params(FSPM_UPD *memupd) > A bunch of the settings in here should be the same for GLK and GLKR. Can be done as a follow-up. Yup, once APL is done, I want to figure out how to de-dupe the code as around 70% of it is the same for APL, GLK and GLKR. -- To view, visit https://review.coreboot.org/c/coreboot/+/62706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1cf2846a139004e9bec7bb27e9afe07b7e6f64f Gerrit-Change-Number: 62706 Gerrit-PatchSet: 19 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 03 Apr 2022 20:37:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: register generic LPC resources
by Michael Niewöhner (Code Review) 03 Apr '22

03 Apr '22

Attention is currently required from: Felix Singer, Nico Huber, Michał Żygowski, Paul Menzel, Michał Kopeć, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63341 ) Change subject: soc/intel/common: register generic LPC resources ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/63341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f45b38498390016f841ab1d70c8438496dc857e Gerrit-Change-Number: 63341 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 03 Apr 2022 20:13:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs/merlin: Remove comment about OPWE
by Angel Pons (Code Review) 03 Apr '22

03 Apr '22

Attention is currently required from: Sean Rhodes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63171 ) Change subject: ec/starlabs/merlin: Remove comment about OPWE ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Oh no, the unicorns! -- To view, visit https://review.coreboot.org/c/coreboot/+/63171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a1310c779002dfb00d01a22437ea223bb406609 Gerrit-Change-Number: 63171 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Sun, 03 Apr 2022 19:32:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/lite: Add Lite Mk IV variant
by Angel Pons (Code Review) 03 Apr '22

03 Apr '22

Attention is currently required from: Sean Rhodes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62706 ) Change subject: mb/starlabs/lite: Add Lite Mk IV variant ...................................................................... Patch Set 18: Code-Review+1 (6 comments) File src/mainboard/starlabs/lite/Kconfig: https://review.coreboot.org/c/coreboot/+/62706/comment/623bcba5_caf99b7f PS18, Line 42: default "glkr" if BOARD_STARLABS_LITE_GLKR nit: if alignment? https://review.coreboot.org/c/coreboot/+/62706/comment/b1a03385_0c14784f PS18, Line 77: default "glkr" if BOARD_STARLABS_LITE_GLKR nit: if alignment? File src/mainboard/starlabs/lite/variants/glkr/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62706/comment/71c96ab7_9f83a670 PS18, Line 6: # Graphics : # TODO: : # register "panel_cfg" = "{ : # .up_delay_ms = 0, // T3 : # .backlight_on_delay_ms = 0, // T7 : # .backlight_off_delay_ms = 0, // T9 : # .down_delay_ms = 0, // T10 : # .cycle_delay_ms = 500, // T12 : # .backlight_pwm_hz = 200, // PWM : # }" Anything to do? https://review.coreboot.org/c/coreboot/+/62706/comment/55fdad8c_0df9e552 PS18, Line 23: register "dptf_enable" = "0" Can be omitted https://review.coreboot.org/c/coreboot/+/62706/comment/7fd4822c_1687ff3c PS18, Line 36: : register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" : register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" : register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" : register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" : register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" : register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" : : register "pcie_rp_deemphasis_enable[0]" = "1" : register "pcie_rp_deemphasis_enable[1]" = "1" : register "pcie_rp_deemphasis_enable[2]" = "1" : register "pcie_rp_deemphasis_enable[3]" = "1" : register "pcie_rp_deemphasis_enable[4]" = "1" : register "pcie_rp_deemphasis_enable[5]" = "1" Hmmm, but all PCIe ports are off? File src/mainboard/starlabs/lite/variants/glkr/romstage.c: https://review.coreboot.org/c/coreboot/+/62706/comment/13b37c76_24025bff PS18, Line 52: void mainboard_memory_init_params(FSPM_UPD *memupd) A bunch of the settings in here should be the same for GLK and GLKR. Can be done as a follow-up. -- To view, visit https://review.coreboot.org/c/coreboot/+/62706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1cf2846a139004e9bec7bb27e9afe07b7e6f64f Gerrit-Change-Number: 62706 Gerrit-PatchSet: 18 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Sun, 03 Apr 2022 19:32:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/mb/facebook/fbg1701: Remove IGNORE_IASL_MISSING_DEPENDENCY
by Angel Pons (Code Review) 03 Apr '22

03 Apr '22

Attention is currently required from: Frans Hendriks. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63243 ) Change subject: src/mb/facebook/fbg1701: Remove IGNORE_IASL_MISSING_DEPENDENCY ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I014a9078cb12908c515a978e4111ff9facc9e443 Gerrit-Change-Number: 63243 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Comment-Date: Sun, 03 Apr 2022 19:23:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/mb/facebook/fbg1701/acpi/superio.asl: Remove _PSR
by Angel Pons (Code Review) 03 Apr '22

03 Apr '22

Attention is currently required from: Frans Hendriks. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63242 ) Change subject: src/mb/facebook/fbg1701/acpi/superio.asl: Remove _PSR ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63242/comment/78aa2bcd_8bffc720 PS2, Line 7: _PSR typo: _PRS -- To view, visit https://review.coreboot.org/c/coreboot/+/63242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9e004e192bc7f9680c3728ce7c60d56f1a13945 Gerrit-Change-Number: 63242 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Comment-Date: Sun, 03 Apr 2022 19:22:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/wifi/generic/acpi.c: NULL-check pointers before dereferencing
by Angel Pons (Code Review) 03 Apr '22

03 Apr '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63340 ) Change subject: drivers/wifi/generic/acpi.c: NULL-check pointers before dereferencing ...................................................................... drivers/wifi/generic/acpi.c: NULL-check pointers before dereferencing Checking whether a pointer is NULL after it has been dereferenced makes zero sense. Make sure the `wifi_ssdt_write_properties()` function never gets invoked with a NULL argument for the `dev` parameter, and simplify the logic around the `is_cnvi_ddr_rfim_enabled` variable accordingly. Change-Id: I3fbc9565e7e9b4e1c14a68f6a5fd779577045236 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/wifi/generic/acpi.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/63340/1 diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 65940d6..ee09631 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -533,11 +533,9 @@ static void wifi_ssdt_write_properties(const struct device *dev, const char *scope) { - bool is_cnvi_ddr_rfim_enabled = false; - const struct drivers_wifi_generic_config *config = dev->chip_info; - if (dev && config) - is_cnvi_ddr_rfim_enabled = config->enable_cnvi_ddr_rfim; + + bool is_cnvi_ddr_rfim_enabled = config && config->enable_cnvi_ddr_rfim; /* Scope */ acpigen_write_scope(scope); @@ -646,6 +644,8 @@ void wifi_cnvi_fill_ssdt(const struct device *dev) { const char *path; + if (!dev) + return; path = acpi_device_path(dev->bus->dev); if (!path) -- To view, visit https://review.coreboot.org/c/coreboot/+/63340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fbc9565e7e9b4e1c14a68f6a5fd779577045236 Gerrit-Change-Number: 63340 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR Kconfig
by Sridhar Siricilla (Code Review) 03 Apr '22

03 Apr '22

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63339 ) Change subject: soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR Kconfig ...................................................................... soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR Kconfig The patch removes Kconfig CONFIG_ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR code which updates PMC descriptor for an intermediate ADL-P SoC stepping. Since intermediate ADL-P SoC is no longer supported, removing the code that updates PMC descriptor. TEST=Build and boot Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I2a629353a4194a7505655346dcab4ef53059e0b7 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/bootblock/bootblock.c D src/soc/intel/alderlake/bootblock/pmc_descriptor.c 4 files changed, 0 insertions(+), 101 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/63339/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 25d11d3..eed157a 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -112,15 +112,6 @@ select UDK_202005_BINDING select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM -config ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR - bool - help - Alder Lake stepping A0 needs a different value for a PMC setting in - the IFD. When this option is selected, coreboot will update the IFD - value at runtime, which allows using an IFD with the new value with - any CPU stepping. To apply this workaround, the IFD region needs to - be writable by the host. - config ALDERLAKE_CAR_ENHANCED_NEM bool default y if !INTEL_CAR_NEM diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 095d210..d2c48b7 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -16,7 +16,6 @@ bootblock-y += espi.c bootblock-y += gpio.c bootblock-y += p2sb.c -bootblock-$(CONFIG_ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR) += bootblock/pmc_descriptor.c romstage-y += espi.c romstage-y += gpio.c diff --git a/src/soc/intel/alderlake/bootblock/bootblock.c b/src/soc/intel/alderlake/bootblock/bootblock.c index e209ae2..b8086a4 100644 --- a/src/soc/intel/alderlake/bootblock/bootblock.c +++ b/src/soc/intel/alderlake/bootblock/bootblock.c @@ -25,9 +25,6 @@ void bootblock_soc_init(void) { - if (CONFIG(ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR)) - configure_pmc_descriptor(); - report_platform_info(); bootblock_pch_init(); diff --git a/src/soc/intel/alderlake/bootblock/pmc_descriptor.c b/src/soc/intel/alderlake/bootblock/pmc_descriptor.c deleted file mode 100644 index c585f70..0000000 --- a/src/soc/intel/alderlake/bootblock/pmc_descriptor.c +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <arch/cpu.h> -#include <arch/mmio.h> -#include <cf9_reset.h> -#include <commonlib/region.h> -#include <console/console.h> -#include <cpu/intel/cpu_ids.h> -#include <fmap.h> -#include <intelblocks/pmclib.h> -#include <soc/bootblock.h> -#include <types.h> - -#define PMC_DESC_7_BYTE3 0xc32 - -/* Flash Master 1 : HOST/BIOS */ -#define FLMSTR1 0x80 - -/* Flash signature Offset */ -#define FLASH_SIGN_OFFSET 0x10 -#define FLMSTR_WR_SHIFT_V2 20 -#define FLASH_VAL_SIGN 0xFF0A55A - -/* It checks whether host(Flash Master 1) has write access to the Descriptor Region or not */ -static int is_descriptor_writeable(uint8_t *desc) -{ - /* Check flash has valid signature */ - if (read32((void *)(desc + FLASH_SIGN_OFFSET)) != FLASH_VAL_SIGN) { - printk(BIOS_DEBUG, "Flash Descriptor is not valid\n"); - return 0; - } - - /* Check host has write access to the Descriptor Region */ - if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { - printk(BIOS_DEBUG, "Host doesn't have write access to Descriptor Region\n"); - return 0; - } - - return 1; -} - -/* It updates PMC Descriptor in the Descriptor Region */ -void configure_pmc_descriptor(void) -{ - uint8_t si_desc_buf[CONFIG_SI_DESC_REGION_SZ]; - struct region_device desc_rdev; - - if (cpu_get_cpuid() != CPUID_ALDERLAKE_A0) - return; - - if (fmap_locate_area_as_rdev_rw(CONFIG_SI_DESC_REGION, &desc_rdev) < 0) { - printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", CONFIG_SI_DESC_REGION); - return; - } - - if (rdev_readat(&desc_rdev, si_desc_buf, 0, CONFIG_SI_DESC_REGION_SZ) != - CONFIG_SI_DESC_REGION_SZ) { - printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); - return; - } - - if (!is_descriptor_writeable(si_desc_buf)) - return; - - if (si_desc_buf[PMC_DESC_7_BYTE3] != 0x40) { - printk(BIOS_DEBUG, "Update of PMC Descriptor is not required!\n"); - return; - } - - si_desc_buf[PMC_DESC_7_BYTE3] = 0x44; - - if (rdev_eraseat(&desc_rdev, 0, CONFIG_SI_DESC_REGION_SZ) != CONFIG_SI_DESC_REGION_SZ) { - printk(BIOS_ERR, "Failed to erase Descriptor Region area\n"); - return; - } - - if (rdev_writeat(&desc_rdev, si_desc_buf, 0, CONFIG_SI_DESC_REGION_SZ) - != CONFIG_SI_DESC_REGION_SZ) { - printk(BIOS_ERR, "Failed to update Descriptor Region\n"); - return; - } - - printk(BIOS_DEBUG, "Update of PMC Descriptor successful, trigger GLOBAL RESET\n"); - - pmc_global_reset_enable(true); - do_full_reset(); - die("Failed to trigger GLOBAL RESET\n"); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/63339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a629353a4194a7505655346dcab4ef53059e0b7 Gerrit-Change-Number: 63339 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mb/facebook/monolith: Remove IGNORE_IASL_MISSING_DEPENDENCY
by Angel Pons (Code Review) 03 Apr '22

03 Apr '22

Attention is currently required from: Frans Hendriks. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63245 ) Change subject: src/mb/facebook/monolith: Remove IGNORE_IASL_MISSING_DEPENDENCY ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d7c99e69d56aa8ebe08b52c91ef800390263185 Gerrit-Change-Number: 63245 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Comment-Date: Sun, 03 Apr 2022 19:04:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/mb/facebook/monolith/acpi/superio.asl: Remove _PRS
by Angel Pons (Code Review) 03 Apr '22

03 Apr '22

Attention is currently required from: Frans Hendriks. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63244 ) Change subject: src/mb/facebook/monolith/acpi/superio.asl: Remove _PRS ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I554d3497255c1e50cdbe74b1cffc9f2c59fbae77 Gerrit-Change-Number: 63244 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Comment-Date: Sun, 03 Apr 2022 19:04:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2022