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Change subject: drivers/i2c/dw_i2c: Add detect callback to i2c_bus_ops
......................................................................
Patch Set 2:
(1 comment)
File src/drivers/i2c/designware/dw_i2c.c:
https://review.coreboot.org/c/coreboot/+/63210/comment/b110a633_02c14589
PS1, Line 544: dw_i2c_disable
> Can an interrupt sneak in between the clear and disable? Should we disable before clearing? […]
Seems unlikely in this case, as the bus has already gone idle, so the transaction is done from the controller perspective, and the target device cannot initiate anything.
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Change subject: soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetree
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/63303/comment/3dc207d5_988394bb
PS2, Line 448: VrPowerDeliveryDesign
Please use snake case here, e.g.
`vr_power_delivery_design`
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Change subject: soc/intel/alderlake: Hook up PAVP to Kconfig
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Patch Set 2: Code-Review+2
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Change subject: drivers/wifi/generic/acpi.c: NULL-check pointers before dereferencing
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
Thanks Angel!
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Change subject: tpm: Accept Google Ti50 TPM DID:VID
......................................................................
Patch Set 11:
(1 comment)
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/63158/comment/7b14a365_478e5dd8
PS11, Line 32: MAINBOARD_HAS_I2C_TPM_TI50
Brya boards do not have Ti50 on them in general, this should go in BASEBOARD_NISSA I believe
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Change subject: soc/intel/alderlake: Add support for UFS controller
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62856/comment/eab250b9_d5cb63f7
PS2, Line 620: /* UFS */
> This is right, UFS controller 0 is unused in case of ADL-N/P/M.
> And hence we are enabling index 1.
Thanks for confirming!
Marking this as unresolved, as the original comment isn't fully addressed. Personally, I'd go with the following:
/* UfsEnable[0] is unused on ADL-M/N/P */
s_cfg->UfsEnable[1] = is_devfn_enabled(PCH_DEVFN_UFS);
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Change subject: soc/intel/alderlake: Add support for UFS controller
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62856/comment/c63092c9_728738db
PS2, Line 620: /* UFS */
> This is right, UFS controller 0 is unused in case of ADL-N/P/M. […]
Hi Meera. do you mean UFS controller 0 wont work with ADL-P PCH or just ADL-P RVP?
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