coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: tpm: Accept Google Ti50 TPM DID:VID
by Jes Klinke (Code Review) 04 Apr '22

04 Apr '22

Attention is currently required from: Jes Klinke, Christian Walter. Hello build bot (Jenkins), Tim Wawrzynczak, Christian Walter, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63158 to look at the new patch set (#12). Change subject: tpm: Accept Google Ti50 TPM DID:VID ...................................................................... tpm: Accept Google Ti50 TPM DID:VID A new iteration of Google's TPM implementation will advertize a new DID:VID, but otherwise follow the same protocol as the earlier design. Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Signed-off-by: Jes B. Klinke <jbk(a)chromium.org> --- M src/drivers/i2c/tpm/Kconfig M src/drivers/i2c/tpm/cr50.c M src/drivers/spi/tpm/tpm.c M src/drivers/tpm/cr50.c M src/drivers/tpm/cr50.h M src/mainboard/google/brya/Kconfig A src/mainboard/google/volteer/.history_*outside* 7 files changed, 543 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/63158/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/63158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Gerrit-Change-Number: 63158 Gerrit-PatchSet: 12 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jett Rink <jettrink(a)chromium.org> Gerrit-CC: Jett Rink <jettrink(a)google.com> Gerrit-Attention: Jes Klinke <jbk(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: correcting the samsung part number vau...
by Robert Zieba (Code Review) 04 Apr '22

04 Apr '22

Attention is currently required from: Chris Wang, Felix Held. Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63354 ) Change subject: mb/google/guybrush/var/dewatt: correcting the samsung part number vaule in SPD data ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Looks good to me, but I can only give a +1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35dc5f036a29cdf4763389b6425df99ff63bbfa0 Gerrit-Change-Number: 63354 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 04 Apr 2022 18:34:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE
by Tim Wawrzynczak (Code Review) 04 Apr '22

04 Apr '22

Attention is currently required from: Sridhar Siricilla. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62843 ) Change subject: soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie55ded673c8fa0edf2ca6789b15771bd2e56c95e Gerrit-Change-Number: 62843 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)gmail.com> Gerrit-Comment-Date: Mon, 04 Apr 2022 18:19:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: crossgcc: Upgrade binutils from 2.37 to 2.38
by Elyes Haouas (Code Review) 04 Apr '22

04 Apr '22

Attention is currently required from: Martin Roth. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61767 ) Change subject: crossgcc: Upgrade binutils from 2.37 to 2.38 ...................................................................... Patch Set 13: (1 comment) Patchset: PS13: > I'll see what I can figure out. […] Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/61767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94a11e52be878b13eae9f00f7d6dc1ab2053693e Gerrit-Change-Number: 61767 Gerrit-PatchSet: 13 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Mon, 04 Apr 2022 18:18:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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Change in coreboot[master]: Makefile.inc: Move adding bootblock non-x86 targets
by Martin Roth (Code Review) 04 Apr '22

04 Apr '22

Attention is currently required from: Arthur Heymans. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63217 ) Change subject: Makefile.inc: Move adding bootblock non-x86 targets ...................................................................... Patch Set 5: (1 comment) File Makefile.inc: https://review.coreboot.org/c/coreboot/+/63217/comment/bb48e5fc_debfb65f PS5, Line 1161: ifneq ($(CONFIG_ARCH_X86),y) Shouldn't this be part of a target or something? Right now it looks like it's just a bare part of the makefile that will get run when the makefile is sourced regardless of what target is being run. -- To view, visit https://review.coreboot.org/c/coreboot/+/63217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50eae4f00d171d26a221ca969086f4f294fa524b Gerrit-Change-Number: 63217 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 04 Apr 2022 18:17:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR Kconfig
by Sridhar Siricilla (Code Review) 04 Apr '22

04 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63339 ) Change subject: soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR Kconfig ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63339/comment/f820be8e_9753645f PS1, Line 13: > Briefly mention that no board selects it anymore? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a629353a4194a7505655346dcab4ef53059e0b7 Gerrit-Change-Number: 63339 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 04 Apr 2022 18:12:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR Kconfig
by Sridhar Siricilla (Code Review) 04 Apr '22

04 Apr '22

Attention is currently required from: Subrata Banik, Sridhar Siricilla. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63339 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR Kconfig ...................................................................... soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR Kconfig The patch removes Kconfig CONFIG_ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR code which updates PMC descriptor for an intermediate ADL-P SoC stepping. Since intermediate ADL-P SoC is no longer supported and no board is selecting the Kconfig, so removing the code that updates PMC descriptor. TEST=Build and boot Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I2a629353a4194a7505655346dcab4ef53059e0b7 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/bootblock/bootblock.c D src/soc/intel/alderlake/bootblock/pmc_descriptor.c 4 files changed, 0 insertions(+), 101 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/63339/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a629353a4194a7505655346dcab4ef53059e0b7 Gerrit-Change-Number: 63339 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add new CPU ID
by Angel Pons (Code Review) 04 Apr '22

04 Apr '22

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63302 ) Change subject: soc/intel/alderlake: Add new CPU ID ...................................................................... soc/intel/alderlake: Add new CPU ID Add new CPU ID 0x906A3 (L0 stepping). Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I280da46e5fdd3792df50556e2804b3bcb346eee3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63302 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/cpu/intel/cpu_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c 3 files changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index f0c1baf..6d36851 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -54,6 +54,7 @@ #define CPUID_ALDERLAKE_J0 0x906a0 #define CPUID_ALDERLAKE_Q0 0x906a1 #define CPUID_ALDERLAKE_K0 0x906a2 +#define CPUID_ALDERLAKE_L0 0x906a3 #define CPUID_ALDERLAKE_R0 0x906a4 #define CPUID_ALDERLAKE_N_A0 0xb06e0 #define CPUID_METEORLAKE_A0_1 0xa06a0 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 721355c..bdce2b7 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -25,6 +25,7 @@ } cpu_table[] = { { CPUID_ALDERLAKE_J0, "Alderlake J0 Platform" }, { CPUID_ALDERLAKE_K0, "Alderlake K0 Platform" }, + { CPUID_ALDERLAKE_L0, "Alderlake L0 Platform" }, { CPUID_ALDERLAKE_Q0, "Alderlake Q0 Platform" }, { CPUID_ALDERLAKE_R0, "Alderlake R0 Platform" }, { CPUID_ALDERLAKE_N_A0, "Alderlake-N Platform" }, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 0305815..823f23e 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -72,6 +72,7 @@ { X86_VENDOR_INTEL, CPUID_ALDERLAKE_S_A0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_J0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_K0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_L0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_Q0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_R0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/63302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I280da46e5fdd3792df50556e2804b3bcb346eee3 Gerrit-Change-Number: 63302 Gerrit-PatchSet: 2 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Update CPU IDs with correct steppings
by Angel Pons (Code Review) 04 Apr '22

04 Apr '22

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63299 ) Change subject: soc/intel/alderlake: Update CPU IDs with correct steppings ...................................................................... soc/intel/alderlake: Update CPU IDs with correct steppings Update ADL CPU IDs per correct steppings listed in Intel Doc 626774. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I722043c493b8c3de8965bcaa13f33c907d51f284 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63299 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/intel/mipi_camera/camera.c M src/include/cpu/intel/cpu_ids.h M src/soc/intel/alderlake/bootblock/pmc_descriptor.c M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/common/block/cpu/mp_init.c 7 files changed, 16 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index d846c81..5e3c4bb 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -138,7 +138,7 @@ port_name[i] = strdup(name); if (CONFIG(ACPI_ADL_IPU_ES_SUPPORT)) { u32 cpu_id = cpu_get_cpuid(); - if (cpu_id == CPUID_ALDERLAKE_A0 || cpu_id == CPUID_ALDERLAKE_A1 || + if (cpu_id == CPUID_ALDERLAKE_J0 || cpu_id == CPUID_ALDERLAKE_Q0 || cpu_id == CPUID_ALDERLAKE_N_A0) acpi_dp_add_integer(dsd, "is_es", 1); else diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 07e359a..f0c1baf 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -51,10 +51,10 @@ #define CPUID_ELKHARTLAKE_A0 0x90660 #define CPUID_ELKHARTLAKE_B0 0x90661 #define CPUID_ALDERLAKE_S_A0 0x90670 -#define CPUID_ALDERLAKE_A0 0x906a0 -#define CPUID_ALDERLAKE_A1 0x906a1 -#define CPUID_ALDERLAKE_A2 0x906a2 -#define CPUID_ALDERLAKE_A3 0x906a4 +#define CPUID_ALDERLAKE_J0 0x906a0 +#define CPUID_ALDERLAKE_Q0 0x906a1 +#define CPUID_ALDERLAKE_K0 0x906a2 +#define CPUID_ALDERLAKE_R0 0x906a4 #define CPUID_ALDERLAKE_N_A0 0xb06e0 #define CPUID_METEORLAKE_A0_1 0xa06a0 #define CPUID_METEORLAKE_A0_2 0xa06a1 diff --git a/src/soc/intel/alderlake/bootblock/pmc_descriptor.c b/src/soc/intel/alderlake/bootblock/pmc_descriptor.c index c585f70..14a9dcb 100644 --- a/src/soc/intel/alderlake/bootblock/pmc_descriptor.c +++ b/src/soc/intel/alderlake/bootblock/pmc_descriptor.c @@ -45,7 +45,7 @@ uint8_t si_desc_buf[CONFIG_SI_DESC_REGION_SZ]; struct region_device desc_rdev; - if (cpu_get_cpuid() != CPUID_ALDERLAKE_A0) + if (cpu_get_cpuid() != CPUID_ALDERLAKE_J0) return; if (fmap_locate_area_as_rdev_rw(CONFIG_SI_DESC_REGION, &desc_rdev) < 0) { diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 3342e4b..721355c 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -23,10 +23,10 @@ u32 cpuid; const char *name; } cpu_table[] = { - { CPUID_ALDERLAKE_A0, "Alderlake Platform" }, - { CPUID_ALDERLAKE_A1, "Alderlake Platform" }, - { CPUID_ALDERLAKE_A2, "Alderlake Platform" }, - { CPUID_ALDERLAKE_A3, "Alderlake Platform" }, + { CPUID_ALDERLAKE_J0, "Alderlake J0 Platform" }, + { CPUID_ALDERLAKE_K0, "Alderlake K0 Platform" }, + { CPUID_ALDERLAKE_Q0, "Alderlake Q0 Platform" }, + { CPUID_ALDERLAKE_R0, "Alderlake R0 Platform" }, { CPUID_ALDERLAKE_N_A0, "Alderlake-N Platform" }, }; diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 2e76cd7..fe21b41 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -273,7 +273,7 @@ const uint32_t cpuid = cpu_get_cpuid(); /* Disable VT-d for early silicon steppings as it results in a CPU hard hang */ - if (cpuid == CPUID_ALDERLAKE_A0 || cpuid == CPUID_ALDERLAKE_A1) { + if (cpuid == CPUID_ALDERLAKE_J0 || cpuid == CPUID_ALDERLAKE_Q0) { m_cfg->VtdDisable = 1; return; } diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 45421c8..5e79535 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -27,7 +27,7 @@ bool skip_cse_sub_part_update(void) { - return cpu_get_cpuid() != CPUID_ALDERLAKE_A2; + return cpu_get_cpuid() != CPUID_ALDERLAKE_K0; } /* Save the DIMM information for SMBIOS table 17 */ diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 2d838c5..0305815 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -70,10 +70,10 @@ { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_B0 }, { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_S_A0 }, - { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A0 }, - { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A1 }, - { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A2 }, - { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A3 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_J0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_K0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_Q0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_R0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0 }, { 0, 0 }, }; 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I722043c493b8c3de8965bcaa13f33c907d51f284 Gerrit-Change-Number: 63299 Gerrit-PatchSet: 4 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: crossgcc: Upgrade binutils from 2.37 to 2.38
by Martin Roth (Code Review) 04 Apr '22

04 Apr '22

Attention is currently required from: Elyes Haouas. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61767 ) Change subject: crossgcc: Upgrade binutils from 2.37 to 2.38 ...................................................................... Patch Set 13: (1 comment) Patchset: PS13: > I don't find why it failed. […] I'll see what I can figure out. The last time I tried upgrading the jenkins docker image, I had failures there too, so haven't completed that task yet. This will probably fit into that task. -- To view, visit https://review.coreboot.org/c/coreboot/+/61767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94a11e52be878b13eae9f00f7d6dc1ab2053693e Gerrit-Change-Number: 61767 Gerrit-PatchSet: 13 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 04 Apr 2022 17:20:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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coreboot-gerrit April 2022