Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63349 )
Change subject: mb/ti/beaglebone/board.fmd: USe 'FLASH' for device name
......................................................................
mb/ti/beaglebone/board.fmd: USe 'FLASH' for device name
FLASH is often used when accessing FMAP base and size from
fmap_config.h so it's handy to be consistent with all other boards.
Change-Id: Ibba938c72d42ac74dcea8e8e6478ddae510d8c03
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/ti/beaglebone/board.fmd
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/63349/1
diff --git a/src/mainboard/ti/beaglebone/board.fmd b/src/mainboard/ti/beaglebone/board.fmd
index c0e4281..0656b85 100644
--- a/src/mainboard/ti/beaglebone/board.fmd
+++ b/src/mainboard/ti/beaglebone/board.fmd
@@ -1,4 +1,4 @@
-SDCARD@0x000 32M {
+FLASH@0x000 32M {
BIOS@0x0 109K {
BOOTBLOCK@0x0 20K
}
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Change subject: Makefile.inc: Generate master header and pointer as C structs
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Looks like TI beaglebone does not use 'flash' inside its FMAP.
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Change subject: soc/intel/alderlake: Hook up PAVP to Kconfig
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63304/comment/029ba107_4603e3e7
PS1, Line 7: Configure PAVP at compile-time
> +1
Done
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Change subject: soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetree
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63303/comment/470cba67_ba0c3dbf
PS1, Line 7: Add VrPowerDeliveryDesign to chip options
> Suggestion: […]
Done
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Change subject: soc/intel/alderlake: Hook up PAVP to Kconfig
......................................................................
soc/intel/alderlake: Hook up PAVP to Kconfig
Expose configuration of Intel PAVP (Protected Audio-Video Path, a
digital rights protection/management (DRM) technology for
multimedia content) to Kconfig.
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: I5a364a9781642eb366e5e502a4ee69008c19bcd6
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/63304/2
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Change subject: soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetree
......................................................................
soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetree
The FSP needs to program VrPowerDeliverDesign configuration per
platform according to the platform capabilities to avoid incorrect
electrial/power parameters. This value is an enum of the available
power delivery segments that are defined in the Platform Design
Guide.
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: I74859e6735e59a15084a9e690b43f68341862833
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/63303/2
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Change subject: soc/intel/alderlake: Add VrPowerDeliveryDesign to chip options
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/63303/comment/6d65510a_788f7b3a
PS1, Line 445: enum
> Would be nice to have this enum in the code.
it has more than 50 of them.. it would be great if Intel Engineers could help to upstream this info :P
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Change subject: soc/intel/alderlake: Update CPU IDs with correct steppings
......................................................................
soc/intel/alderlake: Update CPU IDs with correct steppings
Update ADL CPU IDs per correct steppings listed in Intel Doc 626774.
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: I722043c493b8c3de8965bcaa13f33c907d51f284
---
M src/drivers/intel/mipi_camera/camera.c
M src/include/cpu/intel/cpu_ids.h
M src/soc/intel/alderlake/bootblock/pmc_descriptor.c
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/alderlake/romstage/fsp_params.c
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/block/cpu/mp_init.c
7 files changed, 16 insertions(+), 16 deletions(-)
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Change subject: soc/intel/alderlake: Update CPU IDs with correct steppings
......................................................................
Patch Set 2:
(1 comment)
File src/include/cpu/intel/cpu_ids.h:
https://review.coreboot.org/c/coreboot/+/63299/comment/9acd17e2_10bd50d2
PS2, Line 54: #define CPUID_ALDERLAKE_J0 0x906a0
: #define CPUID_ALDERLAKE_Q0 0x906a1
: #define CPUID_ALDERLAKE_K0 0x906a2
: #define CPUID_ALDERLAKE_R0 0x906a4
> Out of curiosity, are these CPU IDs paired with a specific PCH type?
Yes sorrect. ADL-P is SoC hence PCH & CPU is packed in 1 single Die
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