coreboot-gerrit April 2022

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Change in coreboot[master]: mb/starlabs/labtop: Remove subsystem device ID
by Felix Held (Code Review) 06 Apr '22

06 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63348 ) Change subject: mb/starlabs/labtop: Remove subsystem device ID ...................................................................... mb/starlabs/labtop: Remove subsystem device ID Remove the subsystem device ID for HDA devices, so that the correct Intel [8086:xxxx] is used. This was an old workaround for Windows that is no longer required with a new driver. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I50c03a2df06af3ef1939afd0739e083a9056557f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63348 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/starlabs/labtop/variants/cml/devicetree.cb M src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb 2 files changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb index c0077a4..b3d7f34 100644 --- a/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb @@ -182,7 +182,6 @@ device pci 1f.1 off end # P2SB device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on # Intel HDA - subsystemid 0x10ec 0x1200 register "PchHdaAudioLinkHda" = "1" end device pci 1f.4 on end # SMBus diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb index 6264257..ed65f4e 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -232,7 +232,6 @@ device pci 1f.1 off end # P2SB device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on # Intel HDA - subsystemid 0x10ec 0x1200 register "PchHdaAudioLinkHdaEnable" = "1" end device pci 1f.4 on end # SMBus -- To view, visit https://review.coreboot.org/c/coreboot/+/63348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50c03a2df06af3ef1939afd0739e083a9056557f Gerrit-Change-Number: 63348 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/ehl/fsp_params: Set Intel Speed Step (Eist) from devicetree
by Felix Held (Code Review) 06 Apr '22

06 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63352 ) Change subject: soc/intel/ehl/fsp_params: Set Intel Speed Step (Eist) from devicetree ...................................................................... soc/intel/ehl/fsp_params: Set Intel Speed Step (Eist) from devicetree This patch provides the set value for intel speed step in devicetree for FSPS. Before that in case of not set value in device tree the default value of disabled was overwritten by default enabled of FSP. Test: mainboard/siemens/mc_ehl/variants/mc_ehl1 Check status of Bit 16 in MSR 0x1a0 after boot. Change-Id: I0a5ef4968a27978116c21ce35b3818c6b36e086f Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63352 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/elkhartlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 1584c6a..2100cc4 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -264,6 +264,9 @@ params->DdiPortCHpd = config->DdiPortCHpd; params->DdiPortCDdc = config->DdiPortCDdc; + /* Intel Speed Step */ + params->Eist = config->eist_enable; + /* Use coreboot MP PPI services if Kconfig is enabled */ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); -- To view, visit https://review.coreboot.org/c/coreboot/+/63352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a5ef4968a27978116c21ce35b3818c6b36e086f Gerrit-Change-Number: 63352 Gerrit-PatchSet: 4 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/fsp1_1: Rename hob finding functions
by Felix Held (Code Review) 06 Apr '22

06 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63204 ) Change subject: drivers/intel/fsp1_1: Rename hob finding functions ...................................................................... drivers/intel/fsp1_1: Rename hob finding functions The hob finding functions are never looped over so there is no point for the 'next' inside their name. Change-Id: I18e452d313612ba14edda479d43f2797f6c84034 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63204 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/intel/fsp1_1/hob.c M src/drivers/intel/fsp1_1/include/fsp/util.h M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp1_1/romstage.c M src/mainboard/google/cyan/spd/spd.c 6 files changed, 13 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index bba32d1..e7c5fb4 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -45,7 +45,7 @@ } /* Returns the next instance of the matched GUID HOB from the starting HOB. */ -void *get_next_guid_hob(const EFI_GUID *guid, const void *hob_start) +void *get_guid_hob(const EFI_GUID *guid, const void *hob_start) { EFI_PEI_HOB_POINTERS hob; @@ -62,7 +62,7 @@ /* * Returns the next instance of the matching resource HOB from the starting HOB. */ -void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start) +void *get_resource_hob(const EFI_GUID *guid, const void *hob_start) { EFI_PEI_HOB_POINTERS hob; diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index 0c9a1fa..2dec3f0 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -24,7 +24,7 @@ void fsp_notify(u32 phase); void print_hob_type_structure(u16 hob_type, void *hob_list_ptr); void print_fsp_info(FSP_INFO_HEADER *fsp_header); -void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start); +void *get_resource_hob(const EFI_GUID *guid, const void *hob_start); void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old, uint64_t new); void report_fsp_output(void); @@ -77,7 +77,7 @@ #endif void *get_hob_list(void); -void *get_next_guid_hob(const EFI_GUID *guid, const void *hob_start); +void *get_guid_hob(const EFI_GUID *guid, const void *hob_start); asmlinkage void chipset_teardown_car_main(void); diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 78700a9..7da85d4 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -120,7 +120,7 @@ /* Locate the FSP reserved memory area */ fsp_reserved_bytes = 0; - fsp_memory = get_next_resource_hob(&fsp_reserved_guid, hob_list_ptr); + fsp_memory = get_resource_hob(&fsp_reserved_guid, hob_list_ptr); if (fsp_memory == NULL) { fsp_verification_failure = 1; printk(BIOS_ERR, @@ -155,7 +155,7 @@ fsp_set_runtime(fsp_header, hob_list_ptr); /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ - cbmem_root = get_next_resource_hob(&bootldr_tolum_guid, hob_list_ptr); + cbmem_root = get_resource_hob(&bootldr_tolum_guid, hob_list_ptr); if (cbmem_root == NULL) { fsp_verification_failure = 1; printk(BIOS_ERR, "7.4: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); @@ -164,7 +164,7 @@ } /* Locate the FSP_SMBIOS_MEMORY_INFO HOB */ - memory_info_hob = get_next_guid_hob(&memory_info_hob_guid, + memory_info_hob = get_guid_hob(&memory_info_hob_guid, hob_list_ptr); if (memory_info_hob == NULL) { printk(BIOS_ERR, "FSP_SMBIOS_MEMORY_INFO HOB missing!\n"); @@ -185,7 +185,7 @@ * 7.5: EFI_PEI_GRAPHICS_INFO_HOB produced by SiliconInit * FSP_SMBIOS_MEMORY_INFO HOB verified above */ - hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr); + hob_ptr.Raw = get_guid_hob(&mrc_guid, hob_list_ptr); if ((hob_ptr.Raw == NULL) && (params->saved_data == NULL)) { printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n"); fsp_verification_failure = 1; @@ -236,7 +236,7 @@ "ERROR - coreboot's requirements not met by FSP binary!\n"); /* Locate the memory configuration data to speed up the next reboot */ - mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr); + mrc_hob = get_guid_hob(&mrc_guid, hob_list_ptr); if (mrc_hob == NULL) { printk(BIOS_DEBUG, "Memory Configuration Data Hob not present\n"); diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index d85ba7c..2ffa675 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -38,7 +38,7 @@ * FSP_SMBIOS_MEMORY_INFO HOB verified by raminit */ if ((fsp_info_header->ImageAttribute & GRAPHICS_SUPPORT_BIT) && - !get_next_guid_hob(&graphics_info_guid, hob_list_ptr) && + !get_guid_hob(&graphics_info_guid, hob_list_ptr) && CONFIG(DISPLAY_HOBS)) { printk(BIOS_ERR, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n"); printk(BIOS_ERR, "Missing one or more required FSP HOBs!\n"); @@ -117,7 +117,7 @@ u32 *vbt_hob; void *hob_list_ptr = get_hob_list(); - vbt_hob = get_next_guid_hob(&vbt_guid, hob_list_ptr); + vbt_hob = get_guid_hob(&vbt_guid, hob_list_ptr); if (vbt_hob == NULL) { printk(BIOS_ERR, "FSP_ERR: Graphics Data HOB is not present\n"); } else { diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 7fd1cf5..3f93f33 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -152,7 +152,7 @@ /* Locate the memory info HOB, presence validated by raminit */ hob_list_ptr = fsp_get_hob_list(); - hob_ptr = get_next_guid_hob(&memory_info_hob_guid, hob_list_ptr); + hob_ptr = get_guid_hob(&memory_info_hob_guid, hob_list_ptr); memory_info_hob = (FSP_SMBIOS_MEMORY_INFO *)(hob_ptr + 1); /* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */ diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index 21a298e..169b983 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -118,7 +118,7 @@ /* Locate the memory info HOB, presence validated by raminit */ hob_list_ptr = fsp_get_hob_list(); - hob_ptr = get_next_guid_hob(&memory_info_hob_guid, hob_list_ptr); + hob_ptr = get_guid_hob(&memory_info_hob_guid, hob_list_ptr); if (hob_ptr != NULL) { memory_info_hob = (FSP_SMBIOS_MEMORY_INFO *)(hob_ptr + 1); dimm->ddr_frequency = memory_info_hob->MemoryFrequencyInMHz; -- To view, visit https://review.coreboot.org/c/coreboot/+/63204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18e452d313612ba14edda479d43f2797f6c84034 Gerrit-Change-Number: 63204 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Add IOE SBI access for TCSS functions
by Felix Held (Code Review) 06 Apr '22

06 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63128 ) Change subject: soc/intel/common: Add IOE SBI access for TCSS functions ...................................................................... soc/intel/common: Add IOE SBI access for TCSS functions Meteor Lake has the IOE Die for TCSS. This change adds IOE SBI access for TCSS pad configuration and Thunderbolt authentication. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I324242a018fb47207dd426fc8acd103f677d5cab Signed-off-by: John Zhao <john.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63128 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/include/intelblocks/tcss.h M src/soc/intel/common/block/tcss/tcss.c 2 files changed, 20 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/include/intelblocks/tcss.h b/src/soc/intel/common/block/include/intelblocks/tcss.h index 5209858..12400d8 100644 --- a/src/soc/intel/common/block/include/intelblocks/tcss.h +++ b/src/soc/intel/common/block/include/intelblocks/tcss.h @@ -146,6 +146,7 @@ /* Method to configure pads */ void tcss_configure_aux_bias_pads_regbar(const struct typec_aux_bias_pads *pads); +void ioe_tcss_configure_aux_bias_pads_sbi(const struct typec_aux_bias_pads *pads); /* * 1) Initialize TCSS muxes to disconnected state @@ -163,5 +164,6 @@ /* Method to validate the Thunderbolt authentication */ bool tcss_valid_tbt_auth(void); +bool ioe_tcss_valid_tbt_auth(void); #endif /* _TCSS_H_ */ diff --git a/src/soc/intel/common/block/tcss/tcss.c b/src/soc/intel/common/block/tcss/tcss.c index f1a3584..18fff20 100644 --- a/src/soc/intel/common/block/tcss/tcss.c +++ b/src/soc/intel/common/block/tcss/tcss.c @@ -368,6 +368,19 @@ } } +void ioe_tcss_configure_aux_bias_pads_sbi( + const struct typec_aux_bias_pads *pads) +{ + for (size_t i = 0; i < MAX_TYPE_C_PORTS; i++) { + if (pads[i].pad_auxn_dc && pads[i].pad_auxp_dc) { + ioe_p2sb_sbi_write(PID_IOM, IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(i), + calc_bias_ctrl_reg_value(pads[i].pad_auxp_dc)); + ioe_p2sb_sbi_write(PID_IOM, IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(i), + calc_bias_ctrl_reg_value(pads[i].pad_auxn_dc)); + } + } +} + const struct tcss_port_map *tcss_get_port_info(size_t *num_ports) { static struct tcss_port_map port_map[MAX_TYPE_C_PORTS]; @@ -424,3 +437,8 @@ { return REGBAR32(PID_IOM, IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION; } + +bool ioe_tcss_valid_tbt_auth(void) +{ + return ioe_p2sb_sbi_read(PID_IOM, IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/63128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I324242a018fb47207dd426fc8acd103f677d5cab Gerrit-Change-Number: 63128 Gerrit-PatchSet: 3 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Abstract the common TCSS functions
by Felix Held (Code Review) 06 Apr '22

06 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62723 ) Change subject: soc/intel/common: Abstract the common TCSS functions ...................................................................... soc/intel/common: Abstract the common TCSS functions This change abstracts the common TCSS functions for pad configuration and Thunderbolt authentication. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Signed-off-by: John Zhao <john.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62723 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/tcss.c M src/soc/intel/common/block/include/intelblocks/tcss.h M src/soc/intel/common/block/tcss/Kconfig M src/soc/intel/common/block/tcss/tcss.c M src/soc/intel/common/block/usb4/usb4.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/tcss.c 10 files changed, 36 insertions(+), 38 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 25d11d3..3570f27 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -92,7 +92,6 @@ select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_TCSS - select SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_REGBAR select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 095d210..16784aa 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -43,6 +43,7 @@ ramstage-y += retimer.c ramstage-y += soundwire.c ramstage-y += systemagent.c +ramstage-y += tcss.c ramstage-y += vr_config.c ramstage-y += xhci.c ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c diff --git a/src/soc/intel/alderlake/tcss.c b/src/soc/intel/alderlake/tcss.c new file mode 100644 index 0000000..c51fe6c --- /dev/null +++ b/src/soc/intel/alderlake/tcss.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/tcss.h> + +const struct soc_tcss_ops tcss_ops = { + .configure_aux_bias_pads = tcss_configure_aux_bias_pads_regbar, + .valid_tbt_auth = tcss_valid_tbt_auth, +}; diff --git a/src/soc/intel/common/block/include/intelblocks/tcss.h b/src/soc/intel/common/block/include/intelblocks/tcss.h index 181eff0..5209858 100644 --- a/src/soc/intel/common/block/include/intelblocks/tcss.h +++ b/src/soc/intel/common/block/include/intelblocks/tcss.h @@ -137,12 +137,22 @@ gpio_t pad_auxp_dc; }; +struct soc_tcss_ops { + void (*configure_aux_bias_pads)(const struct typec_aux_bias_pads *pads); + bool (*valid_tbt_auth)(void); +}; + +extern const struct soc_tcss_ops tcss_ops; + +/* Method to configure pads */ +void tcss_configure_aux_bias_pads_regbar(const struct typec_aux_bias_pads *pads); + /* * 1) Initialize TCSS muxes to disconnected state * 2) Configure GPIO pads to provide DC Bias on AUX signals * 3) Detect DP-over-Type-C alternate mode */ -void tcss_configure(const struct typec_aux_bias_pads pads[MAX_TYPE_C_PORTS]); +void tcss_configure(const struct typec_aux_bias_pads aux_bias_pads[MAX_TYPE_C_PORTS]); /* * Method to get only the port information to initialize the muxes to @@ -152,6 +162,6 @@ const struct tcss_port_map *tcss_get_port_info(size_t *num_ports); /* Method to validate the Thunderbolt authentication */ -uint32_t tcss_valid_tbt_auth(void); +bool tcss_valid_tbt_auth(void); #endif /* _TCSS_H_ */ diff --git a/src/soc/intel/common/block/tcss/Kconfig b/src/soc/intel/common/block/tcss/Kconfig index 0b80cb9..2e67913 100644 --- a/src/soc/intel/common/block/tcss/Kconfig +++ b/src/soc/intel/common/block/tcss/Kconfig @@ -9,16 +9,3 @@ depends on SOC_INTEL_COMMON_BLOCK_TCSS && RUN_FSP_GOP help Enable displays to be detected over Type-C ports during boot. - -config SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_REGBAR - def_bool n - depends on SOC_INTEL_COMMON_BLOCK_TCSS - help - Enable TCSS registers access through REGBAR for platforms like - Tiger Lake and Alder Lake - -config SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_SBI - def_bool n - depends on SOC_INTEL_COMMON_BLOCK_TCSS - help - Enable TCSS registers access through Sideband interface on applicable SoC platforms diff --git a/src/soc/intel/common/block/tcss/tcss.c b/src/soc/intel/common/block/tcss/tcss.c index e0ca90d..f1a3584 100644 --- a/src/soc/intel/common/block/tcss/tcss.c +++ b/src/soc/intel/common/block/tcss/tcss.c @@ -355,7 +355,7 @@ cpu_pid; } -static void tcss_configure_aux_bias_pads_regbar( +void tcss_configure_aux_bias_pads_regbar( const struct typec_aux_bias_pads *pads) { for (size_t i = 0; i < MAX_TYPE_C_PORTS; i++) { @@ -368,16 +368,6 @@ } } -static void tcss_configure_aux_bias_pads( - const struct typec_aux_bias_pads *pads) -{ - if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_REGBAR)) - tcss_configure_aux_bias_pads_regbar(pads); - else - printk(BIOS_ERR, "%s: Error: No TCSS configuration method is selected!\n", - __func__); -} - const struct tcss_port_map *tcss_get_port_info(size_t *num_ports) { static struct tcss_port_map port_map[MAX_TYPE_C_PORTS]; @@ -423,19 +413,14 @@ tcss_init_mux(i, &port_map[i]); /* This should be performed before alternate modes are entered */ - tcss_configure_aux_bias_pads(aux_bias_pads); + if (tcss_ops.configure_aux_bias_pads) + tcss_ops.configure_aux_bias_pads(aux_bias_pads); if (CONFIG(ENABLE_TCSS_DISPLAY_DETECTION)) tcss_configure_dp_mode(port_map, num_ports); } -uint32_t tcss_valid_tbt_auth(void) +bool tcss_valid_tbt_auth(void) { - if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_REGBAR)) { - return REGBAR32(PID_IOM, IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION; - } else { - printk(BIOS_ERR, "%s: Error: No validation for Thunderbolt authentication!\n", - __func__); - return 0; - } + return REGBAR32(PID_IOM, IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION; } diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c index 6924bb7..86bd09b 100644 --- a/src/soc/intel/common/block/usb4/usb4.c +++ b/src/soc/intel/common/block/usb4/usb4.c @@ -29,7 +29,7 @@ { struct acpi_dp *dsd, *pkg; - if (!tcss_valid_tbt_auth()) + if (tcss_ops.valid_tbt_auth && !tcss_ops.valid_tbt_auth()) return; acpigen_write_scope(acpi_device_path(dev)); diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index df5c167..265aa5f 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -70,7 +70,6 @@ select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_TCSS - select SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_REGBAR select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE select SOC_INTEL_COMMON_BLOCK_USB4_XHCI diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 0b616be..8436980 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -40,6 +40,7 @@ ramstage-y += retimer.c ramstage-y += soundwire.c ramstage-y += systemagent.c +ramstage-y += tcss.c ramstage-y += xhci.c ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog_lib.c diff --git a/src/soc/intel/tigerlake/tcss.c b/src/soc/intel/tigerlake/tcss.c new file mode 100644 index 0000000..c51fe6c --- /dev/null +++ b/src/soc/intel/tigerlake/tcss.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/tcss.h> + +const struct soc_tcss_ops tcss_ops = { + .configure_aux_bias_pads = tcss_configure_aux_bias_pads_regbar, + .valid_tbt_auth = tcss_valid_tbt_auth, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/62723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Gerrit-Change-Number: 62723 Gerrit-PatchSet: 16 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Add support to control coreboot and Intel SoC features
by Felix Held (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Nico Huber, Subrata Banik, Sridhar Siricilla, Arthur Heymans, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/intel/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 17: (1 comment) File src/soc/intel/common/basecode/debug/debug_feature.c: https://review.coreboot.org/c/coreboot/+/61380/comment/73a445f4_83b0718e PS17, Line 23: uint8_t i'd use enum cb_err instead of uint8_t as return value and return CB_SUCCESS/CB_ERR -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 17 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 06 Apr 2022 16:15:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Allow coreboot to control FSP serial redirection
by Subrata Banik (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Arthur Heymans, Lean Sheng Tan, Michael Niewöhner, Andrey Petrov. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63166 ) Change subject: drivers/intel/fsp2_0: Allow coreboot to control FSP serial redirection ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > merge conflict. I will rebase Sheng, Thanks for pointing. -- To view, visit https://review.coreboot.org/c/coreboot/+/63166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b008ca9d4f40bfa6a989a6fd655c234f91fde65 Gerrit-Change-Number: 63166 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 15:52:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Initialize device_path subid
by Tim Wawrzynczak (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: 小田喜陽彦. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63384 ) Change subject: ec/google/chromeec: Initialize device_path subid ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Thanks Akihiko, not sure if I've seen you around coreboot before, welcome if you are new! -- To view, visit https://review.coreboot.org/c/coreboot/+/63384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910998a5555319cf9840493a31df4934054e08ce Gerrit-Change-Number: 63384 Gerrit-PatchSet: 1 Gerrit-Owner: 小田喜陽彦 <akihiko.odaki(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: 小田喜陽彦 <akihiko.odaki(a)gmail.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 15:50:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Initialize device_path subid
by Tim Wawrzynczak (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: 小田喜陽彦. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63384 ) Change subject: ec/google/chromeec: Initialize device_path subid ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910998a5555319cf9840493a31df4934054e08ce Gerrit-Change-Number: 63384 Gerrit-PatchSet: 1 Gerrit-Owner: 小田喜陽彦 <akihiko.odaki(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: 小田喜陽彦 <akihiko.odaki(a)gmail.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 15:50:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Hook up PAVP to Kconfig
by Tim Wawrzynczak (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Christian Walter, Angel Pons, Meera Ravindranath, Arthur Heymans, Lean Sheng Tan. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63304 ) Change subject: soc/intel/alderlake: Hook up PAVP to Kconfig ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: Thanks Sheng, we've been inadvertently relying on the default value of `1` in the FSP here. -- To view, visit https://review.coreboot.org/c/coreboot/+/63304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a364a9781642eb366e5e502a4ee69008c19bcd6 Gerrit-Change-Number: 63304 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 15:47:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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