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Change subject: soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetree
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Patch Set 3: Code-Review+2
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Change subject: sc7280: Performance improvement by removing delays in cpucp init
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Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63085/comment/4cf1014e_182d2982
PS6, Line 7: sc7280: Performance improvement by removing delays in cpucp init
Please make it a statement:
> Improve performance by removing delays in cpucp init
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Change subject: soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetree
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Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63303/comment/7edbd361_17ac3014
PS3, Line 8:
: The FSP needs to program VrPowerDeliverDesign configuration per
: platform according to the platform capabilities to avoid incorrect
: electrial/power parameters. This value is an enum of the available
: power delivery segments that are defined in the Platform Design
: Guide.
> if I am understanding correctly (and to be a little more specific), the FSP will read the SKU inform […]
Yes correct, but this upd will provide even more refined power settings out of more than 50 options from the table in FSP (unfortunately I am not sure I am allowed to open source the table).
Without setting this, FSP debug will print error log and applied a more generic power settings.
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Change subject: drivers/intel/fsp2_0: Allow coreboot to control FSP serial redirection
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Patch Set 2:
(1 comment)
Patchset:
PS2:
merge conflict.
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Change subject: soc/intel/cse: Allow calling all functions associated with `cse_final`
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Change subject: soc/intel/common/cse: Show CSE device slot and function number properly
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Change subject: soc/intel/common/cse: Show CSE device slot and function number properly
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Patch Set 1:
(1 comment)
Patchset:
PS1:
Good catch. Thanks for doing this!
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