coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

Change in coreboot[master]: util: Add amdfwread utility
by Robert Zieba (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Bao Zheng, Marshall Dawson, Felix Held. Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62795 ) Change subject: util: Add amdfwread utility ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > 54901 is kinda similar though it seems to be focused just on extracting the binaries. […] I took a deeper look into 54901 and it seems that amdfwtool is so focused on writing FW images that I think the resulting code would be cleaner if this sort of functionality is contained within its own tool. -- To view, visit https://review.coreboot.org/c/coreboot/+/62795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Gerrit-Change-Number: 62795 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 06 Apr 2022 18:06:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Robert Zieba <robertzieba(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/spd_tools: Add ability to override SPD file for parts
by Robert Zieba (Code Review) 06 Apr '22

06 Apr '22

Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63281 ) Change subject: util/spd_tools: Add ability to override SPD file for parts ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > can CB:62905 be reverted with this in place? I think it might be better to leave it in place because it's a fairly minor change and I can imagine situations in the future where it might be needed. But I don't have strong feelings either way. -- To view, visit https://review.coreboot.org/c/coreboot/+/63281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I078dd04fead2bf19f53bc6ca8295187d439adc20 Gerrit-Change-Number: 63281 Gerrit-PatchSet: 4 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 06 Apr 2022 18:06:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/qualcomm/common: update size of memchipinfo structure
by Shelley Chen (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Ravi Kumar Bokka. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63408 ) Change subject: soc/qualcomm/common: update size of memchipinfo structure ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Hey Ravi, you've uploaded a new Change-Id again. Can you please abandon this one and upload to https://review.coreboot.org/c/coreboot/+/63026/ where the original patch is? -- To view, visit https://review.coreboot.org/c/coreboot/+/63408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51113c61d6e54268a46d53ac9e4c846ccaec4e21 Gerrit-Change-Number: 63408 Gerrit-PatchSet: 2 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Wed, 06 Apr 2022 18:01:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/prodrive/atlas: Update GPIOs
by Lean Sheng Tan (Code Review) 06 Apr '22

06 Apr '22

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63411 ) Change subject: mb/prodrive/atlas: Update GPIOs ...................................................................... mb/prodrive/atlas: Update GPIOs Update Atlas GPIOs for GPD11 & E7. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I92a0d0797206cdba96d7c6efe264b0356b5157ea --- M src/mainboard/prodrive/atlas/early_gpio.c M src/mainboard/prodrive/atlas/gpio.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/63411/1 diff --git a/src/mainboard/prodrive/atlas/early_gpio.c b/src/mainboard/prodrive/atlas/early_gpio.c index b793752..de84763 100644 --- a/src/mainboard/prodrive/atlas/early_gpio.c +++ b/src/mainboard/prodrive/atlas/early_gpio.c @@ -11,6 +11,9 @@ /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* EC_IN_RW */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + /* PCH HSID */ PAD_CFG_GPI(GPP_A8, NONE, DEEP), PAD_CFG_GPI(GPP_F19, NONE, DEEP), diff --git a/src/mainboard/prodrive/atlas/gpio.c b/src/mainboard/prodrive/atlas/gpio.c index 0f92889..5d67aa7 100644 --- a/src/mainboard/prodrive/atlas/gpio.c +++ b/src/mainboard/prodrive/atlas/gpio.c @@ -76,6 +76,7 @@ /* ------- GPIO Group GPD ------- */ PAD_NC(GPD8, NONE), /* SUSCLK */ + PAD_CFG_GPO(GPD11, 1, PLTRST), /* LAN_DISABLE_N */ }; void configure_gpio_pads(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/63411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92a0d0797206cdba96d7c6efe264b0356b5157ea Gerrit-Change-Number: 63411 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/prodrive/atlas: Update correct SPD address
by Lean Sheng Tan (Code Review) 06 Apr '22

06 Apr '22

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63410 ) Change subject: mb/prodrive/atlas: Update correct SPD address ...................................................................... mb/prodrive/atlas: Update correct SPD address Update the SPD address as Atlas is using DIMM 0 & 1 in memory controller 1 channel 1. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: Icefcd23b57a7f97e1ee25fed20b35d0e2cb51145 --- M src/mainboard/prodrive/atlas/romstage_fsp_params.c 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/63410/1 diff --git a/src/mainboard/prodrive/atlas/romstage_fsp_params.c b/src/mainboard/prodrive/atlas/romstage_fsp_params.c index bd4c0a3..8aaef5b 100644 --- a/src/mainboard/prodrive/atlas/romstage_fsp_params.c +++ b/src/mainboard/prodrive/atlas/romstage_fsp_params.c @@ -35,11 +35,7 @@ const struct mem_spd dimm_module_spd_info = { .topo = MEM_TOPO_DIMM_MODULE, .smbus = { - [0] = { - .addr_dimm[0] = 0x50, - .addr_dimm[1] = 0x51, - }, - [1] = { + [3] = { .addr_dimm[0] = 0x52, .addr_dimm[1] = 0x53, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/63410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icefcd23b57a7f97e1ee25fed20b35d0e2cb51145 Gerrit-Change-Number: 63410 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: ec/starlabs/merlin: Correct Q event for CPU DN SPEED
by 9elements QA (Code Review) 06 Apr '22

06 Apr '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62901 ) Change subject: ec/starlabs/merlin: Correct Q event for CPU DN SPEED ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/99746 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/99745 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/99744 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/99743 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/99742 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/99741 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/99740 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/99739 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/99738 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/99737 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/99736 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/99735 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/99734 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/99733 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/99732 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/99731 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/62901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieea1c8d0923f6ea6b13cf76525c9c4c686a92c40 Gerrit-Change-Number: 62901 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 17:51:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD device
by Felix Held (Code Review) 06 Apr '22

06 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63295 ) Change subject: mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD device ...................................................................... mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD device Setting the clock source depends on clock request pin for WLAN/SD/SSD device. Also turn off the unused (CLKREQ#3) clock sources.In skyrim, clock source 0/1/2 are routed for WLAN/SD/SSD device. BUG=b:227297986 BRANCH=none TEST=Build Signed-off-by: Chris.Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I21fb912b69f59717eb4e84c379f706a0257a9ed1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63295 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Jon Murphy: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index 7f74d6d..a6894ee 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -47,6 +47,12 @@ register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # Audio/SAR register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC + # general purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" + register "gpp_clk_config[1]" = "GPP_CLK_REQ" + register "gpp_clk_config[2]" = "GPP_CLK_REQ" + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works device domain 0 on 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21fb912b69f59717eb4e84c379f706a0257a9ed1 Gerrit-Change-Number: 63295 Gerrit-PatchSet: 3 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: ChromeOS: Promote variant_cros_gpio()
by Felix Held (Code Review) 06 Apr '22

06 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58897 ) Change subject: ChromeOS: Promote variant_cros_gpio() ...................................................................... ChromeOS: Promote variant_cros_gpio() The only purpose of mainboard_chromeos_acpi_generate() was to pass cros_gpio array for ACPI \\OIPG package generation. Promote variant_cros_gpio() from baseboards to ChromeOS declaration. Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/amd/chausie/chromeos.c M src/mainboard/amd/majolica/chromeos.c M src/mainboard/emulation/qemu-q35/chromeos.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/brya/chromeos.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/chromeos.c M src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/glados/chromeos.c M src/mainboard/google/guybrush/chromeos.c M src/mainboard/google/hatch/chromeos.c M src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/kahlee/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/octopus/chromeos.c M src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/reef/chromeos.c M src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/sarien/chromeos.c M src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h M src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h M src/mainboard/google/skyrim/chromeos.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/google/volteer/chromeos.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/chromeos.c M src/mainboard/intel/adlrvp/chromeos.c M src/mainboard/intel/adlrvp/gpio_m.c M src/mainboard/intel/adlrvp/gpio_n.c M src/mainboard/intel/adlrvp/include/baseboard/variants.h M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/glkrvp/chromeos.c M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/jasperlake_rvp/chromeos.c M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/shadowmountain/chromeos.c M src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/tglrvp/chromeos.c M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c M src/vendorcode/google/chromeos/acpi.c M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/gnvs.c 70 files changed, 97 insertions(+), 321 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/amd/chausie/chromeos.c b/src/mainboard/amd/chausie/chromeos.c index 062fdad..fffde8d 100644 --- a/src/mainboard/amd/chausie/chromeos.c +++ b/src/mainboard/amd/chausie/chromeos.c @@ -18,11 +18,9 @@ return 0; } -static const struct cros_gpio cros_gpios[] = { - /* No ChromeOS GPIOs */ -}; - -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + /* No ChromeOS GPIOs */ + *num = 0; + return NULL; } diff --git a/src/mainboard/amd/majolica/chromeos.c b/src/mainboard/amd/majolica/chromeos.c index 14f89d1..acef8d1 100644 --- a/src/mainboard/amd/majolica/chromeos.c +++ b/src/mainboard/amd/majolica/chromeos.c @@ -18,11 +18,9 @@ return 0; } -static const struct cros_gpio cros_gpios[] = { - /* No ChromeOS GPIOs */ -}; - -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + /* No ChromeOS GPIOs */ + *num = 0; + return NULL; } diff --git a/src/mainboard/emulation/qemu-q35/chromeos.c b/src/mainboard/emulation/qemu-q35/chromeos.c index c4770ff..7fd2add 100644 --- a/src/mainboard/emulation/qemu-q35/chromeos.c +++ b/src/mainboard/emulation/qemu-q35/chromeos.c @@ -20,9 +20,10 @@ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, "QEMU"), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 9807ace..71f5099 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -36,9 +36,10 @@ CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index db64649..df051a8 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -70,9 +70,10 @@ CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/google/brya/chromeos.c b/src/mainboard/google/brya/chromeos.c index cb636c6..5c99371 100644 --- a/src/mainboard/google/brya/chromeos.c +++ b/src/mainboard/google/brya/chromeos.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/gpio.h> -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -24,14 +22,6 @@ return gpio_get(GPIO_PCH_WP); } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} - int get_ec_is_trusted(void) { /* EC is trusted if not in RW. */ diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h index 9accc08..8c79a8a 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h @@ -15,7 +15,6 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_gpio_override_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); -const struct cros_gpio *variant_cros_gpios(size_t *num); const struct pad_config *variant_romstage_gpio_table(size_t *num); const struct mb_cfg *variant_memory_params(void); diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index b4bd5fe..f31967c 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -53,9 +53,10 @@ CROS_GPIO_WP_AL(WP_GPIO, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index a11b6f9..6ecab94 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -60,9 +60,10 @@ CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c index ad37b20..5c99371 100644 --- a/src/mainboard/google/dedede/chromeos.c +++ b/src/mainboard/google/dedede/chromeos.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/gpio.h> -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -24,15 +22,6 @@ return gpio_get(GPIO_PCH_WP); } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} - int get_ec_is_trusted(void) { /* EC is trusted if not in RW. */ diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index 78e44b4..aef3075 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -13,7 +13,6 @@ const struct pad_config *variant_base_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); const struct pad_config *variant_sleep_gpio_table(size_t *num); -const struct cros_gpio *variant_cros_gpios(size_t *num); const struct pad_config *variant_override_gpio_table(size_t *num); /** diff --git a/src/mainboard/google/deltaur/chromeos.c b/src/mainboard/google/deltaur/chromeos.c index 778eccb..589d6c0 100644 --- a/src/mainboard/google/deltaur/chromeos.c +++ b/src/mainboard/google/deltaur/chromeos.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <baseboard/variants.h> #include <baseboard/gpio.h> #include <bootmode.h> #include <boot/coreboot_tables.h> @@ -42,15 +41,6 @@ return !gpio_get(GPIO_REC_MODE); } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *cros_gpios; - size_t num_gpios = 0; - - cros_gpios = variant_cros_gpios(&num_gpios); - - chromeos_acpi_gpio_generate(cros_gpios, num_gpios); -} int get_recovery_mode_switch(void) { diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h index aadbbec..682ff7f 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h @@ -28,7 +28,5 @@ const struct pad_config *override_gpio_table(size_t *num); const struct pad_config *override_early_gpio_table(size_t *num); -struct cros_gpio; -const struct cros_gpio *override_cros_gpios(size_t *num); #endif diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h index 6804ef6..f3a4059 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h @@ -6,7 +6,6 @@ #include <soc/gpio.h> #include <soc/meminit.h> #include <stddef.h> -#include <vendorcode/google/chromeos/chromeos.h> /* * The next set of functions return the gpio table and fill in the number of @@ -16,8 +15,6 @@ const struct pad_config *variant_early_gpio_table(size_t *num); const struct pad_config *variant_override_gpio_table(size_t *num); -const struct cros_gpio *variant_cros_gpios(size_t *num); - const struct mb_cfg *variant_memory_params(void); void variant_memory_init(FSPM_UPD *mupd); diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index 0891f87..4c5c8b8 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -40,15 +40,6 @@ return !gpio_get(GPP_E8); } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *cros_gpios; - size_t num_gpios = 0; - - cros_gpios = variant_cros_gpios(&num_gpios); - - chromeos_acpi_gpio_generate(cros_gpios, num_gpios); -} int get_recovery_mode_switch(void) { diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h index 22a2d45..db0b3a9 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h @@ -29,7 +29,4 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); -struct cros_gpio; -const struct cros_gpio *variant_cros_gpios(size_t *num); - #endif diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index bc458de..fadec40 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -32,9 +32,10 @@ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index d10a59f..59105ce 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -3,10 +3,8 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> -#include <baseboard/variants.h> #include <soc/gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h> @@ -28,15 +26,6 @@ return gpio_get(GPIO_PCH_WP); } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} - int get_ec_is_trusted(void) { /* EC is trusted if not in RW. */ diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h index cf22926..ae5eeff 100644 --- a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h @@ -5,7 +5,6 @@ #include <soc/gpio.h> #include <stdint.h> -#include <vendorcode/google/chromeos/chromeos.h> /* * The next set of functions return the gpio table and fill in the number of @@ -14,8 +13,6 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); -const struct cros_gpio *variant_cros_gpios(size_t *num); - void variant_smi_sleep(u8 slp_typ); struct nhlt; diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 1adaed4..c90d12d 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -31,9 +31,10 @@ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/google/guybrush/chromeos.c b/src/mainboard/google/guybrush/chromeos.c index 9875554..c5530db 100644 --- a/src/mainboard/google/guybrush/chromeos.c +++ b/src/mainboard/google/guybrush/chromeos.c @@ -23,9 +23,10 @@ CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index bbca895..9c5e19d 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -1,13 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> #include <variant/gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -26,16 +24,6 @@ return gpio_get(GPIO_PCH_WP); } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *cros_gpios; - size_t num_gpios = 0; - - cros_gpios = variant_cros_gpios(&num_gpios); - - chromeos_acpi_gpio_generate(cros_gpios, num_gpios); -} - int get_ec_is_trusted(void) { /* EC is trusted if not in RW. */ diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index 2f06a55..125f738 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -6,7 +6,6 @@ #include <soc/cnl_memcfg_init.h> #include <soc/gpio.h> #include <stdint.h> -#include <vendorcode/google/chromeos/chromeos.h> /* * The next set of functions return the gpio table and fill in the number of @@ -28,9 +27,6 @@ /* Return GPIO pads that need to be configured before ramstage */ const struct pad_config *variant_early_gpio_table(size_t *num); -/* Return ChromeOS gpio table and fill in number of entries. */ -const struct cros_gpio *variant_cros_gpios(size_t *num); - /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 239134b..c5ebc72 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -72,9 +72,10 @@ CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index 690a9e3..c7f7671 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -30,9 +30,10 @@ CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index f544167..a1ac2d6 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -37,9 +37,10 @@ CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/google/octopus/chromeos.c b/src/mainboard/google/octopus/chromeos.c index 82599ac..42eeeee 100644 --- a/src/mainboard/google/octopus/chromeos.c +++ b/src/mainboard/google/octopus/chromeos.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <variant/gpio.h> @@ -27,15 +25,6 @@ return gpio_get(GPIO_PCH_WP); } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} - int get_ec_is_trusted(void) { /* EC is trusted if not in RW. */ diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h index 5f2c6e2..bbc5d56 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h @@ -6,7 +6,6 @@ #include <soc/gpio.h> #include <soc/meminit.h> #include <stdint.h> -#include <vendorcode/google/chromeos/chromeos.h> /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ @@ -23,8 +22,6 @@ const struct lpddr4_cfg *variant_lpddr4_config(void); /* Return memory SKU for the board. */ size_t variant_memory_sku(void); -/* Return ChromeOS gpio table and fill in number of entries. */ -const struct cros_gpio *variant_cros_gpios(size_t *num); /* Seed the NHLT tables with the board specific information. */ struct nhlt; diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 4efcb4c..dc476f9 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -51,9 +51,10 @@ CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 3c267ca..2ed2828 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h> @@ -31,15 +29,6 @@ return gpio_get(GPIO_PCH_WP); } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} - int get_ec_is_trusted(void) { /* EC is trusted if not in RW. */ diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h index 1fdc32f..9d3e7f0 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h @@ -5,7 +5,6 @@ #include <soc/gpio.h> #include <stdint.h> -#include <vendorcode/google/chromeos/chromeos.h> /* * The next set of functions return the gpio table and fill in the number of @@ -20,7 +19,6 @@ */ const struct pad_config *variant_romstage_gpio_table(size_t *num); -const struct cros_gpio *variant_cros_gpios(size_t *num); /* Config gpio by different sku id */ const struct pad_config *variant_sku_gpio_table(size_t *num); diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index d76c5e4..eae2357 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -43,9 +43,10 @@ CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 1d1c990..ca3de03 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -1,11 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <variant/gpio.h> @@ -27,15 +25,6 @@ return gpio_get(GPIO_PCH_WP); } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} - int get_ec_is_trusted(void) { /* EC is trusted if not in RW. */ diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h index 5b08c6a..c9b8b9d 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h @@ -6,7 +6,6 @@ #include <soc/gpio.h> #include <soc/meminit.h> #include <stdint.h> -#include <vendorcode/google/chromeos/chromeos.h> /* Return the sku id based off the strapping resistors attached to SoC. */ uint8_t sku_strapping_value(void); @@ -29,9 +28,6 @@ /* Set variant board sku to ec by sku id */ void variant_board_ec_set_skuid(void); -/* Return ChromeOS gpio table and fill in number of entries. */ -const struct cros_gpio *variant_cros_gpios(size_t *num); - /* Seed the NHLT tables with the board specific information. */ struct nhlt; void variant_nhlt_oem_overrides(const char **oem_id, diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 180a98e..8cdd15c 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -38,15 +38,6 @@ return !gpio_get(GPP_E8); } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *cros_gpios; - size_t num_gpios = 0; - - cros_gpios = variant_cros_gpios(&num_gpios); - - chromeos_acpi_gpio_generate(cros_gpios, num_gpios); -} int get_recovery_mode_switch(void) { diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h b/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h index f56a8b5..f56059c 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h @@ -15,7 +15,4 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); -struct cros_gpio; -const struct cros_gpio *variant_cros_gpios(size_t *num); - #endif diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h b/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h index f56a8b5..f56059c 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h @@ -15,7 +15,4 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); -struct cros_gpio; -const struct cros_gpio *variant_cros_gpios(size_t *num); - #endif diff --git a/src/mainboard/google/skyrim/chromeos.c b/src/mainboard/google/skyrim/chromeos.c index 67107d1..347e9d0 100644 --- a/src/mainboard/google/skyrim/chromeos.c +++ b/src/mainboard/google/skyrim/chromeos.c @@ -20,7 +20,8 @@ CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 634e563..9e0ab0c 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -28,9 +28,10 @@ CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 2fbddc2..2f3ae8c 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -79,7 +79,8 @@ CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c index 9b8e2f5..1b6f7ba 100644 --- a/src/mainboard/google/volteer/chromeos.c +++ b/src/mainboard/google/volteer/chromeos.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <variant/gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -26,15 +24,6 @@ return gpio_get(GPIO_PCH_WP); } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} - int get_ec_is_trusted(void) { /* EC is trusted if not in RW. */ diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h index ba4bf7f..94c39d9 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h @@ -6,7 +6,6 @@ #include <soc/gpio.h> #include <soc/meminit.h> #include <stddef.h> -#include <vendorcode/google/chromeos/chromeos.h> /* * The next set of functions return the gpio table and fill in the number of @@ -17,8 +16,6 @@ const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num); const struct pad_config *variant_override_gpio_table(size_t *num); -const struct cros_gpio *variant_cros_gpios(size_t *num); - const struct mb_cfg *variant_memory_params(void); int variant_memory_sku(void); void memcfg_variant_init(FSPM_UPD *mupd); diff --git a/src/mainboard/google/zork/chromeos.c b/src/mainboard/google/zork/chromeos.c index d649193..a975099 100644 --- a/src/mainboard/google/zork/chromeos.c +++ b/src/mainboard/google/zork/chromeos.c @@ -29,9 +29,10 @@ CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c index d7e55a9..56fbc50 100644 --- a/src/mainboard/intel/adlrvp/chromeos.c +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/gpio.h> -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -42,15 +40,6 @@ return 0; } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} - #if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) ||\ CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)) int get_ec_is_trusted(void) diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c index 62ae0f3..33b5a1d 100644 --- a/src/mainboard/intel/adlrvp/gpio_m.c +++ b/src/mainboard/intel/adlrvp/gpio_m.c @@ -2,6 +2,8 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <vendorcode/google/chromeos/chromeos.h> /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { diff --git a/src/mainboard/intel/adlrvp/gpio_n.c b/src/mainboard/intel/adlrvp/gpio_n.c index 6f4e4a5..364deac 100644 --- a/src/mainboard/intel/adlrvp/gpio_n.c +++ b/src/mainboard/intel/adlrvp/gpio_n.c @@ -3,6 +3,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> +#include <vendorcode/google/chromeos/chromeos.h> /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index 143679a..4ae1011 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -6,7 +6,6 @@ #include <soc/gpio.h> #include <soc/meminit.h> #include <stdint.h> -#include <vendorcode/google/chromeos/chromeos.h> enum adl_boardid { /* ADL-P LPDDR4 RVPs */ @@ -28,9 +27,6 @@ ADL_N_LP5 = 0x7, }; -/* The next set of functions return the gpio table and fill in the number of - * entries for each table. */ -const struct cros_gpio *variant_cros_gpios(size_t *num); /* Functions to configure GPIO as per variant schematics */ void variant_configure_gpio_pads(void); void variant_configure_early_gpio_pads(void); diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index d4408f4..05280b15 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -47,7 +47,8 @@ CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index 5c5003b..b2ea87f 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -1,13 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -35,12 +33,3 @@ /* No write protect */ return 0; } - -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h index b7a1616..6ae25d4 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h @@ -5,7 +5,6 @@ #include <soc/cnl_memcfg_init.h> #include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ @@ -13,8 +12,6 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); -const struct cros_gpio *variant_cros_gpios(size_t *num); - /* Return memory configuration structure. */ const struct cnl_mb_cfg *variant_memcfg_config(void); diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 2d0e2e1..621ecfd 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -44,7 +44,8 @@ CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 7a14c86..bc27b27 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <variant/gpio.h> @@ -26,15 +24,6 @@ return 0; } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} - int __weak get_lid_switch(void) { return -1; diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h index f1df937..24c28f9 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h @@ -5,7 +5,6 @@ #include <soc/gpio.h> #include <soc/meminit.h> -#include <vendorcode/google/chromeos/chromeos.h> /** * variant_board_id() - Get the board id for the current board variant @@ -27,9 +26,6 @@ /* Return memory SKU for the board. */ size_t variant_memory_sku(void); -/* Return ChromeOS gpio table and fill in number of entries. */ -const struct cros_gpio *variant_cros_gpios(size_t *num); - /* Seed the NHLT tables with the board specific information. */ struct nhlt; void variant_nhlt_init(struct nhlt *nhlt); diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index 6df26af..2b1f9af 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -2,12 +2,10 @@ #include <acpi/acpi.h> #include <baseboard/gpio.h> -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -35,12 +33,3 @@ /* No write protect */ return 0; } - -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h index ccbadca..48d6c1c 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h @@ -4,13 +4,11 @@ #define __BASEBOARD_VARIANTS_H__ #include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); -const struct cros_gpio *variant_cros_gpios(size_t *num); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c index bf9a7bf..ef0d7ec 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.c +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/gpio.h> -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -37,12 +35,3 @@ /* No write protect */ return 0; } - -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h index e2e331a..120833f 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h @@ -6,7 +6,6 @@ #include <soc/gpio.h> #include <soc/meminit.h> #include <stdint.h> -#include <vendorcode/google/chromeos/chromeos.h> enum jsl_board_id { jsl_ddr4 = 1, @@ -18,7 +17,6 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); -const struct cros_gpio *variant_cros_gpios(size_t *num); const struct mb_cfg *variant_memcfg_config(uint8_t board_id); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index afc27cd..f64f5bd 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -60,9 +60,10 @@ CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 87a0e01..2bb59fb 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -31,9 +31,10 @@ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } int get_ec_is_trusted(void) diff --git a/src/mainboard/intel/shadowmountain/chromeos.c b/src/mainboard/intel/shadowmountain/chromeos.c index 0858754..1e7c7d9 100644 --- a/src/mainboard/intel/shadowmountain/chromeos.c +++ b/src/mainboard/intel/shadowmountain/chromeos.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/gpio.h> -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -26,15 +24,6 @@ return gpio_get(GPIO_PCH_WP); } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} - int get_ec_is_trusted(void) { /* EC is trusted if not in RW. */ diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h index a145ac9..e8886d9 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h @@ -6,7 +6,6 @@ #include <soc/gpio.h> #include <soc/meminit.h> #include <stddef.h> -#include <vendorcode/google/chromeos/chromeos.h> /* * The next set of functions return the gpio table and fill in the number of @@ -14,7 +13,6 @@ */ const struct pad_config *variant_base_gpio_table(size_t *num); const struct pad_config *variant_override_gpio_table(size_t *num); -const struct cros_gpio *variant_cros_gpios(size_t *num); void variant_configure_early_gpio_pads(void); diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 91ce9ae..a6a0af2 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -38,7 +38,8 @@ CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index dd6c666..779c9a0 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/gpio.h> -#include <baseboard/variants.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> #include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) { @@ -39,15 +37,6 @@ return 0; } -void mainboard_chromeos_acpi_generate(void) -{ - const struct cros_gpio *gpios; - size_t num; - - gpios = variant_cros_gpios(&num); - chromeos_acpi_gpio_generate(gpios, num); -} - int get_ec_is_trusted(void) { /* Do not have a Chrome EC involved in entering recovery mode; diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h index fbb86f7..45ae15e 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h @@ -5,14 +5,12 @@ #include <soc/gpio.h> #include <soc/meminit.h> -#include <vendorcode/google/chromeos/chromeos.h> /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); -const struct cros_gpio *variant_cros_gpios(size_t *num); size_t variant_memory_sku(void); const struct mb_cfg *variant_memory_params(void); diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 5e01910..49da437 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -36,7 +36,8 @@ CROS_GPIO_WP_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index f8b0afc..e5c8d30 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -90,7 +90,8 @@ CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index b845a91..95801c1 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -83,7 +83,8 @@ CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; -void mainboard_chromeos_acpi_generate(void) +const struct cros_gpio *variant_cros_gpios(size_t *num) { - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; } diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c index 5a54d70..383cd31 100644 --- a/src/vendorcode/google/chromeos/acpi.c +++ b/src/vendorcode/google/chromeos/acpi.c @@ -6,11 +6,16 @@ #endif #include "chromeos.h" -void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num) +void chromeos_acpi_gpio_generate(void) { - size_t i; + const struct cros_gpio *gpios; + size_t i, num; int gpio_num; + gpios = variant_cros_gpios(&num); + if (!gpios) + return; + acpigen_write_scope("\\"); acpigen_write_name("OIPG"); diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index da25617..34a9f57 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -38,16 +38,9 @@ enum cb_err get_dsm_calibration_from_key(const char *key, uint64_t *value); /* - * Create the OIPG package containing the Chrome OS gpios described by - * the chromeos_gpio array. - */ -struct cros_gpio; -void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num); - -/* * Declaration for mainboards to use to generate ACPI-specific Chrome OS needs. */ -void mainboard_chromeos_acpi_generate(void); +void chromeos_acpi_gpio_generate(void); enum { CROS_GPIO_REC = 1, /* Recovery */ @@ -104,4 +97,6 @@ #define CROS_GPIO_PE_AH(num, dev) \ CROS_GPIO_PE_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev) +const struct cros_gpio *variant_cros_gpios(size_t *num); + #endif /* __CHROMEOS_H__ */ diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 33389b4e..faaa646 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -98,6 +98,5 @@ acpigen_write_opregion(&cnvs_op); acpigen_pop_len(); - /* Usually this creates OIPG package for GPIOs. */ - mainboard_chromeos_acpi_generate(); + chromeos_acpi_gpio_generate(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/58897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Gerrit-Change-Number: 58897 Gerrit-PatchSet: 18 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE
by Felix Held (Code Review) 06 Apr '22

06 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62843 ) Change subject: soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE ...................................................................... soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODE The patch SOC_INTEL_COMMON_BASECODE Kconfig for Comet Lake, Jasper Lake and Tiger Lake SoCs. It allows access to intelbasecode/debug_feature.h for Comet Lake, Jasper Lake and Tiger Lake SoCs. TEST=Build code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ie55ded673c8fa0edf2ca6789b15771bd2e56c95e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62843 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/tigerlake/Kconfig 3 files changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 0a61381..ddb1619 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -26,6 +26,7 @@ select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_CONFIGURE_DDI_A_4_LANES select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT + select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU config SOC_INTEL_COMETLAKE_1 bool diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index e0e0c7b..53b0201 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -69,6 +69,7 @@ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 265aa5f..c0cf683 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -88,6 +88,7 @@ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU config MAX_CPUS int -- To view, visit https://review.coreboot.org/c/coreboot/+/62843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie55ded673c8fa0edf2ca6789b15771bd2e56c95e Gerrit-Change-Number: 62843 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)gmail.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/brya: Enable dynamic debug capability for brya family
by Felix Held (Code Review) 06 Apr '22

06 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61381 ) Change subject: mb/google/brya: Enable dynamic debug capability for brya family ...................................................................... mb/google/brya: Enable dynamic debug capability for brya family The patch enables dynamic debug capability for Brya family of boards. BRANCH=MAIN BUG=b:153410586 TEST= Verified the CSE firmware update functionality on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I51b0e0bb4392d3fbdb50577d3644491ab90a33c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61381 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index b501754..1fb90c9 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -36,6 +36,7 @@ select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES if SOC_INTEL_ALDERLAKE_PCH_P + select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE config BOARD_GOOGLE_BASEBOARD_BRYA def_bool n 15 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51b0e0bb4392d3fbdb50577d3644491ab90a33c3 Gerrit-Change-Number: 61381 Gerrit-PatchSet: 18 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2022