coreboot-gerrit April 2022

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Change in coreboot[master]: MAINTAINERS: lower maintenance level of super I/O and superiotool
by Raul Rangel (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Angel Pons, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63417 ) Change subject: MAINTAINERS: lower maintenance level of super I/O and superiotool ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7bd3c68c1adc0db82dab078291918742b453d4c Gerrit-Change-Number: 63417 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 06 Apr 2022 19:52:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: MAINTAINERS: lower maintenance level of super I/O and superiotool
by Felix Held (Code Review) 06 Apr '22

06 Apr '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63417 ) Change subject: MAINTAINERS: lower maintenance level of super I/O and superiotool ...................................................................... MAINTAINERS: lower maintenance level of super I/O and superiotool I don't really get around to review super I/O or superiotool patches any more, so lower the maintenance level of those. If anyone else wants to step up as new maintainer for those two, feel free to do so. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id7bd3c68c1adc0db82dab078291918742b453d4c --- M MAINTAINERS 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/63417/1 diff --git a/MAINTAINERS b/MAINTAINERS index 930d37e..3181ef3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -880,7 +880,7 @@ SUPERIOS & SUPERIOTOOL M: Felix Held <felix-coreboot(a)felixheld.de> -S: Maintained +S: Odd Fixes F: src/superio/ F: util/superiotool/ -- To view, visit https://review.coreboot.org/c/coreboot/+/63417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7bd3c68c1adc0db82dab078291918742b453d4c Gerrit-Change-Number: 63417 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/taniks: Enable Genesys L1 max entry delay
by Tim Wawrzynczak (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: YH Lin, Joey Peng. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63131 ) Change subject: mb/google/brya/var/taniks: Enable Genesys L1 max entry delay ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a5888e943c1ebf83a54f9b172f986f8b13d9b6a Gerrit-Change-Number: 63131 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 19:18:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Update CSE sub partition update
by Tim Wawrzynczak (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Subrata Banik, Paul Menzel, Sridhar Siricilla, Kane Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63169 ) Change subject: soc/intel/common: Update CSE sub partition update ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629 Gerrit-Change-Number: 63169 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 19:18:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/acpi_bert_storage.c: Use BOOT_STATE over CBMEM hooks
by Arthur Heymans (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63415 ) Change subject: arch/x86/acpi_bert_storage.c: Use BOOT_STATE over CBMEM hooks ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: All the remaining RAMSTAGE_CBMEM hooks are about recovering data from romstage. So it's safe to skip those when linking ramstage in the bootblock. -- To view, visit https://review.coreboot.org/c/coreboot/+/63415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I317173d468073906d76228d1c8cc7bc28aae9e75 Gerrit-Change-Number: 63415 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 18:54:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/acpi_bert_storage.c: Use BOOT_STATE over CBMEM hooks
by Arthur Heymans (Code Review) 06 Apr '22

06 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63415 ) Change subject: arch/x86/acpi_bert_storage.c: Use BOOT_STATE over CBMEM hooks ...................................................................... arch/x86/acpi_bert_storage.c: Use BOOT_STATE over CBMEM hooks With the purpose of linking ramstage inside the bootblock we likely want to skip some ramstage CBMEM hooks and keep those only for recovering data from earlier stages. Change-Id: I317173d468073906d76228d1c8cc7bc28aae9e75 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/acpi_bert_storage.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/63415/1 diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index 8559c06..7b6b63b 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <cpu/x86/name.h> @@ -577,7 +578,7 @@ *size = 0; } -static void bert_storage_setup(int unused) +static void bert_storage_setup(void *unused) { /* Always start with a blank bert region. Make sure nothing is * maintained across reboots or resumes. @@ -596,4 +597,4 @@ memset(bert_region_base, 0, bert_region_size); } -RAMSTAGE_CBMEM_INIT_HOOK(bert_storage_setup) +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, bert_storage_setup, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/63415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I317173d468073906d76228d1c8cc7bc28aae9e75 Gerrit-Change-Number: 63415 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/hardwaremain.c: Move creating ACPI structs to bootstate hooks
by Arthur Heymans (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63414 ) Change subject: lib/hardwaremain.c: Move creating ACPI structs to bootstate hooks ...................................................................... lib/hardwaremain.c: Move creating ACPI structs to bootstate hooks Change-Id: I613b927b9a193fc076ffb1b2a40c617965ce2645 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/acpi/gnvs.c M src/include/acpi/acpi_gnvs.h M src/lib/hardwaremain.c M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/gnvs.c 5 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/63414/1 diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c index 6de345f..ad20c92 100644 --- a/src/acpi/gnvs.c +++ b/src/acpi/gnvs.c @@ -2,6 +2,7 @@ #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> +#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <soc/nvs.h> @@ -11,8 +12,11 @@ static struct global_nvs *gnvs; static void *dnvs; -void acpi_create_gnvs(void) +static void acpi_create_gnvs(void *unused) { + if (!CONFIG(ACPI_SOC_NVS)) + return; + const size_t gnvs_size = ALIGN_UP(sizeof(struct global_nvs), sizeof(uint64_t)); const size_t dnvs_size = ALIGN_UP(size_of_dnvs(), sizeof(uint64_t)); @@ -34,6 +38,8 @@ gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); } +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, acpi_create_gnvs, NULL); + void *acpi_get_gnvs(void) { if (gnvs) diff --git a/src/include/acpi/acpi_gnvs.h b/src/include/acpi/acpi_gnvs.h index ef98b66..ef6ec29 100644 --- a/src/include/acpi/acpi_gnvs.h +++ b/src/include/acpi/acpi_gnvs.h @@ -7,7 +7,6 @@ struct global_nvs; -void acpi_create_gnvs(void); size_t size_of_dnvs(void); #if CONFIG(ACPI_SOC_NVS) diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 84f3e9b..1f5bd09 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -460,13 +460,6 @@ timestamp_add_now(TS_RAMSTAGE_START); post_code(POST_ENTRY_HARDWAREMAIN); - /* Initialise GNVS early. */ - if (CONFIG(ACPI_SOC_NVS)) - acpi_create_gnvs(); - - if (CONFIG(CHROMEOS_NVS)) - chromeos_init_chromeos_acpi(); - /* Schedule the static boot state entries. */ boot_state_schedule_static_entries(); diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index abdd6c2..f3b8b07 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -26,7 +26,6 @@ void chromeos_set_me_hash(u32*, int); void chromeos_set_ramoops(void *ram_oops, size_t size); void chromeos_set_ecfw_rw(void); -void chromeos_init_chromeos_acpi(void); /** * get_dsm_calibration_from_key - Gets value related to DSM calibration from VPD diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 7821786..733aa65 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <acpi/acpigen.h> +#include <bootstate.h> #include <types.h> #include <string.h> #include <stdlib.h> @@ -31,7 +32,7 @@ return region_device_sz(&vpd); } -void chromeos_init_chromeos_acpi(void) +void chromeos_init_chromeos_acpi(void *unused) { size_t vpd_size; uintptr_t vpd_base = 0; @@ -63,6 +64,8 @@ chromeos_acpi->vbt2 = ACTIVE_ECFW_RW; } +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, chromeos_init_chromeos_acpi, NULL); + void chromeos_set_me_hash(u32 *hash, int len) { if ((len*sizeof(u32)) > sizeof(chromeos_acpi->mehh)) -- To view, visit https://review.coreboot.org/c/coreboot/+/63414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I613b927b9a193fc076ffb1b2a40c617965ce2645 Gerrit-Change-Number: 63414 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: hardwaremain.c: Drop checking the S3 resume
by Arthur Heymans (Code Review) 06 Apr '22

06 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63413 ) Change subject: hardwaremain.c: Drop checking the S3 resume ...................................................................... hardwaremain.c: Drop checking the S3 resume It's not needed to do this early in ramstage and on non-x86 it's even meaningless as those platforms don't have S3. Change-Id: I4a8a7b3c5e347e111eae09e019cf2cfba79545fa Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/lib/hardwaremain.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/63413/1 diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index b5ed6e0..84f3e9b 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -460,9 +460,6 @@ timestamp_add_now(TS_RAMSTAGE_START); post_code(POST_ENTRY_HARDWAREMAIN); - /* Handoff sleep type from romstage. */ - acpi_is_wakeup_s3(); - /* Initialise GNVS early. */ if (CONFIG(ACPI_SOC_NVS)) acpi_create_gnvs(); -- To view, visit https://review.coreboot.org/c/coreboot/+/63413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a8a7b3c5e347e111eae09e019cf2cfba79545fa Gerrit-Change-Number: 63413 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUG
by build bot (Jenkins) (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Tim Wawrzynczak, Arthur Heymans, Nick Vaccaro, Eric Lai. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63167 ) Change subject: soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUG ...................................................................... Patch Set 5: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I779c56b8b0fdebf45ea85b3b456a2d8066e26489 Gerrit-Change-Number: 63167 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 18:51:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Allow coreboot to control FSP serial redirection
by Subrata Banik (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Arthur Heymans, Lean Sheng Tan, Michael Niewöhner, Andrey Petrov. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Arthur Heymans, Eric Lai, Lean Sheng Tan, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63166 to look at the new patch set (#3). Change subject: drivers/intel/fsp2_0: Allow coreboot to control FSP serial redirection ...................................................................... drivers/intel/fsp2_0: Allow coreboot to control FSP serial redirection Commit 3ba6f8cdf (drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler) implements a native FSP debug handler. However, coreboot still can't control when to redirect FSP debug output to the serial console, i.e., at present, integrating a FSP debug binary is enough to output FSP serial messages irrespective of whether user is intended to see FSP debug log. coreboot needs additional mechanism to control FSP debug binary to redirect debug messages over serial port. This patch introduces a config `FSP_ENABLE_SERIAL_DEBUG` to control the FSP debug output, user to enable this config from site-local config file in case like to override the default FSP serial redirection behaviour in more controlled way from coreboot. There could be scenarios as below: Scenario 1: coreboot release image integrated with the FSP debug binaries, is capable of redirecting to the serial console, but coreboot decides to override the config as below to skip FSP debug output redirection to the serial port. `#`FSP Serial console disabled by default (do not remove) `#`CONFIG_FSP_ENABLE_SERIAL_DEBUG is not set Scenario 2: For coreboot serial image with FSP debug binaries integrated but coreboot decides to skip FSP debug output redirection to the serial port. `#`FSP Serial console disabled by default (do not remove) `#`CONFIG_FSP_ENABLE_SERIAL_DEBUG is not set CONFIG_CONSOLE_SERIAL=y CONFIG_CONSOLE_SERIAL_115200=y CONFIG_UART_DEBUG=y CONFIG_UART_FOR_CONSOLE=0 Scenario 3: The final image could be a coreboot serial image with FSP serial redirection enabled to output to the serial port. CONFIG_FSP_ENABLE_SERIAL_DEBUG=y CONFIG_CONSOLE_SERIAL=y CONFIG_CONSOLE_SERIAL_115200=y CONFIG_UART_DEBUG=y CONFIG_UART_FOR_CONSOLE=0 BUG=b:227151510 TEST=Able to build and boot google/redrix with all scenarios between #1--#3 and able to meet the expectation as mentioned above. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I0b008ca9d4f40bfa6a989a6fd655c234f91fde65 --- M src/drivers/intel/fsp2_0/Kconfig 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/63166/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b008ca9d4f40bfa6a989a6fd655c234f91fde65 Gerrit-Change-Number: 63166 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2022