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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55066 )
Change subject: drivers/amd/agesa/romstage.c: Move timestamp and console init up
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55066/comment/06f16abc_4b6d8b25
PS1, Line 8:
> > Immediate follow-up removes them from this file to common romstage. […]
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/55066/comment/2a720cee_fe0113ad
PS2, Line 7: intel
> Ping
Done
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Hello build bot (Jenkins), Paul Menzel, Angel Pons, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
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Change subject: drivers/amd/agesa/romstage.c: Move timestamp and console init up
......................................................................
drivers/amd/agesa/romstage.c: Move timestamp and console init up
Change-Id: I26a37f9384a581a8a750efccc2100a5c6a6f0f85
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/drivers/amd/agesa/romstage.c
1 file changed, 5 insertions(+), 5 deletions(-)
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55070
to look at the new patch set (#9).
Change subject: link Agesa into bootblock
......................................................................
link Agesa into bootblock
For AGESA targets the APs are started by the BSP in romstage and need
to jump past the bootblock into the romstage. When there is a separate
romstage this is complicated as the APs in boot need to know where
to jump in romstage. This is done by setting a pointer in BIOSRAM.
When the romstage is linked inside the bootblock there is no need for
such tricks as the symbol for the AP jump address can directly be
referenced.
Change-Id: Ic4c71b9c9a245e07d713839fb3628cbfc0dc3457
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/Kconfig
M src/arch/x86/bootblock.ld
M src/arch/x86/car.ld
M src/cpu/amd/agesa/Kconfig
M src/drivers/amd/agesa/bootblock.c
M src/drivers/amd/agesa/romstage.c
M src/northbridge/amd/agesa/agesa_helper.h
M src/vendorcode/amd/agesa/Makefile.inc
8 files changed, 28 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/55070/9
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Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Philipp Hug, ron minnich, Stefan Reinauer, Subrata Banik, Julius Werner, Andrey Petrov, Aaron Durbin, Patrick Rudolph, Piotr Król, Jason Glenesk, Michał Żygowski, Martin Roth, Marshall Dawson, ron minnich, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: Allow to build romstage sources inside the bootblock
......................................................................
Allow to build romstage sources inside the bootblock
Having a separate romstage is only desirable:
- with advanced setups like vboot or normal/fallback
- boot medium is slow at startup (some ARM SOCs)
- bootblock is limited in size (Intel APL 32K)
When this is not the case there is no need for the extra complexity
that romstage brings. Including the romstage sources inside the
bootblock substantially reduces the total code footprint. Often the
resulting code is 10-20k smaller.
TESTED: works on qemu x86, arm and aarch64.
Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.inc
M src/Kconfig
M src/arch/arm64/romstage.c
M src/arch/x86/Makefile.inc
M src/include/rules.h
M src/lib/prog_loaders.c
M src/mainboard/emulation/qemu-armv7/romstage.c
7 files changed, 26 insertions(+), 5 deletions(-)
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Change subject: arch/x86: Add a common romstage entry
......................................................................
arch/x86: Add a common romstage entry
It might be possible to have this used for more than x86, but that
will be for a later commit.
Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/Makefile.inc
A src/arch/x86/romstage.c
M src/cpu/intel/car/romstage.c
M src/drivers/amd/agesa/romstage.c
A src/include/romstage_common.h
M src/soc/amd/cezanne/romstage.c
M src/soc/amd/picasso/romstage.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/example/min86/romstage.c
9 files changed, 42 insertions(+), 45 deletions(-)
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Change subject: Allow to build romstage sources inside the bootblock
......................................................................
Patch Set 9:
(1 comment)
File src/include/rules.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145581):
https://review.coreboot.org/c/coreboot/+/55068/comment/42d82005_0ed0359f
PS9, Line 313: #define ENV_FIRST_CBMEM_STAGE (CONFIG(SEPARATE_ROMSTAGE) ? ENV_ROMSTAGE : ENV_BOOTBLOCK)
line over 96 characters
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Change subject: arch/x86: Add a common romstage entry
......................................................................
Patch Set 7:
(3 comments)
File src/arch/x86/romstage.c:
https://review.coreboot.org/c/coreboot/+/55067/comment/6ba17d01_1907e636
PS5, Line 8: /* Provide an entry point for verstage when it's a separate stage. */
> verstage?
Done
File src/soc/amd/cezanne/romstage.c:
https://review.coreboot.org/c/coreboot/+/55067/comment/ab33138f_ebe3a7da
PS5, Line 4: #include <acpi/acpi.h>
: #include <amdblocks/acpimmio.h>
: #include <amdblocks/memmap.h>
: #include <amdblocks/pmlib.h>
: #include <arch/cpu.h>
: #include <console/console.h>
: #include <fsp/api.h>
: #include <program_loading.h>
: #include <timestamp.h>
> Looks like these includes are sorted alphabetically. […]
Done
https://review.coreboot.org/c/coreboot/+/55067/comment/b3e9b833_ce3c8bec
PS5, Line 16: timestamp_add_now(TS_START_ROMSTAGE);
> This needs to be removed
Done
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I'd like you to reexamine a change. Please visit
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Change subject: arch/x86: Add a common romstage entry
......................................................................
arch/x86: Add a common romstage entry
It might be possible to have this used for more than x86, but that
will be for a later commit.
Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/Makefile.inc
A src/arch/x86/romstage.c
M src/cpu/intel/car/romstage.c
M src/drivers/amd/agesa/romstage.c
A src/include/romstage_common.h
M src/soc/amd/cezanne/romstage.c
M src/soc/amd/picasso/romstage.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/example/min86/romstage.c
9 files changed, 37 insertions(+), 44 deletions(-)
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Change subject: soc/amd/non_car/memlayout_x86.ld: Top align the bootblock
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55796/comment/20417c29_c7ed01c1
PS2, Line 7: aling
> align
Done
File src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld:
https://review.coreboot.org/c/coreboot/+/55796/comment/efc6ac8e_68b4c6cd
PS1, Line 124: 64
> > Why the extra 64? […]
Done
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