coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/alderlake: Enable debug driver for Alder Lake platform
by Felix Held (Code Review) 06 Apr '22

06 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62652 ) Change subject: soc/intel/alderlake: Enable debug driver for Alder Lake platform ...................................................................... soc/intel/alderlake: Enable debug driver for Alder Lake platform The patch enables dynamic debug capability driver for Alder Lake platform. BUG=b:153410586 TEST= Build code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ic4df3d7f3d6585bd37c632b1a3f0a47c94b63697 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62652 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/romstage/romstage.c 2 files changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 3570f27..6b0a27a 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -98,6 +98,7 @@ select SOC_INTEL_COMMON_BLOCK_USB4_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG + select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 5e79535..3f29fc3 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -9,6 +9,7 @@ #include <intelblocks/pmclib.h> #include <intelblocks/smbus.h> #include <intelblocks/thermal.h> +#include <intelbasecode/debug_feature.h> #include <memory_info.h> #include <soc/intel/common/smbios.h> #include <soc/iomap.h> @@ -134,6 +135,9 @@ /* Initialize HECI interface */ heci_init(HECI1_BASE_ADDRESS); + if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE)) + pre_mem_debug_init(); + s3wake = pmc_fill_power_state(ps) == ACPI_S3; if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) { 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4df3d7f3d6585bd37c632b1a3f0a47c94b63697 Gerrit-Change-Number: 62652 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Add support to control coreboot and Intel SoC features
by Felix Held (Code Review) 06 Apr '22

06 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/intel/common: Add support to control coreboot and Intel SoC features ...................................................................... soc/intel/common: Add support to control coreboot and Intel SoC features The patch adds a framework to control coreboot and Intel SoC features dynamically. BIOS reads control information from OEM Section in the Descriptor Region and control the developer selected features. With the feature, debug team can control the selected SoC and coreboot features without rebuilding coreboot. In order to enable the feature, SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE has to be selcted from mainboard. The OEM section starts from offset:0xf00 till end of the Descriptor Region(0xfff). BUG=b:153410586 BRANCH=None TEST=Verified CSE firmware update functionality on brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61380 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/common/basecode/Kconfig A src/soc/intel/common/basecode/debug/Kconfig A src/soc/intel/common/basecode/debug/Makefile.inc A src/soc/intel/common/basecode/debug/debug_feature.c A src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h 5 files changed, 71 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Maulik V Vaghela: Looks good to me, approved Ronak Kanabar: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/basecode/Kconfig b/src/soc/intel/common/basecode/Kconfig index 9e0f788..9730985 100644 --- a/src/soc/intel/common/basecode/Kconfig +++ b/src/soc/intel/common/basecode/Kconfig @@ -2,3 +2,9 @@ bool help Common coreboot stages and non-IP block for Intel platform + +if SOC_INTEL_COMMON_BASECODE + +source "src/soc/intel/common/basecode/*/Kconfig" + +endif diff --git a/src/soc/intel/common/basecode/debug/Kconfig b/src/soc/intel/common/basecode/debug/Kconfig new file mode 100644 index 0000000..f72055b --- /dev/null +++ b/src/soc/intel/common/basecode/debug/Kconfig @@ -0,0 +1,6 @@ +config SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE + bool + default n + help + Driver to control runtime features of Intel SoC & coreboot. For example, controlling + the CSE firmware update feature without rebuilding the code. diff --git a/src/soc/intel/common/basecode/debug/Makefile.inc b/src/soc/intel/common/basecode/debug/Makefile.inc new file mode 100644 index 0000000..f783c8d --- /dev/null +++ b/src/soc/intel/common/basecode/debug/Makefile.inc @@ -0,0 +1 @@ +romstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE) += debug_feature.c diff --git a/src/soc/intel/common/basecode/debug/debug_feature.c b/src/soc/intel/common/basecode/debug/debug_feature.c new file mode 100644 index 0000000..5cdbaf7 --- /dev/null +++ b/src/soc/intel/common/basecode/debug/debug_feature.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <boot_device.h> +#include <commonlib/region.h> +#include <intelbasecode/debug_feature.h> +#include <console/console.h> +#include <fmap.h> + +#define SI_DESC_OEM_SECTION_OFFSET 0xF00 +#define PRE_MEM_FEATURE_CTRL_OFFSET SI_DESC_OEM_SECTION_OFFSET +#define PRE_MEM_FEATURE_CTRL_SZ 64 +#define SI_DESC_REGION_SZ 4096 + +struct pre_mem_ft { + uint8_t reserved[64]; +}; + +static struct pre_mem_ft pre_mem_debug; + +_Static_assert(sizeof(struct pre_mem_ft) % 64 == 0 && sizeof(struct pre_mem_ft) <= 256, + "sizeof(struct pre_mem_ft) must be a multiple of 64 bytes and up to 256 bytes"); + +uint8_t pre_mem_debug_init(void) +{ + struct region_device desc_rdev; + const struct region_device *boot_device = boot_device_ro(); + + if (!boot_device) { + printk(BIOS_ERR, "Failed to get RW boot device\n"); + return 1; + } + + if (rdev_chain(&desc_rdev, boot_device, 0, SI_DESC_REGION_SZ)) { + printk(BIOS_ERR, "Failed to get description region device\n"); + return 1; + } + + if (rdev_readat(&desc_rdev, &pre_mem_debug, PRE_MEM_FEATURE_CTRL_OFFSET, + PRE_MEM_FEATURE_CTRL_SZ) != PRE_MEM_FEATURE_CTRL_SZ) { + printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); + return 1; + } + return 0; +} diff --git a/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h b/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h new file mode 100644 index 0000000..fabf27d --- /dev/null +++ b/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE_H +#define SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE_H + +#include <types.h> + +/* + * Reads OEM Section area in the Descriptor Region and + * populates pre_mem_debug structure. + */ +uint8_t pre_mem_debug_init(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 18 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Add support to control coreboot and Intel SoC features
by Felix Held (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Nico Huber, Subrata Banik, Sridhar Siricilla, Arthur Heymans, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/intel/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 17: (1 comment) File src/soc/intel/common/basecode/debug/debug_feature.c: https://review.coreboot.org/c/coreboot/+/61380/comment/9ddc4d0d_f9fda44e PS17, Line 23: uint8_t > I will let this patch train get up streamed first. I will push separate CL to use cb_err. sounds good to me -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 17 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 06 Apr 2022 17:32:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add support to control coreboot and Intel SoC features
by Sridhar Siricilla (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Nico Huber, Subrata Banik, Arthur Heymans, Patrick Rudolph, Felix Held. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/intel/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 17: (1 comment) File src/soc/intel/common/basecode/debug/debug_feature.c: https://review.coreboot.org/c/coreboot/+/61380/comment/f493f50e_c1417876 PS17, Line 23: uint8_t > i'd use enum cb_err instead of uint8_t as return value and return CB_SUCCESS/CB_ERR I will let this patch train get up streamed first. I will push separate CL to use cb_err. -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 17 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 06 Apr 2022 16:59:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add support for UFS controller
by Lean Sheng Tan (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Subrata Banik, Wonkyu Kim, Kangheui Won, Tim Wawrzynczak, Paul Menzel, Rizwan Qureshi, Meera Ravindranath, Angel Pons, Eric Lai. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62856 ) Change subject: soc/intel/alderlake: Add support for UFS controller ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4 Gerrit-Change-Number: 62856 Gerrit-PatchSet: 7 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 16:42:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add support for UFS controller
by Meera Ravindranath (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Subrata Banik, Wonkyu Kim, Kangheui Won, Tim Wawrzynczak, Paul Menzel, Rizwan Qureshi, Angel Pons, Lean Sheng Tan, Eric Lai. Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62856 ) Change subject: soc/intel/alderlake: Add support for UFS controller ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/62856/comment/6def8631_7d2604d0 PS6, Line 641: s_cfg->UfsEnable[0] = 0; /* UFS Controller 0 is fuse disabled */ > Oh yeah that is right, UFS is working for ADL-P too, will need to move this out of ADL-N kconfig Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4 Gerrit-Change-Number: 62856 Gerrit-PatchSet: 7 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 16:42:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add support for UFS controller
by Meera Ravindranath (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Subrata Banik, Wonkyu Kim, Kangheui Won, Tim Wawrzynczak, Paul Menzel, Rizwan Qureshi, Meera Ravindranath, Angel Pons, Eric Lai. Hello build bot (Jenkins), Kangheui Won, Tim Wawrzynczak, Rizwan Qureshi, Angel Pons, Eric Lai, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62856 to look at the new patch set (#7). Change subject: soc/intel/alderlake: Add support for UFS controller ...................................................................... soc/intel/alderlake: Add support for UFS controller UFS (Universal Flash Storage) is the next generation storage standard and a SCSI storage technology. It is also a successor of eMMC. Following changes are needed to add support for UFS - 1) Add UFS controller to chipset.cb and keep it off by default 2) Hook up FSP enable UPD for UFS #1 to the device from chipset.cb Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4 --- M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/fsp_params.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/62856/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/62856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4 Gerrit-Change-Number: 62856 Gerrit-PatchSet: 7 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: superiotool/ite: add IT8625E EC registers
by Felix Held (Code Review) 06 Apr '22

06 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63310 ) Change subject: superiotool/ite: add IT8625E EC registers ...................................................................... superiotool/ite: add IT8625E EC registers Add support for dumping ITE IT8625E Environmental Controller registers. Values as per "IT8625E Preliminary Specification V0.3 (For D Version)". Change-Id: I68aad90097206c6b8ef40075530c00809d9511e2 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63310 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M util/superiotool/ite.c 1 file changed, 37 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, but someone else must approve Michał Żygowski: Looks good to me, approved diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index 9b29ceb..31fc496 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -1325,6 +1325,43 @@ 0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x0f,NANA,NANA,NANA, NANA,NANA,NANA,EOT}}, {EOT}}}, + {0x8625, "IT8625E", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, + 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, + 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x1e,0x1f,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,0x30,0x31,0x32, + 0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3a,0x3b,0x3c, + 0x3d,0x3e,0x3f,0x40,0x41,0x42,0x43,0x44,0x45,0x46, + 0x47,0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58, + 0x59,0x5a,0x5b,0x5c,0x5d,0x5e,0x5f,0x60,0x61,0x62, + 0x63,0x64,0x65,0x66,0x68,0x69,0x6a,0x6b,0x6c,0x6d, + 0x6e,0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x78,0x79, + 0x7a,0x7b,0x7c,0x7d,0x7e,0x80,0x81,0x82,0x83,0x84, + 0x85,0x86,0x87,0x88,0x89,0x8a,0x8b,0x8c,0x8d,0x8e, + 0x8f,0x90,0x91,0x92,0x93,0x94,0x98,0x99,0x9c,0x9d, + 0x9e,0x9f,0xa0,0xa1,0xa2,0xa3,0xa4,0xa5,0xa6,0xa8, + 0xa9,0xaa,0xab,0xac,0xad,0xae,0xb2,0xb3,0xb4,0xb5, + 0xb6,0xb7,0xb8,0xb9,EOT}, + {0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0, + 0x44,0x00,0x00,NANA,NANA,NANA,NANA,NANA,NANA,0x00, + 0x40,0x00,0x00,0x00,NANA,NANA,NANA,NANA,NANA,NANA, + 0x00,0x00,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,0x00,0x00,0x7f,0x7f,0x7f,0x40,0x00,0x00,0x90, + 0x00,0x00,0x12,0x60,0x00,0x00,0x00,0x7f,0x7f,0x7f, + 0x00,0x00,0x7f,0x0f,0x7f,0x7f,0x7f,0x00,0x00,0x7f, + 0x0f,0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x0f,0x7f,0x7f, + 0x7f,0x00,0x00,0x7f,0x0f,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + NANA,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0x00,NANA, + 0x00,NANA,0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x0f,0x7f, + 0x7f,0x7f,0x00,0x00,0x7f,0x0f,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,EOT}}, + {EOT}}}, {0x8716, "IT8716F", { {NOLDN, NULL, {0x00,0x04,0x05,0x06,0x07,0x08,0x09,0x0b,0x0c,0x10, 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68aad90097206c6b8ef40075530c00809d9511e2 Gerrit-Change-Number: 63310 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/starlabs/merlin: Add EC related files for Cezanne boards
by Felix Held (Code Review) 06 Apr '22

06 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62994 ) Change subject: ec/starlabs/merlin: Add EC related files for Cezanne boards ...................................................................... ec/starlabs/merlin: Add EC related files for Cezanne boards Add EC memory layout and Q events for AMD Cezanne based boards, "Byte" and "Fighter", which both use the ITE 5570E. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I3f837263d24e6b642cf33fd2995d8c90529706f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62994 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/ec/starlabs/merlin/variants/cezanne/ecdefs.h A src/ec/starlabs/merlin/variants/cezanne/emem.asl A src/ec/starlabs/merlin/variants/cezanne/events.asl 3 files changed, 363 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h b/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h new file mode 100644 index 0000000..a75720e --- /dev/null +++ b/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * EC communication interface for ITE Embedded Controller + */ + +#ifndef _EC_STARLABS_CEZANNE_EC_DEFS_H +#define _EC_STARLABS_CEZANNE_EC_DEFS_H + +/* IT5570 chip ID byte values */ +#define ITE_CHIPID_VAL 0x5570 + +/* EC RAM offsets */ +#define ECRAM_KBL_BRIGHTNESS 0x09 +#define ECRAM_KBL_TIMEOUT 0x10 +#define ECRAM_KBL_STATE 0x19 +#define ECRAM_TRACKPAD_STATE 0x20 +#define ECRAM_FN_LOCK_STATE 0x21 +#define ECRAM_FN_CTRL_REVERSE 0x22 +#define ECRAM_MAX_CHARGE 0x23 +#define ECRAM_FAN_MODE 0x24 + +#endif diff --git a/src/ec/starlabs/merlin/variants/cezanne/emem.asl b/src/ec/starlabs/merlin/variants/cezanne/emem.asl new file mode 100644 index 0000000..41d650f --- /dev/null +++ b/src/ec/starlabs/merlin/variants/cezanne/emem.asl @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (ECF2, EmbeddedControl, 0x00, 0x100) +Field (ECF2, ByteAcc, Lock, Preserve) +{ + Offset(0x00), + ECMV, 8, // Major Version Number + ECSV, 8, // Minor Version Number + KBVS, 8, // Keyboard Controller Version + ECTV, 8, // Test Version Number + OSFG, 8, // OS Flag + FRMF, 8, // Force Mirror Flag + + Offset(0x0c), + P0MV, 8, // PD Port 0 Major Version + P0SV, 8, // PD Port 0 Minor Version + P1MV, 8, // PD Port 1 Major Version + P1SV, 8, // PD Port 1 Minor Version + + Offset(0x13), + AUDI, 8, // Control Audio + TRAC, 8, // Trackpad Control + + Offset(0x18), + BSEC, 8, // Save to CMOS + KLSE, 8, // Keyboard Backlight State + TPLE, 8, // Trackpad State + FLKE, 8, // Function Lock State + FCLS, 8, // Ctrl Fn Reverse (Make Keyboard Apple-like) + MXCH, 8, // Max Charge Level + FANM, 8, // Fan Mode + + Offset(0x40), + SHIP, 8, // Shipping Mode Flag + + Offset(0x46), + ECPS, 8, // AC & Battery Status + + Offset(0x30), + STEF, 8, // Sensor T Error F + + Offset(0x62), + SSKT, 8, // System Skin Temperature + SENF, 8, // Sensor F + TSHT, 8, // Thermal Sensor High Trip Point + TSLT, 8, // Thermal Sensor Low Trip Point + THER, 8, // Thermal Source + + Offset(0x70), + CPUT, 8, // PECI CPU Temperature + PMXT, 8, // PLMX Temperature + CHAR, 8, // Charger Temperature + + Offset(0x7f), + LSTE, 8, // Lid Status + ECPS, 8, // AC & Battery Status + B1MN, 8, // Battery Model Number Code + B1SN, 16, // Battery Serial Number + B1DC, 16, // Battery Design Capacity + B1DV, 16, // Battery Design Voltage + B1FC, 16, // Battery Last Full Charge Capacity + B1TP, 16, // Battery Trip Point + B1ST, 8, // Battery State + B1PR, 16, // Battery Present Rate + B1RC, 16, // Battery Remaining Capacity + B1PV, 16, // Battery Present Voltage + BPRP, 8, // Battery Remaining Percentage + CPUT, 8, // PECI CPU Temperature + STCD, 8, // Shutdown Code + B1HL, 8, // Battery Health + CWFU, 8, // CW2015 Full + B1CC, 16, // Battery Cycle Count + + Offset(0xb0), + MGO0, 8, // UCSI DS MGO 0 + MGO1, 8, // UCSI DS MGO 1 + MGO2, 8, // UCSI DS MGO 2 + MGO3, 8, // UCSI DS MGO 3 + MGO4, 8, // UCSI DS MGO 4 + MGO5, 8, // UCSI DS MGO 5 + MGO6, 8, // UCSI DS MGO 6 + MGO7, 8, // UCSI DS MGO 7 + MGO8, 8, // UCSI DS MGO 8 + MGO9, 8, // UCSI DS MGO 9 + MGOA, 8, // UCSI DS MGO A + MGOB, 8, // UCSI DS MGO B + MGOC, 8, // UCSI DS MGO C + MGOD, 8, // UCSI DS MGO D + MGOE, 8, // UCSI DS MGO E + MGOF, 8, // UCSI DS MGO F + + Offset(0xc0), + UCSV, 16, // UCSI DS Version + UCSD, 16, // UCSI DS Reserved + CCI0, 8, // UCSI DS CCI 0 + CCI1, 8, // UCSI DS CCI 1 + CCI2, 8, // UCSI DS CCI 2 + CCI3, 8, // UCSI DS CCI 3 + CTL0, 8, // UCSI DS Control 0 + CTL1, 8, // UCSI DS Control 0 + CTL2, 8, // UCSI DS Control 0 + CTL3, 8, // UCSI DS Control 0 + CTL4, 8, // UCSI DS Control 0 + CTL5, 8, // UCSI DS Control 0 + CTL6, 8, // UCSI DS Control 0 + CTL7, 8, // UCSI DS Control 0 + + Offset(0xd0), + MGI0, 8, // UCSI DS MGI 0 + MGI1, 8, // UCSI DS MGI 1 + MGI2, 8, // UCSI DS MGI 2 + MGI3, 8, // UCSI DS MGI 3 + MGI4, 8, // UCSI DS MGI 4 + MGI5, 8, // UCSI DS MGI 5 + MGI6, 8, // UCSI DS MGI 6 + MGI7, 8, // UCSI DS MGI 7 + MGI8, 8, // UCSI DS MGI 8 + MGI9, 8, // UCSI DS MGI 9 + MGIA, 8, // UCSI DS MGI A + MGIB, 8, // UCSI DS MGI B + MGIC, 8, // UCSI DS MGI C + MGID, 8, // UCSI DS MGI D + MGIE, 8, // UCSI DS MGI E + MGIF, 8, // UCSI DS MGI F + + Offset(0xe0), + CCS1, 8, // Cross Point Switch Status 1 + CCS2, 8, // Cross Point Switch Status 2 + TCI1, 8, // TC Input 1 / TCHC Thermal Charge CMD [TODO, Confirm] + TCI2, 8, // TC Input 2 / TCHF Thermal Charge Flag [TODO, Confirm] + PDDT, 8, // PD Det [TODO, Confirm] + PDBD, 8, // B PD Det [TODO, Confirm] + ECWD, 16, // EC Wakeup Delay + ECWE, 8, // EC Wakeup Enable + PDV1, 8, // PD Vol [TODO, Confirm] + PDV2, 8, // B PD Vol [TODO, Confirm] + + // Below are the Thunderbolt Offsets from the shared EC code. There aren't + // use for AMD boards but left for reference. + // + // Offset(0xf7), + // TBTC, 8, // Thunderbolt Command + // TBTP, 8, // Thunderbolt Data Port + // TBTD, 8, // Thunderbolt Data + // TBTA, 8, // Thunderbolt Acknowledge + // TBTG, 16, // Thunderbolt DBG Data +} diff --git a/src/ec/starlabs/merlin/variants/cezanne/events.asl b/src/ec/starlabs/merlin/variants/cezanne/events.asl new file mode 100644 index 0000000..12fdf7c --- /dev/null +++ b/src/ec/starlabs/merlin/variants/cezanne/events.asl @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (_Q01, 0, NotSerialized) // Event: F1 Hot Key +{ + Printf ("EC: F1") +} + +Method (_Q02, 0, NotSerialized) // Event: F2 Hot Key +{ + Printf ("EC: F2") +} + +Method (_Q03, 0, NotSerialized) // Event: F3 Hot Key +{ + Printf ("EC: F3") +} + +Method (_Q04, 0, NotSerialized) // Event: F4 Hot Key +{ + Printf ("EC: F4") +} + +Method (_Q05, 0, NotSerialized) // Event: F5 Hot Key +{ + Printf ("EC: F5") +} + +Method (_Q06, 0, NotSerialized) // Event: F6 Hot Key +{ + Printf ("EC: F6") +} + +Method (_Q07, 0, NotSerialized) // Event: F7 Hot Key +{ + Printf ("EC: F7") +} + +Method (_Q08, 0, NotSerialized) // Event: F8 Hot Key +{ + Printf ("EC: F8") +} + +Method (_Q09, 0, NotSerialized) // Event: F9 Hot Key +{ + Printf ("EC: F9") +} + +Method (_Q10, 0, NotSerialized) // Event: F10 Hot Key +{ + Printf ("EC: F10") +} + +Method (_Q12, 0, NotSerialized) // Event: F12 Hot Key +{ + Printf ("EC: F12") +} + +Method (_Q0A, 0, NotSerialized) // Event: AC Power Connected +{ + Notify (BAT0, 0x81) + Notify (ADP1, 0x80) +} + +Method (_Q0B, 0, NotSerialized) // Event: AC Power Disconnected +{ + Notify (BAT0, 0x81) + Notify (BAT0, 0x80) +} + +Method (_Q0C, 0, NotSerialized) // Event: Lid Closed +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0D, 0, NotSerialized) // Event: Lid Open +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0E, 0, NotSerialized) // Event: SLEEP +{ + Printf ("EC: SLEEP") +} + +Method (_Q13, 0, NotSerialized) // Event: BRIGHTNESS +{ + Printf ("EC: BRIGHTNESS") +} + +Method (_Q20, 0, NotSerialized) // Event: CPU_T +{ + Printf ("EC: CPU_T") +} + +Method (_Q21, 0, NotSerialized) // Event: SKIN_T +{ + Printf ("EC: SKIN_T") +} + +Method (_Q22, 0, NotSerialized) // Event: CHARGER_T +{ + Printf ("EC: CHARGER_T") +} + +Method (_Q30, 0, NotSerialized) // Event: THROT_OFF +{ + Printf ("EC: THROT_OFF") +} + +Method (_Q31, 0, NotSerialized) // Event: THROT_LV1 +{ + Printf ("EC: THROT_LV1") +} + +Method (_Q32, 0, NotSerialized) // Event: THROT_LV2 +{ + Printf ("EC: THROT_LV2") +} + +Method (_Q33, 0, NotSerialized) // Event: THROT_LV3 +{ + Printf ("EC: THROT_LV3") +} + +Method (_Q34, 0, NotSerialized) // Event: THROT_LV4 +{ + Printf ("EC: THROT_LV4") +} + +Method (_Q35, 0, NotSerialized) // Event: THROT_LV5 + Printf ("EC: THROT_LV5") +} + +Method (_Q36, 0, NotSerialized) // Event: THROT_LV6 +{ + Printf ("EC:THROT_LV6") +} + +Method (_Q37, 0, NotSerialized) // Event: THROT_LV7 +{ + Printf ("EC: THROT_LV7") +} + +Method (_Q3B, 0, NotSerialized) // Event: CPU_DN_SPEED + Printf ("EC: CPU_DN_SPEED") +} + +Method (_Q3C, 0, NotSerialized) // Event: CPU_UP_SPEED +{ + Printf ("EC: CPU_UP_SPEED") +} + +Method (_Q3D, 0, NotSerialized) // Event: CPU_TURBO_OFF +{ + Printf ("EC: CPU_TURBO_OFF") +} + +Method (_Q3E, 0, NotSerialized) // Event: CPU_TURBO_ON +{ + Printf ("EC: CPU_TURBO_ON") +} + +Method (_Q3F, 0, NotSerialized) // Event: SHUTDOWN + Printf ("EC: SHUTDOWN") +} + +Method (_Q54, 0, NotSerialized) // Event: Power Button Press +{ + Printf ("EC: PWRBTN") +} + +Method (_Q79, 0, NotSerialized) // Event: USB Type-C +{ + Printf ("EC: USB Type-C") + UCEV() +} + +Method (_Q80, 0, NotSerialized) // Event: Volume Up +{ + Printf ("EC:VOLUME_UP") +} + +Method (_Q81, 0, NotSerialized) // Event: Volume Down +{ + Printf ("EC: VOLUME_DOWN") +} + +Method (_Q85, 0, NotSerialized) // Event: HOME +{ + Printf ("EC: HOME") +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f837263d24e6b642cf33fd2995d8c90529706f6 Gerrit-Change-Number: 62994 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/starlabs/merlin: Correct Q event for CPU DN SPEED
by Felix Held (Code Review) 06 Apr '22

06 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62901 ) Change subject: ec/starlabs/merlin: Correct Q event for CPU DN SPEED ...................................................................... ec/starlabs/merlin: Correct Q event for CPU DN SPEED Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ieea1c8d0923f6ea6b13cf76525c9c4c686a92c40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62901 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/ec/starlabs/merlin/variants/tgl/events.asl 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/variants/tgl/events.asl b/src/ec/starlabs/merlin/variants/tgl/events.asl index 90cde39..5dd4ba9 100644 --- a/src/ec/starlabs/merlin/variants/tgl/events.asl +++ b/src/ec/starlabs/merlin/variants/tgl/events.asl @@ -238,7 +238,7 @@ Printf ("EC: THROT_LV7") } -Method (_Q38, 0, NotSerialized) // Event: CPU_DN_SPEED +Method (_Q3B, 0, NotSerialized) // Event: CPU_DN_SPEED { Printf ("EC: CPU_DN_SPEED") } -- To view, visit https://review.coreboot.org/c/coreboot/+/62901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieea1c8d0923f6ea6b13cf76525c9c4c686a92c40 Gerrit-Change-Number: 62901 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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