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Change subject: mb/google/guybrush: allow MKBP devices and disable TBMC device
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63394/comment/f85ae95e_3ee25923
PS1, Line 9: Enable MKBP (Matrix Keyboard Protocol) interface for all guybrush family
: to use for buttons and switches.
> Why is that better? What problem does it solve?
MKBP is needed to properly inhibit volume keys.
EC has already been switched to sending MKBP events, so some functionality is broken without this change.
Patchset:
PS1:
> Please test `firmware_ECPowerButton` and verify it passes with this CL.
Confirmed passing on guybrush variant.
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Change subject: soc/intel/alderlake: Add support for UFS controller
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62856/comment/73f02c43_694c41fc
PS6, Line 641: s_cfg->UfsEnable[0] = 0; /* UFS Controller 0 is fuse disabled */
> I think so, too.
Oh yeah that is right, UFS is working for ADL-P too, will need to move this out of ADL-N kconfig
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Change subject: drivers/efi: Add EFI variable store option support
......................................................................
Patch Set 12:
(1 comment)
File src/drivers/efi/efivars.c:
https://review.coreboot.org/c/coreboot/+/52564/comment/36df85d7_ea4b616c
PS12, Line 48: c < 0x80
> Isn't char16 is signed? How does this work with negative numbers?
UEFI is weird. Char16 is actually unsigned:
typedef unsigned short CHAR16;
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Change subject: soc/qualcomm/common: verify size of memchipinfo structure
......................................................................
Patch Set 4:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63026/comment/184afc51_4308a8e6
PS4, Line 8:
> Commit message updated
Done
File src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h:
PS3:
> hi yu-ping, […]
Done
File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/63026/comment/2a104380_7f9d9534
PS3, Line 27: if (te->size == mem_chip_info_size((void *)te->blob_address)) {
> Running mem_chip_info_size() before checking that at least the header fits is unsafe, so this needs […]
Done
https://review.coreboot.org/c/coreboot/+/63026/comment/f439819e_e8694c22
PS3, Line 29: (void *)
> nit: cast should be unnecessary.
Done
https://review.coreboot.org/c/coreboot/+/63026/comment/8d277c65_724a1971
PS3, Line 32: if (!mem_chip_addr) {
> No, this is supposed...
Done
File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/63026/comment/ace96193_01b5cd4b
PS4, Line 39: {
> ...to go here. […]
Done
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Change subject: soc/qualcomm/common: verify size of memchipinfo structure
......................................................................
Patch Set 4:
(8 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63026/comment/df6fcb9e_e0df7310
PS4, Line 8:
> This should really say "Fix bugs introduced with CB:59195", because that's mostly what this is about […]
Commit message updated
File src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h:
PS3:
> This file is not qualcomm code, so please add mem_chip_info_size() in a separate patch.
hi yu-ping,
I have updated commit message with: src/commonlib/bsd:
and this changes are created in separate commit id.
File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/63026/comment/c76c33eb_597dbed1
PS3, Line 43: if (mem_chip_info_size(mem_chip_addr) != 0)
> I don't think we need to check this.
Ack
https://review.coreboot.org/c/coreboot/+/63026/comment/c8a5a394_1611af3c
PS3, Line 45: mem_chip_info_size(mem_chip_addr));
> Indentation
Ack
https://review.coreboot.org/c/coreboot/+/63026/comment/6ca3bdd0_d200e539
PS3, Line 180: NULL, 0, 0);
> Can be moved into the previous line.
Ack
File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/63026/comment/861bed8e_59411992
PS4, Line 40: void *mem_region_base = NULL;
> Please declare […]
Ack
https://review.coreboot.org/c/coreboot/+/63026/comment/47bc1a7d_b1f2cbb2
PS4, Line 44: mem_chip_info_size
> Please align with "CBMEM_ID_MEM_CHIP_INFO" above. […]
Ack
https://review.coreboot.org/c/coreboot/+/63026/comment/51409ba6_301dcaa6
PS4, Line 177: /* Attempt to read MEM CHIP information */
> I still asked for a better comment on this on the other patch. Maybe […]
Ack
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Change subject: mb/google/dedede/var/beadrix: Update PCIe and SATA pins for low power consumption
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62776/comment/183514dd_af815d1a
PS3, Line 17:
> Nice, but please document the exact power consumption before and after.
Please capture the power consumption before and after or the power savings numbers in the commit message as Paul mentioned. Otherwise LGTM.
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