coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/cse: Show CSE device slot and function number properly
by Subrata Banik (Code Review) 06 Apr '22

06 Apr '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63406 ) Change subject: soc/intel/common/cse: Show CSE device slot and function number properly ...................................................................... soc/intel/common/cse: Show CSE device slot and function number properly This patch fixes a problem where the `is_cse_devfn_visible` function is unable to show the CSE device slot and function number properly. BUG=b:211954778 TEST=Able to display CSE device slot and function number properly as below: Before: [DEBUG] PCI: 00:16.0 final [WARN ] HECI: CSE device 00.0 is disabled [WARN ] HECI: CSE device 00.0 is disabled [WARN ] HECI: CSE device 00.0 is disabled [WARN ] HECI: CSE device 00.0 is disabled [WARN ] HECI: CSE device 00.0 is disabled With this code changes: [DEBUG] PCI: 00:16.0 final [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I76a634c64af26fc0ac24e2c0bb3a8f397a65d77b --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/63406/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 32b7f20..2444cee 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1012,11 +1012,11 @@ void heci_set_to_d0i3(void) { for (int i = 0; i < CONFIG_MAX_HECI_DEVICES; i++) { - pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(PCH_DEV_SLOT_CSE), PCI_FUNC(i)); - if (!is_cse_devfn_visible(dev)) + pci_devfn_t devfn = PCI_DEVFN(PCH_DEV_SLOT_CSE, i); + if (!is_cse_devfn_visible(devfn)) continue; - set_cse_device_state(dev, DEV_IDLE); + set_cse_device_state(devfn, DEV_IDLE); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/63406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76a634c64af26fc0ac24e2c0bb3a8f397a65d77b Gerrit-Change-Number: 63406 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cse: Allow calling all functions associated with `cse_final`
by Subrata Banik (Code Review) 06 Apr '22

06 Apr '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63405 ) Change subject: soc/intel/cse: Allow calling all functions associated with `cse_final` ...................................................................... soc/intel/cse: Allow calling all functions associated with `cse_final` This patch fixes a problem where `cse_final` only calls into 1 function from available `notify_func` lists. BUG=b:211954778 TEST=Able to execute `cse_final_end_of_firmware` function as part of `cse_final` call. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I04d8c9c1213ddeb9ed85473e62fcca298c0d5172 --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/63405/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index d786a65..32b7f20 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1254,7 +1254,7 @@ { for (size_t i = 0; i < ARRAY_SIZE(notify_data); i++) { if (!notify_data[i].skip) - return notify_data[i].notify_func(); + notify_data[i].notify_func(); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/63405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04d8c9c1213ddeb9ed85473e62fcca298c0d5172 Gerrit-Change-Number: 63405 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: allow MKBP devices and disable TBMC device
by Rob Barnes (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Kenneth Chan, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63394 ) Change subject: mb/google/guybrush: allow MKBP devices and disable TBMC device ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9980f2b5bf10b12f2bd666212b5bce925dc323d Gerrit-Change-Number: 63394 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Diana Zigterman <dzigterman(a)google.com> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 13:29:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/nereid: Configure descriptor for either Type-C or ...
by Sam McNally (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Reka Norman, Paul Menzel, Tim Wawrzynczak. Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63366 ) Change subject: mb/google/brya/var/nereid: Configure descriptor for either Type-C or HDMI ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e Gerrit-Change-Number: 63366 Gerrit-PatchSet: 10 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 06 Apr 2022 13:22:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add support to update descriptor at runtime
by Sam McNally (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Paul Menzel, Reka Norman, Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Angel Pons. Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63365 ) Change subject: soc/intel/alderlake: Add support to update descriptor at runtime ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe Gerrit-Change-Number: 63365 Gerrit-PatchSet: 8 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 13:22:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Shawn C (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Christian Walter, Angel Pons, Arthur Heymans, Michael Niewöhner. Shawn C has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... Patch Set 72: (1 comment) Patchset: PS72: It will fail to locate CBFS via FMAP at runtime if CBFS_SIZE greater than (11MB in this case) default size (10MB): .... FMAP missing or corrupted at offset 0x1410000! Cannot locate primary CBFS .... The offset inside coreboot.rom via hexdump: 01410000 5f 5f 46 4d 41 50 5f 5f 01 01 00 00 00 fe 00 00 |__FMAP__........| 01410010 00 00 00 00 00 02 46 4c 41 53 48 00 00 00 00 00 |......FLASH.....| 01410020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| 01410030 00 00 00 00 00 00 04 00 00 00 40 01 00 00 c0 00 |..........@.....| 01410040 42 49 4f 53 00 00 00 00 00 00 00 00 00 00 00 00 |BIOS............| 01410050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| 01410060 00 00 00 00 40 01 00 00 01 00 52 57 5f 4d 52 43 |....@.....RW_MRC| 01410070 5f 43 41 43 48 45 00 00 00 00 00 00 00 00 00 00 |_CACHE..........| 01410080 00 00 00 00 00 00 00 00 00 00 00 00 00 00 41 01 |..............A.| 01410090 00 02 00 00 46 4d 41 50 00 00 00 00 00 00 00 00 |....FMAP........| 014100a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| 014100b0 00 00 00 00 00 00 00 02 41 01 00 fe be 00 43 4f |........A.....CO| 014100c0 52 45 42 4f 4f 54 00 00 00 00 00 00 00 00 00 00 |REBOOT..........| fmap.fmd: FLASH@4261412864 0x02000000 { BIOS@20971520 12582912 { RW_MRC_CACHE@0 0x10000 FMAP@65536 0x200 COREBOOT(CBFS)@66048 12516864 } } Any idea how to fix it? -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 72 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shawn C <citypw(a)hardenedlinux.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Wed, 06 Apr 2022 13:21:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/intelp2m: Add support for Alder Lake H macro generation
by Paul Menzel (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Michał Żygowski, Maxim Polyakov, Michał Kopeć. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63403 ) Change subject: util/intelp2m: Add support for Alder Lake H macro generation ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5871394bcb0636c2c803607ffb129441aa934417 Gerrit-Change-Number: 63403 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Wed, 06 Apr 2022 13:17:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: Add support for Alder Lake chips detection and GPIOs
by Paul Menzel (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Michał Żygowski, Michał Kopeć, Stefan Reinauer. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63374 ) Change subject: util/inteltool: Add support for Alder Lake chips detection and GPIOs ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6 Gerrit-Change-Number: 63374 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Wed, 06 Apr 2022 13:16:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/*:[WIP] enable FSP-M decompression at execution
by Paul Menzel (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Rizwan Qureshi, Tim Wawrzynczak. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63397 ) Change subject: soc/intel/*:[WIP] enable FSP-M decompression at execution ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63397/comment/3966e514_af9ebfec PS1, Line 9: FSP-M is compressed and is not more XIP. Hence remove the FSP_M_XIP config. : The FSP-M decompression requires more CAR memory. Increase CAR region size : to 2.5 MB. As per the system adress MAP we will be breaching the LAPIC base : address and HPET addresses hence rebase the CAR memory to somewhere safe. : Also increase the required stack szie Please reflow for 72 characters per line. https://review.coreboot.org/c/coreboot/+/63397/comment/b77fdf38_9a455096 PS1, Line 13: szie size -- To view, visit https://review.coreboot.org/c/coreboot/+/63397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2a20b0e81a116a81170363f7b93c845cde863f8 Gerrit-Change-Number: 63397 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 06 Apr 2022 13:13:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake:[WIP] enable FSP-M compression
by Paul Menzel (Code Review) 06 Apr '22

06 Apr '22

Attention is currently required from: Rizwan Qureshi, Tim Wawrzynczak. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63398 ) Change subject: soc/intel/alderlake:[WIP] enable FSP-M compression ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63398/comment/02268345_5e8ff88c PS1, Line 10: SinceLLC Missing space? https://review.coreboot.org/c/coreboot/+/63398/comment/9dc74399_9ddbf4a3 PS1, Line 12: * Enable FSP-M compression at build time What algorithm is used? https://review.coreboot.org/c/coreboot/+/63398/comment/d9769d7c_a7a59874 PS1, Line 14: Rebase rebase https://review.coreboot.org/c/coreboot/+/63398/comment/cb462915_0b0648e9 PS1, Line 15: What is the size without and with compression? What is the load time difference? -- To view, visit https://review.coreboot.org/c/coreboot/+/63398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie16e97b9445f2fe44b403bc03de55fbfb4de4da9 Gerrit-Change-Number: 63398 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 06 Apr 2022 13:12:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2022